JPH0369550B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention, when a pachinko ball flies into a continuous winning opening, starts to maintain a state that increases the winning probability of a winning device within a predetermined time, and To provide a pachinko machine which starts the winning probability increasing state again from the beginning when a pachinko ball flies into the continuous winning hole again during the winning probability increasing state of the device.

(Prior Art) Conventionally, some pachinko machines change a winning device based on winning balls to generate a specific state in which the probability of winning increases. An example of this pachinko machine is the pachinko machine disclosed in Japanese Patent Laid-Open No. 112571/1983. The pachinko machine disclosed in this publication has a plurality of types of specific winning holes and a winning device arranged on the game board from which pachinko balls are shot, and this winning device has a continuous winning hole and a winning device that can be opened and closed. A movable piece, an electric drive unit that drives the movable piece to open and close, and an operation circuit that operates the electric drive unit are provided.

There are two types of special winning holes, one for opening and closing the movable piece once and the other for opening and closing the movable piece twice by operating the electric drive part by the operation circuit. When the hit pachinko ball enters any of the specific winning slots, the opening and closing of the movable piece makes it easier to enter the winning device, so that the specific state occurs. In addition, when a pachinko ball enters the winning device and further enters the continuous winning slot due to the occurrence of a specific state based on a winning in the specific winning opening, the electric drive unit opens and closes the movable piece 18 times to win the specific winning opening. Generates a specific state that is different from the case based on winnings. As a result, rights advantageous to the player are continuously generated.

In addition, the above bulletin states that during the occurrence of a specific condition based on a winning in a specific winning opening, if a prize is won in a specific winning opening different from the specific winning opening, and during the occurrence of a specific condition based on a winning in a continuous winning opening, The process for winning a prize in the winning slot is not disclosed.

(Problem to be Solved by the Invention) For this reason, when a pachinko ball hit on the game board successively wins a specific winning hole, the electric drive unit opens and closes the movable piece unlimitedly by the operating circuit. Or, if a specific winning slot is won while a specific state based on a winning slot is occurring, the continuous opening/closing cycle of the movable piece will be disrupted, resulting in the occurrence of rights advantageous to the player. There was a problem that caused inconveniences such as the content of the text becoming unclear. Therefore, an object of the present invention is to provide a pachinko machine equipped with means for solving such problems.

(Means for Solving the Problems) Therefore, in order to achieve such an object, the present invention has an electric drive unit (solenoid) that, during an operation based on a winning in the specific winning opening, detects the specific winning opening that is different from the winning opening. When a prize is won in a winning opening, the short operating time of the electric drive unit is extended into a long operating time to give priority to the operation based on winning in the different specific winning opening;
The operation circuit has a function of disabling the operation of the electric drive unit based on the winning of the specific winning opening when the electric driving unit wins the specific winning opening while operating based on the winning of the continuous winning opening. The configuration includes a timing circuit (reset timing circuit) for

(Function) Since the present invention is configured as described above, when pachinko balls successively win in a specific winning hole, the timing circuit retracts the short operating time of the electric drive unit into a long operating time and By prioritizing the operation based on winning in the winning opening, it is possible to invalidate the operation of the electric drive unit based on winning in the specific winning opening, which has a short operating time.

On the other hand, if the electric drive unit wins a prize in the specific winning hole while operating based on a winning in the continuous winning hole,
The timing circuit prevents the continuous opening/closing period of the movable piece from being disrupted by disabling the operation of the electric drive unit based on the winning of the specific winning opening.

(Example) An embodiment of the present invention will be described below.

In FIG. 1, 1 is a winning device according to the present invention, and in the center of this winning device 1 are pivots 1a, 1b.
Guide vanes 1c and 1d are provided as movable pieces that open in the direction of picking up pachinko balls from the starting point. That is, the guide vane 1c rotates counterclockwise until it becomes as horizontal as possible, and the guide vane 1d rotates clockwise until it becomes as horizontal as possible. The guide vanes 1c, 1d are linked with rods 2c, 2d forming part of solenoids 2a, 2b as electric drive units, as shown in FIG. The guide vanes 1c, 1d are opened by driving the solenoids 2a, 2b.

At the bottom of the winning device 1, partition plates 3, 3 are set up, and between the partition plates 3, 3 is a continuous winning opening 4, and this continuous winning opening 4 has a guide as a continuous winning detector. An 18-times operation winning ball switch 5 is provided to cause the blades 1c and 1d to operate 18 times. In addition to this, two other specific winning holes (not shown) are provided, and as shown in FIG. A one-time operation winning ball switch 6 is provided to perform the one-time operation of 1d, and the other two specific winning holes are equipped with guide vanes 1c and 1 as specific winning detectors, as shown in FIG.
A two-time action winning ball switch 7 is provided for performing the two-time action of d. On the front of the winning device 1, there is a light emitting diode 8 as part of the notification means.
A to 8g are arranged.

FIG. 3 shows a control circuit for the solenoids 2a and 2b. It consists of an operating circuit as the main component and a reset timing circuit 15 as a timing circuit. Further, 16 is a clock oscillation circuit, 17 is a light emitting diode blinking circuit as a notification means, and 18 is a sound effect generation circuit as a notification means.

The configuration and function of each of these circuits will be explained below.

The flip-flop circuit 9 has set terminals S0,
S1, S2, S3 and output terminals Q0, Q1, Q
2, Q3 and reset terminals R0, R1, R2, R
3 and a ground terminal E0, and here,
Set terminal S3, reset terminal R3, output terminal Q
3 is not used. Power supply voltage VDD is connected to set terminals S0, S1 and Schmitt circuit 11 via a group of resistors. The power supply voltage VDD is
The high potential side, and each switch 6, 7, 5 is the third
As shown in the figure, when in the open state, set terminals S0, S1, and S2 are at H level input. The set terminal S0 changes from H to L when the switch 6 is closed, the set terminal S1 changes from H to L when the switch 7 closes, and the set terminal S2 changes from H to L when the switch 5 is closed. When the voltage is changed, the voltage changes from H to L. Each output terminal Q0~Q
2 is set to L output when each set terminal S0 to S2 is H, and when each set terminal S0 to S2 is L,
It is said to be H output. 19 and 20 are OR circuits. The OR circuit 19 outputs an H signal when at least one of the output terminals Q0 to Q2 of the flip-flop 9 is H.
These OR circuits 19 and 20 have the function of inhibiting the output of each component of the reset timing circuit 15. The Schmitt circuit 11 has an OR gate 21 and a reset release control circuit 1 that controls the 8-bit binary counter circuit 10.
3 consists of NAND gates, NAND gate 1
The output of the Schmitt circuit 11 is input to one input terminal of the NAND gate 13, and the output of the OR circuit 19 is input to the other input terminal of the NAND gate 13 via the delay circuit 12. The delay circuit 12 is composed of a group of resistive capacitors, and the function of the delay circuit 12 will be explained together with the configuration of the 8-bit binary counter circuit 10.

The 8-bit binary counter circuit 10 has reset terminals Ra, Rb and output terminals Q0a to Q3a, Q.
0b to Q3b, and input terminals Ea and Eb. The input terminal Ea is connected to a clock oscillation circuit 16 that generates a clock signal as shown in FIG. 4, and each of the output terminals Q0a to Q3a generates a rectangular signal as shown in FIG. There is.

The output terminal Q0a has a period twice that of the clock signal, has a function of outputting when the first clock signal is input, and has the function of outputting when the first clock signal is input.
has a period four times the period of the clock signal and has a function of outputting when the second clock signal is input, and the output terminal Q2a has a period eight times the period of the clock signal. It has a function of outputting when the fourth clock signal is input, and the output terminal Q3a has a period 16 times the period of the clock signal, and outputs when the eighth clock signal is input. It has a function to output to.

The output of the output terminal Q3a is input to the input terminal Eb, and the output terminal Q0b has a period twice that of the rectangular signal from the output terminal Q3a, as shown in FIG. The output terminal Q1b is not used here, and the output terminal Q2b has a function of outputting a rectangular signal with a period eight times that of the rectangular signal from the output terminal Q3a. It has an output terminal Q3
It has a function of outputting when the fourth output signal of the rectangular signal from a is input, and the output terminal Q3b
has a period 16 times that of the rectangular signal from the output terminal Q3a, has a function of outputting when the eighth output signal of the rectangular signals from the output terminal Q3a is input, and outputs the signal from the output terminal Q3b. The output of is inputted to the input terminal CP of the shift register 14 via the inverter element 22.

The shift register 14 has the input terminal CP, the reset terminal R, the power supply potential terminal D, the output terminal Q0,
Q1 and Q2, and the reset terminal R has
The output from the NAND gate 13 is input, and the power supply potential terminal D is connected to the power supply VDD.

The output terminal Q0 of the shift register 14 receives the rectangular signal from the output terminal Q3a, as shown in FIG.
It has a cycle that is 32 times longer and has a function of outputting when the 16th rectangular signal from output terminal Q3a is input, but it is not used here, and output terminal Q1 is It has a period 64 times that of the rectangular signal from terminal Q3a, and output terminal Q3
It has a function of outputting when the 32nd rectangular signal from a is input, and the output terminal Q2 is not used here.

The reset terminal Ra of the 8-bit binary counter circuit 10 is connected to the delay circuit 12, and the output from the OR circuit 19 is input to the reset terminal Ra with a delay of 0.5 seconds.
This reset terminal Ra opens the output from the output terminal Q0a when its input is L.
This inhibits the output of Q0a when its input is H.

The output of the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit 10, and when the input to the reset terminal Rb is H, the output from the output terminal Q0b is prohibited, and the input to the reset terminal Rb is disabled. When is L, output terminal Q0b
The output from is to be released. The input to the reset terminal Rb is set to L at the same time as the input to the reset terminal Ra becomes H.

The light emitting diode blinking circuit 17 includes two shift registers 23 and 24, an OR circuit group 25, a light emitting diode drive circuit 26, and a light emitting diode group 27.
It is roughly composed of.

The shift register 23 has input terminals D and CP, a reset terminal R, and output terminals Q0 to Q3, and the output from the output terminal Q2 of the flip-flop circuit 9 is input to the input terminal CP.
Output terminal Q0 of bit binary counter circuit 10
The output from a is input.

The outputs from the output terminals Q0 to Q3 of the shift register 23 are fed back to the input terminal D of the shift register 23 via the NOR circuit 28, and the output from the output terminal Q0 is input to the OR circuit 29 and the OR circuit 35. The output from the output terminal Q1 is input to the OR circuit 30 and the OR circuit 34, the output from the output terminal Q2 is input to the OR circuit 31 and the OR circuit 33,
The output from the output terminal Q3 is input to the OR circuit 32.

The light emitting diode drive circuit 26 has an input terminal I0.
~ I6 and output terminals Q0 to Q6, the OR circuit 29 controls the output from the output terminal Q0, the OR circuit 30 controls the output from the output terminal Q1, and the OR circuit 29 controls the output from the output terminal Q1. The circuit 31 controls the output from the output terminal Q2, the OR circuit 32 controls the output from the output terminal Q3, and the OR circuit 33 controls the output from the output terminal Q4. The OR circuit 34 controls the output from the output terminal Q5, the OR circuit 35 controls the output from the output terminal Q6, and the light emitting diodes 8a and 8g control the output from the output terminal Q0 of the shift register 23. The light-emitting diodes 8b and 8f are controlled to blink by the output from the output terminal Q1 of the shift register 23, and the light-emitting diodes 8c and 8e are blinked by the output from the output terminal Q2 of the shift register 23. 8d is controlled to blink by the output from the output terminal Q3 of the shift register 23, and the light emitting diode group 27 is configured so that each diode row is blinked from the top and bottom toward the center as shown in FIG. Noah Gate 28 is
Each diode array has a function of repeating the blinking state from the top to the center from the beginning after the blinking state is completed.

Note that the reset terminal R of the shift register 23 is
When the input is H, the light emitting diode group 27 has a function of inhibiting output from the output terminals Q0 to Q3 of the shift register 23, and when the output from the output terminal Q2 of the flip-flop circuit 9 is H, , all lights are turned off.

The shift register 24 has reset terminals Ra and Rb.
, input terminals Ca, Cb, Db and output terminals Q0a~Q
3a, Q0b to Q2b.

The reset terminals Ra and Rb of the shift register 24 are inputted with the output of a NOR gate 36, which will be described later, and the output from the output terminal Q2 of the flip-flop circuit 9 is inputted into the NOR gate 36. When the output from the output terminal Q2 of the NOR gate 36 is L, the output becomes H, and the shift register 24 is reset. When the output from the output terminal Q2 of the flip-flop circuit 9 is H, the output of the NOR gate 36 becomes H. The output becomes L, and the reset of the shift register 24 is released. Therefore, when the shift register 23 is in the reset release state, the shift register 24
is in the reset state, and when the shift register 23 is in the reset state, the shift register 24 is in the reset state.
is set in a reset release state.

The Schmitt circuit 11 is connected to the input terminals Ca and Cb of the shift register 24 via an inverter element 37.
The output from is input. shift register 2
4 output terminals Q0a to Q3a, Q4b to Q6b
are connected to the OR circuits 29 to 35 in order, respectively, and the output from the output terminal Q3a is connected to the input terminal
Db, the output terminals Q4b to Q6b receive and output the output from the output terminal Q3a, and the output from the output terminal Q6b is fed back to the other input terminals of the OR gate 21 forming a part of the Schmitt circuit 11. has been entered.

When the output from the output terminal Q6b of the shift register 24 is L and the input terminal of the OR gate 21 is H, the output of the OR gate 21 becomes H, and the output from the output terminal Q6b of the shift register 24 becomes L. When one input terminal of the OR gate 21 is L, the output becomes L, and when the output of the output terminal Q6b of the shift register 24 is H, regardless of whether the input to the one input terminal of the OR gate 21 is L or H. The output becomes H.

Or Gator 21 is 18 times winning ball switch 5
When is opened and closed once, the output changes from H to L, and the output terminal Q0a of the shift register 24 changes from L to H. Along with this, the light emitting diode 8
A is now lit.

When the 18-time operation winning ball switch 5 is repeatedly opened and closed 8 times, the light emitting diodes 8a to 8g are turned on in this order. When all the light emitting diodes 8a to 8g are turned on, the output from the output terminal Q6b of the shift register 24 becomes H, and the inputs of the other input terminals of the OR gate 21 become H, so that the 18th operation winning ball switch 5 becomes 8. After opening and closing the 18-time winning ball switch 5, the output of the OR gate 21 becomes H, and the light-emitting diode group 27 is no longer lit.

The reset timing circuit 15 is the AND circuit 3
8, a NAND circuit 39, a NOR gate 40, an inverter element 41, a NOR gate 42, an AND circuit 43, and a NOR circuit 44. The AND circuit 38 includes an 8-bit binary counter circuit 1
The outputs of output terminal Q1a and output terminal Q3a of 0 are input. The output from the AND circuit 38 and the output from the output terminal Q0b of the 8-bit binary counter circuit 10 are input to the NAND circuit 39. The output from the NAND circuit 39 and the output from the OR circuit 20 are input to the NOR gate 40 . The inverter element 4 is connected to the NOR gate 42.
1, the output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q2 of the flip-flop circuit 9 are inputted. The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q1 of the shift register 14 are input to the AND circuit 43, and the NOR gate 40 is input to the NOR circuit 44.
, the outputs of the NOR gate 42, the AND circuit 43, and the power supply voltage are input. Noah circuit 44
The output from the flip-flop circuit 9 is input to each reset terminal R0, R1, R2, and when the output from the NOR circuit 44 is L, the output from each output terminal Q0 to Q2 of the flip-flop circuit 9 is prohibited. When the output of the NOR circuit 44 is H, the outputs from the respective output terminals Q0 to Q2 of the flip-flop circuit 9 are opened. Noah circuit 44
When the power supply voltage of the NOR gates 40 and 42 and the AND circuit 43 is L, the output becomes H, and the flip-flop circuit 9 is released from reset.

The AND circuit 38, the NAND circuit 39, and the NOR gate 40 are used as a reset timing circuit that operates the solenoids 2a and 2b once, and the inverter element 41 and the NOR gate 42 serve as a reset timing circuit that operates the solenoids 2a and 2b twice. The AND circuit 43 is a reset timing circuit 15 that operates the solenoids 2a and 2b 18 times. The time required for two operations of the solenoids 2a and 2b is set to be longer than the time required for one operation.

The output of the NOR gate 40 is always L when the outputs of the output terminals Q1 and Q2 of the flip-flop circuit 9 are H, and the output of the NOR gate 42 is always L when the output from the output terminal Q2 of the flip-flop circuit 9 is H. Its output is set to be L.

The solenoids 2a and 2b are connected to the switching circuit 4.
5 and 46, respectively, and the switching circuit 4
5 and 46 are connected to OR gates 47 and 48, respectively, and OR gates 47 and 48 are connected to the output terminal Q0b of the 8-bit binary counter circuit 10. The output terminal Q0b of the 8-bit binary counter circuit 10 is connected to an AND circuit 49, and the NOR gate 36 and the AND circuit 49 have a function of controlling the sound effect generation circuit 18. , here solenoids 2a and 2b are
A sound effect is generated during the 18th movement. 50 is a display circuit that displays that the solenoids 2a and 2b are operating 18 times, and a lamp 5
2 and an AND circuit 53.

Next, the effect will be explained.

() The 1st action winning ball switch 6, the 2nd action winning ball switch 7, and the 18th action winning ball switch 5 are all open, and the flip-flop circuit 9
When the inputs of the set terminals S0, S1, and S2 of the OR gate 21 are H, the input of one input terminal of the OR gate 21 is H, and the input of the other input terminal is L.

Output terminals Q0 to Q2 of flip-flop circuit 9
The output of is L, and the output of OR gate 21 is H, so H is input to one input terminal of NAND gate 13, L is input to the other input terminal, and H is output from NAND gate 13. be done. Therefore, the input to the reset terminal Ra of the 8-bit binary counter circuit 10 is set to L, and the input to the reset terminal Rb of the 8-bit binary counter circuit 10 is set to L.
The input of is set to H. Therefore, the reset of the reset terminal Ra of the 8-bit binary counter circuit 10 is released, the output from the output terminal Q0a is open, and the clock oscillation circuit 16
The clock signal is outputted from the output terminal Q0a, and the light emitting diode group 27 repeatedly blinks from the top to the center from the top to the center as shown in FIG.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset, output from the output terminals Q0b to Q3b is prohibited, and the solenoids 2a and 2b are not driven.

() The winning ball switch 6 is closed once,
When the input to the other input terminal of the OR gate 21 is L.

When the one-time winning ball switch 6 is closed, the set terminal S0 of the flip-flop circuit 9 is changed from H to L, and the output from the output terminal Q0 is changed from L to H. The output is sent to the reset terminal of the 8-bit binary counter circuit 10 via the delay circuit 12.
The signal is input to Ra and is also input to other input terminals of the NAND gate 13. On the other hand, ORGATE 21 is
At this time, H is output, and the output is input to one input terminal of the NAND gate 13, and from the NAND gate 13, L is input to the reset terminal Rb of the 8-bit binary counter circuit 10. still,
The input to the reset terminal Rb is set to low when the output terminal Q0 of the flip-flop circuit 9 changes from low to high.
It is said that Output terminal Q of flip-flop circuit 9
When the output from 0 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit 12 of the delay circuit 12, and output from the output terminals Q0a to Q3a is prohibited. . On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset after a delay time elapses due to the time constant of the integrating circuit, and a rectangular signal as shown in FIG. 5 is output from the output terminals Q0b to Q3b. Output. Then, the output terminal Q0b of the 8-bit binary counter circuit 10
The rectangular signal output from the OR gates 47, 4
8 and switching circuits 45 and 46 to the solenoids 2a and 2b, and simultaneously to the NAND circuit 39 and the AND circuit 49.

Therefore, the solenoids 2a and 2b are driven, but due to the one-time operation reset timing circuit of the AND circuit 38, NAND circuit 39, and NOR gate 40, when L is output from the NAND circuit 39, L is output from the NOR circuit 44. The reset terminals R0, R1, and R2 of the flip-flop circuit 9 are reset (see FIG. 6).

Therefore, output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven for only 0.5 seconds as shown in FIG.

() The winning ball switch 7 is closed twice,
When the input to the other input terminal of the OR gate 21 is L.

When the double-operation winning ball switch 7 is closed, the set terminal S1 of the flip-flop circuit 9 is changed from H to L, and the output from the output terminal Q1 is changed from L to H. The output thereof is inputted to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, as in the case () above, and is also inputted to the other input terminals of the NAND gate 13. On the other hand, the OR gate 21 is outputting H at this time, and its output is input to one input terminal of the NAND gate 13, and from the NAND gate 13, it is output to the reset terminal of the 8-bit binary counter circuit 10.
L is input to Rb. Also at this time, the input to the reset terminal Rb is set to L when the output from the output terminal Q1 of the flip-flop circuit 9 changes from L to H.

When the output from the output terminal Q1 of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 is connected to the delay circuit 12.
The differential circuit 12 resets the output terminals for a time constant, and outputs from the output terminals Q0a to Q3a are prohibited. In addition, an 8-bit binary counter circuit 10
The reset terminal Rb of the
A rectangular signal as shown in FIG. 5 is output from the output terminals Q0b to Q3b.

Therefore, the solenoids 2a and 2b are driven, but due to the two-time reset timing circuit of the inverter element 41 and the NOR gate 42, when the NOR gate 42 outputs an H level, the NOR circuit 44 outputs an L level, and the flip-flop circuit The reset terminals R0, R1, and R2 of 9 are reset (see FIG. 7).

Therefore, the output terminals Q0, Q1 . The output from Q2 is inhibited, and solenoids 2a and 2b are driven only twice for 0.8 seconds each, as shown in FIG. that's all,
The first or second movement of the guide vanes 1c and 1d
state.

() When the one-time action winning ball switch 6 and the two-time action winning ball switch 7 are closed at the same time, or when the two-time action winning ball switch 7 is closed while the solenoids 2a and 2b are being driven once.

When the one-time action winning ball switch 6 and the two-time action winning ball switch 7 are closed at the same time, the flip-flop circuit 9 is closed as in () and ().
The output terminals Q0 and Q1 of the 8-bit binary counter circuit 10 go from L to H, and this output H passes through the OR circuit 19 and then is sent to the reset terminal Ra of the 8-bit binary counter circuit 10 and other input terminals of the NAND gate 13 via the delay circuit 12. , and the output H that has passed through the OR circuit 20 is input to the other input terminals of the NOR gate 40. As a result, the output of the NOR gate 40 becomes L, and this output L does not depend on the output terminals Q1a, Q3a, Q0b of the 8-bit binary counter circuit 10.

Also, during one drive of the solenoids 2a and 2b,
When the two-time winning ball switch 7 is closed, the output terminal Q1 of the flip-flop circuit 9 becomes L at the point when the two-time winning ball switch 7 is closed.
becomes H. As a result, the output of the NOR gate 40 is held at L from this point on, and similarly to the above, the output L of the NOR gate 40 does not depend on the output terminals Q1a, Q3a, Q0b of the 8-bit binary counter circuit 10.

Therefore, the start of a short operating time (opening and closing once) of the electric drive is compared to a long operating time (opening and closing twice).
In other words, the reset timing circuit 15 incorporates the short operating time of the electric drive unit into the long operating time, gives priority to the operation based on winning a prize in the specific winning opening during the long operating time, and It is possible to invalidate the operation of the electric drive unit based on winning a prize in a specific winning opening.

On the other hand, even if the OR gate 19 is outputting H and the one-time winning ball switch 6 and the two-time winning ball switch 7 are closed,
The output H is input to one input terminal of the NAND gate 13, and from the NAND gate 13, it is input to the reset terminal Rb of the 8-bit binary counter circuit 10.
L is input to . Therefore, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset, and a rectangular signal as shown in FIG. 5 is output from the output terminals Q0b to Q3b. The rectangular signal output from the output terminal Q0b of the 8-bit binary counter circuit 10 is input to the solenoids 2a and 2b via the OR gates 47 and 48 and the switching circuits 45 and 46, and at the same time is input to the solenoids 2a and 2b. is input.

Therefore, the solenoids 2a and 2b are driven, but when an H is output from the NOR gate 42 by the one-time operation reset timing circuit and the two-time operation reset timing circuit, the NOR circuit 44
L is output from the flip-flop circuit 9, and the reset terminals R0, R1, and R2 of the flip-flop circuit 9 are reset (see FIG. 7). Therefore, the output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the reset terminal Rb of the 8-bit binary counter circuit 10 becomes H, and the solenoid 2a, 2b is reset. is driven only twice for 0.8 seconds each as shown in FIG.

Furthermore, while the solenoids 2a and 2b are driven once or twice, the flip-flop circuit 9
Since the output from the output terminal Q0 or output terminal Q1 is H, even if the one-time winning ball switch 6 and the two-time winning ball switch 7 are closed during this period, it will be invalid.

() 18th operation When winning ball switch 5 is closed.

When the 18th operation winning ball switch 5 is closed, L is momentarily input to one input terminal of the OR gate 21, and at this time, L is input from the output terminal Q6b of the shift register 24 to the other input terminal of the OR gate 21. is input, and L is output from the OR gate 21. The output is input to one input terminal of the NAND gate 13, and at this time, if the guide vanes 1c and 1d are in the middle of the first and second operations, the NAND gate 1
Since H is input to the other input terminal of 3, the NAND gate 13 momentarily outputs H, and the output is sent to the 8-bit binary counter circuit 1.
0 reset terminal Rb.

Therefore, the reset terminal Rb is instantaneously reset, and the output from the output terminal Q0b of the 8-bit binary counter circuit 10 is prohibited. Therefore, if the 18th movement winning ball switch 5 is closed in the middle of the 1st and 2nd movement, the 1st and 2nd movement will be played at that point.
The rotation ends immediately. Also, or gate 21
The output from the flip-flop circuit 9 is input to the set terminal S2 of the flip-flop circuit 9, and an H level is output from the output terminal Q2. The output H is transmitted through the OR circuit 20, the OR circuit 19, and the delay circuit 12 to the (), ()
Similarly, it is input to the reset terminal Ra of the 8-bit binary counter circuit 10, and the NAND gate 1
3 is input to the other input terminal. On the other hand, at this time, the 18th operation winning ball switch 5 has been opened,
H is input to one input terminal of the OR gate 21,
The OR gate 21 outputs H, one input terminal of the NAND gate 13 is set to H, and the output of L from the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit 10.

In this case, as in () and () above, the input of the reset terminal Rb is connected to the flip-flop circuit 9.
When the output from the output terminal Q2 changes from L to H, it is set to L.

Therefore, the 8-bit binary counter circuit 10
The reset terminal Ra of is reset, and the output terminal Q
Outputs from 0a to Q3a are prohibited. Also, 8
Reset terminal of bit binary counter circuit 10
Rb is reset and output terminal Q0b~
A rectangular signal as shown in FIG. 5 is output from Q3b.

Therefore, the solenoids 2a and 2b are driven, but due to the 18-time operation reset timing circuit of the AND circuit 43, when the AND circuit 43 outputs H, the NOR circuit 44 outputs L, and the flip-flop circuit 9 Reset terminal R0, R
1 and R2 are reset (see FIG. 8).

Therefore, output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven 18 times for 0.8 seconds each as shown in FIG. In this way, the 18 opening and closing operations of the guide members 1c and 1d are performed in the second
state.

() 1 during 18 operations of solenoids 2a and 2b
When the two-time action winning ball switch 6 or the two-time action winning ball switch 7 is closed.

When the solenoids 2a and 2b are operating 18 times, that is, when the guide vanes 1c and 1d are operating 18 times, the OR circuit 1 is
The output of 9 is H. Therefore, even if there is a win in the 1st or 2nd operation to the specific winning hole during the 18th operation, the output of the OR circuit 19 remains H and does not change.
During the 18 operations, the reset terminal Rb of the binary counter circuit 10 is not reset by closing the one-time winning ball switch 6 and the two-time winning ball switch 7. In other words, during the 18 operations of the guide vanes 1c and 1d, the reset timing circuit 15 disables the operation of the solenoids 2a and 2b based on the 1-time winning ball switch 6 and the 2-time winning ball switch 7, thereby continuously This prevents the opening/closing cycle (0.8 seconds) of the movable piece from being disturbed.

In addition, since the output from the NOR circuit 44 is input to the reset terminals R0, R1, and R2 of the flip-flop circuit 9, even if there is a win in the 1st and 2nd operation from a specific winning hole during the 18th operation. ,
At the end of the 18th operation, the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 are all reset, so after the 18th operation is completed, the 1st and 2nd prizes due to winnings in the 1st and 2nd operations during the 18th operation are No action is taken.

() 18th operation When winning ball switch 5 is closed.

L is momentarily input to the input terminal of the OR gate 21 by closing the 18-time winning ball switch 5, and L is momentarily output from the OR gate 21 in response. The output is input to one input terminal of the NAND gate 13, and at this time, since H is input to the other input terminal of the NAND gate 13, H is momentarily output from the NAND gate 13, and the output is 8 bits. Binary counter circuit 1
0 reset terminal Rb. Therefore,
The reset terminal Rb is momentarily reset, and the output terminal Q0b of the 8-bit binary counter circuit 10 is reset.
output is momentarily inhibited (see Figure 9).

Therefore, 8-bit binary counter circuit 1
The 18-time operation rectangular signal from output terminal Q0b of
As shown in FIG. 9, the process starts again from the beginning.

The H output from the output terminal Q2 of the flip-flop circuit 9 is further input to the reset terminal R of the shift register 23 and to the NOR gate 36. Therefore, the output from the set terminals S0 to S3 of the shift register 23 is prohibited, and the light emitting diodes 8a to 8g are all turned off, while the NOR gate 36 outputs L, and the output is sent to the reset terminals Ra, S3 of the shift register 24. The signal is input to Rb, and the reset terminals Ra and Rb are released from reset. At this time, the input terminals Ca and Cb of the shift register 24 are connected to the input terminals Ca and Cb through the inverter element 37.
The output from the OR gate 21 accompanying the closing of the 18th operation winning ball switch 5 is input, and H is output from the output terminal Q0a of the shift register 24. Along with this, the light emitting diode 8a is turned on. Similarly, the solenoids 2a and 2b are
When the 18th operation winning ball switch 5 is repeatedly opened and closed 8 times during the 18th operation, the light emitting diode 8 is activated in this order.
b to 8g are lit.

When all the light emitting diodes 8a to 8g are turned on, H is output from the output terminal Q6b of the shift register 24, and the inputs of the other input terminals of the OR gate 21 are set to H. Therefore, after the 18-time winning ball switch 5 has been opened and closed 8 times, the output of the OR gate 21 is set to H regardless of whether the 18-time winning ball switch 5 is opened or closed, and the light emitting diode group 27 is not lit thereafter. do not have.

In addition, in the winning probability increase state, if the winning ball switch 5 does not win the prize after 18 operations, the guide blade operates once and twice as described above, and the winning probability ends after 18 operations, but the winning ball does not reach the winning area of the winning device. The game may end when a predetermined number of pachinko balls (for example, 10 balls) win.

(Effect of light emitting light) As is clear from the above description, in the present invention, when a pachinko ball consecutively wins a prize in a specific winning hole, the timing circuit retracts the short operation time of the electric drive unit into a long operation time and Since priority is given to the operation based on winning to the specific winning opening, the operation of the electric drive unit based on winning to the specific winning opening with a short operation time is disabled. As a result, there is no need to open and close the movable piece indefinitely based on a winning in a specific winning opening, and a fair pachinko machine can be provided.

On the other hand, if the electric drive unit wins a prize in the specific winning hole while operating based on a winning in the continuous winning hole,
The timing circuit prevents the continuous opening/closing period of the movable piece from being disrupted by disabling the operation of the electric drive unit based on the winning of the specific winning opening. Thereby, the generation of rights advantageous to the player can be clearly displayed, the rights can be effectively utilized, and the player's desire to play is improved.

[Brief explanation of drawings]

FIG. 1 is a schematic front view showing one embodiment of the present invention, FIG. 2 is a schematic perspective view showing one embodiment of the present invention, FIG. 3 is a control circuit diagram used in the present invention, and FIG. 5 is a signal waveform diagram of the clock signal output from the 8-bit binary counter circuit, FIG. 6 is a series of signal waveform diagrams when the solenoid is made to open and close once, and FIG. , a series of signal waveform diagrams when the solenoid is made to open and close twice, Figure 8 is a series of signal waveform diagrams when the solenoid is made to open and close 18 times, and Figure 9 is a series of signal waveform diagrams when the solenoid opens and closes 18 times. It is a series of signal waveform diagrams when the 18-time operation winning ball switch is closed during operation. 1... Winning device, 1c, 1d... Movable piece (guide vane), 2a, 2b... Electric drive unit (solenoid), 4... Continuous winning opening, 9, 10, 11, 12,
13, 14...Operating circuit (flip-flop circuit, 8-bit binary counter circuit, Schmitt circuit, delay circuit, reset release control circuit, shift register), 15...Timing circuit (reset timing circuit).

Claims (1)

[Scope of Claims] 1. A game board from which pachinko balls are shot is provided with a plurality of types of specific winning holes and a winning device, and the winning device has a movable piece that can be opened and closed with respect to the continuous winning hole and the winning device. and an electric drive unit that drives the movable piece to open and close, and an operating circuit that operates the electric drive unit for a preset time in response to a win in the specific winning opening or continuous winning opening, and setting in the operating circuit. The operation time of the electric drive unit is set to be different from each other based on the winning of each specific winning opening, and the operating time of the electric driving unit is set to be different from each other based on the winning of the specific winning opening. In a pachinko machine that is set to be longer than the specified winning time, if the electric drive unit enters a prize in a specific winning opening different from the winning opening while operating based on a winning in the specific winning opening, the short operating time of the electric driving unit is changed to a long operating time. A function that prioritizes operations based on winnings in the different specific winning openings by retraction, and when the electric drive unit enters the specific winning opening while operating based on winnings in the continuous winning opening, A pachinko machine characterized by being provided with a timing circuit for the operation circuit, which has a function of disabling the operation of the electric drive unit based on winning.