JPH0370266B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention applies to two storage control devices MCU.
From the channel control device CHP directly connected to only one of each storage control device MCU to the central processing unit CPU,
or from the channel controller CHP to the central processing unit indirectly connected through another storage controller MCU
In the CPU interrupt processing method, the counter that selects the interrupt pending latch group in each storage controller MCU and the interrupt enable signal (mask signal) from the central processing unit CPU are synchronized between the two storage controllers MCU. Regarding the conversion method. With recent remarkable progress in semiconductor technology, logic blocks have become highly integrated, such as central processing units (CPUs) in data processing equipment, channel control units, etc.
As CHP, etc. are now configured on one board, the number of connectors for connecting each device has become limited. In addition, with the recent trend toward faster data processing equipment, two storage controllers MCU are equipped with a central processing unit.
In the basic configuration of a large data processing system in which a CPU and a channel control device CHP are connected, delays in signals propagating through signal lines from each device have become a problem, and the length of each signal line has to be reduced. Due to the desire to be as small as possible, data processing systems have changed from the configuration shown in FIG. 3a to the configuration shown in FIG. 3b. In the conventional system configuration shown in Figure 3a, each channel controller CHPO,1 is connected to a central processing unit.
Interrupt processing for CPU, 1, 2, 3 is 2
Since batch processing was performed on the master M side of the storage control unit MCU of the
Central processing that selects one of the interrupt requests sent in time series from CHP0 and CHP1 based on the value of a counter provided in the storage control unit MCU, and generates it based on the output signal of the same counter. There was no problem with the interrupt processing even in the method of generating interrupt signals by receiving interrupt mask signals from the devices (CPUs 0 to 3) in time series and comparing them with the above-mentioned interrupt requests. However, in a system configuration like b, the channel control unit CHP connected to one storage control unit MCU is connected to the central processing unit CPU.
There is no problem with the interrupt processing for
Channel control device CHP connected to MCU
When considering interrupt processing from a free central processing unit (CPU0, 2, or
It is necessary to synchronize with the interrupt enable signal (mask signal) from the CPUs 1 and 3), and an effective synchronization method between the two storage control units MCU has been awaited. [Prior Art] Figure 4 is a block diagram of a conventional interrupt processing mechanism in a storage control unit MCU.
1 is a counter, 2 is a decoder DEC, 3 is a group of interrupt pending latches, 4 is a selector SEL, 5 is an interrupt control section, 6 is a correction adder CA, 70 to 76 are latches, and 8 is a master and slave of the storage control unit MCU. This is the latch (M/S) to display. For convenience of explanation, CPUs 0, 1 and 2 are used as central processing units connected to each storage control unit MCU.
The explanation will be based on a system limited to two CHPs 0 and 1 as channel control devices. Also, usually
Interrupt processing, etc. is done by the storage control device on the master (M) side.
The MCU does it. Now, the channel control device (hereinafter referred to as CHP0, 1)
) to the central processing unit (hereinafter referred to as CPU0,1
), and when the interrupt information is set in latches 70 and 71,
It is decoded by decoder DEC2 and set in the relevant bit of interrupt pending latch group 3. Counter 1 is made up of, for example, 4 bits (=16 counts), and is counted up every machine cycle, and depending on the count value at that time, one of the interrupt pending latch group 3 made up of 16 bits is selected. It operates as if selected by selector SEL4. On the other hand, the value of the counter 1 is determined by the correction adder CA6, which reads the mask bit corresponding to the value of the counter 1 by the CPUs 0 and 1, and sets the latch 72,
73, the interrupt controller 5 corrects the delay cycle until the interrupt latch selected by the selector SEL4 is ANDed, and the signal is sent to the CPUs 0 and 1 through the latch 76. The interrupt mask bits sent from each CPU0 and 1 are set in latches 72 and 73, and
In the interrupt control unit 5, an AND is performed with the interrupt pending latch selected by the selector SEL4,
One interrupt according to the priority determined by the AND output is selected, and the latch 74 or 7
5 and is sent to CPU0,1 respectively, from CHP0,1 to CPU0,1.
An interruption is made. A logic table for sending the interrupt latch selected by the selector SEL4 to either CPU0 or CPU1 is shown below.

[Problem that the invention seeks to solve]

In such a conventional system, interrupt processing is executed collectively in the storage control unit MCU on the master side, so all channel control units connected to the system (for example, CHP0,
1) For the central processing unit (e.g. CPU0-3), latches corresponding to the latches 70-76,
and connection terminals are required, and the storage control device MCU
There were problems that hindered high integration. In addition, the channel control unit CHP and central processing unit CPU, which should normally be controlled by the storage control unit MCU on the slave side (or master side), are controlled by the storage control unit MCU on the master (M) side {or slave (S) side}. It is also necessary to connect to the storage control unit MCU, and as the signal line length increases, the signal propagation delay increases, which poses a problem that hinders the speeding up of the data processing system. In view of the above-mentioned conventional drawbacks, the present invention provides two storage control units MCU and all channel control units.
In a system configuration in which there is no direct connection between the CHPi or the central processing unit CPUj, the channel control device (for example, CHP0 or CHP
1, it is an object of the present invention to provide a method for effectively interrupting a central processing unit (eg, CPU,1, or CPU2,3). [Means for solving the problem] The purpose of this is to set an interrupt request from one channel control device CHP to the interrupt pending latch group of the directly connected storage control device MCU, and to send it through the storage control device MCU. , according to the numbers sent in chronological order from the storage control unit MCU to which the central processing unit CPU is directly connected. The interrupt enable signal (mask signal) received by the storage controller MCU is input in chronological order to the interrupt mask latch unit of the storage controller MCU, and is also input to the interrupt mask latch unit of another storage controller MCU through the storage controller MCU. Further, the mechanism and each storage control unit MCU are provided with a counter for selecting at least one interrupt signal from the group of interrupt pending latches according to the interrupt enable signal, and a state of the counter is decoded. , a third switching mechanism is provided that sends out to the other storage control unit MCU, and each storage control unit MCU transmits the decoded signal within itself based on the decoded signal sent by the third switching mechanism. and other storage controller MCU
means for detecting a discrepancy with the decoded signal sent from the decoded signal, the counter is forcibly set to a predetermined state by the discrepancy signal, and the counter is forcibly set to a predetermined state by the discrepancy signal; , the above forced setting is canceled, the counter is controlled to start counting, and the counter is synchronized by a synchronization mechanism 9 provided in each storage control device that synchronizes the counter. , based on the output signal of the synchronized counter, sends a number specifying the corresponding interrupt enable signal, and based on the first, second, and third switching mechanism, the two devices This is achieved by the synchronized interrupt control circuit of the present invention, which synchronizes the interrupt enable signal and the interrupt request between the storage control units MCU. [Operation] That is, according to the present invention, two storage control devices
The interrupt mechanism of the MCU is configured symmetrically, and the interrupt request information from the channel control device CHPi connected to each storage control device MCU is
At the same time, the interrupt mask signals sent in time series from the central processing unit CPUj are crossed with each other, and the latch data and the mask latch, which are obtained by decoding the interrupt request information, are stored in a group of interrupt pending latches in each interrupt control section. A counter output for selecting one from
In order to have a one-to-one correspondence, the output of the counter is
A mechanism is provided to synchronize the state of the counter to a specific state, for example, the '0' state, by crossing the lines at the intersection lines of the counters. Even if this happens, the counters of both MCUs will be automatically synchronized after a relatively short period of time without executing any special instructions to make the counters match, and self-memory control will be performed. Interrupt requests from the channel control device CHPi connected to the device MCU as well as interrupt requests from the channel control device CHPi connected to other storage control device MCU,
This has the advantage that it can be sent to any interrupt destination central processing unit CPUj at the same timing. [Examples] Examples of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart showing the synchronization operation of the counter, which is the main focus of the present invention, and FIG. The same reference numerals indicate the same objects, and the latches 80 to 83, the synchronization mechanism 9 of the counter 1, and the cross line (mask information, interrupt request information, counter decoding information) are functional blocks necessary to implement the present invention. It is. The system configuration in this embodiment is based on the configuration shown in FIG. 3b, but for convenience of explanation, the system configuration is
CPU0, CHP0, and CPU1, CHP1 respectively
It is assumed that they are directly connected. Even if the present invention is implemented, the basic operation of interrupt processing is the same as the conventional method explained in FIG. 4, so a detailed explanation will be omitted.
The timing at which interrupt request information from CHP0 connected to CHP0 is decoded by decoder DEC2 and set in interrupt pending latch group 3;
Interrupt request information from CHP1 connected to MCU1 must be decoded by decoder DEC2 of the same MCU0 and set to interrupt pending latch group 3 at the same timing. 1) and latches 80 and 81 for timing adjustment. In the same way, it is connected to MCU0
Interrupt mask information sent in chronological order from CPU 0 and interrupt mask information sent in chronological order from CPU 1 connected to MCU 1 are also processed by a crossover mechanism (second crossover mechanism) and timing alignment. Latches 82 and 83 are provided for this purpose. Next, from CHP1 connected to MCU1,
When an interrupt request is received to CPU0 connected to MCU0, the interrupt control unit 5 of MCU0 matches the interrupt pending latch selected by the value indicated by counter 1 with the mask latch sent from CPU0. In order to do this, MCU0,
1 counter 1 must operate completely synchronously. The main points of the present invention are the above-mentioned interrupt request information switching mechanism (first switching mechanism), mask information switching mechanism (second switching mechanism), and mechanism for synchronizing the counter 1 ( (including the third crossing mechanism) 9. The synchronization operation of the counter 1 will be explained with reference to the time chart of FIG. In the synchronization mechanism 9 of the counter 1, 91 is '
0' decoder DEC, 92 is the '0' decoder DEC of counter 1 provided in each of MCUs 0 and 1.
Output mismatch detection mechanism, a to d in MCU0
(or a' to d' in MCU1) are latches for timing adjustment. Now, when counter 1 of MCU0 starts counting from 0, counter 1 of MCU1 will be 4, 5,
Suppose that a counting operation of 6,... is performed. (See Figure 2, ,') First, the '0' decoder DEC91 of MCU0 is energized, latch a is turned on, and the signal is sent to latch b and passed through the crossing line (third crossing mechanism).
It is also sent to latch c' of MCU1. At this time,
Since the output of the '0' decoder DEC91 of the MCU 1 is '0', the '0' signal is sent to b' and c. Therefore, at the timing when the value of counter 1 of MCU0 is '2', latches b, c and b', c' are compared by the discrepancy detection mechanism 92, and if there is a discrepancy, the value of counter 1 of MCU0 is At timing '3', set latches d and d' to '1',
It functions to forcibly set each counter 1 of MCU0 and 1 to '0'. The '0' setting operation for the counter 1 is performed by energizing each '0' decoder DEC91 to turn on latches a and a', and each mismatch detection mechanism 92 detects a match and sets latches d and d. ' is set to '0'. From the timing when latches d and d' become '0',
Counters 1 of MCU0 and 1 can synchronize and start increasing the counters. (Fig. 2, 2,
2') As long as counters 1 of MCU0 and 1 continue counting up in synchronization, the interrupt mask number sent from MCU0 to CPU0 (i.e., counter 1
Since the interrupt mask number sent to MCU 1 or CPU 1 is exactly the same, the interrupt mask information from CPUs 0 and 1 is also the same, and the two mask information are sent to latches 82 and 1, respectively. Via 83, at the same timing,
For example, it is sent to the interrupt control unit 5 of MCU0, so even when an interrupt request is received from CHP1 connected to MCU1 to CPU0 connected to MCU0, the interrupt control unit 5 of MCU0 The interrupt pending latch selected by the value indicated by can be matched with the mask latch sent from CPU0. In this way, in the present invention, one state (for example, '0') of the counter 1 is decoded and sent to other MCUs (for example, MCU1), and
Corresponding signals received from other MCUs and own MCU (for example,
Due to a mismatch in the corresponding signals of MCU0), the counter 1 is kept set to one state (for example, '0'), and at the timing when a match is detected, the setting to one state is canceled, for example, configuration control is performed. Even if switching from 1MCU to 2MCU occurs due to etc., there is no need to execute any special commands to make the counters match, and the signal line between both MCUs 0 and 1 does not need to be executed.
With a minimum number of three pairs of crossing lines (first, second, and third crossing mechanisms) for interrupt request information, mask information, and counter '0' decoder DEC information,
However, after a relatively short period of time, both MCUs 0 and 1
A feature is that the count values of counter 1 can be automatically matched. [Effects of the Invention] As described above in detail, the interrupt control synchronization method of the present invention is effective when two storage control devices
The interrupt mechanism of the MCU is configured symmetrically, and the interrupt request information from the channel control device CHPi connected to each storage control device MCU is
At the same time, the interrupt mask signals sent in time series from the central processing unit CPUj are crossed with each other, and the latch data and mask latch obtained by decoding the interrupt request information are sent to the interrupt pending latch section in each interrupt control section. A counter output for selecting one from
In order to have a one-to-one correspondence, the output of the counter is
The state of the counter is changed by crossing it with the crossing mechanism of
Since it is equipped with a mechanism to synchronize to a specific state, for example, the '0' state, even if switching from 1MCU to 2MCU occurs due to configuration control, etc., there is no need for special commands etc. to make the counters match. The counters of both MCUs are automatically synchronized after a relatively short period of time, with a minimum of interface wires, and without the need for interrupt requests from the channel controller CHPi connected to the own memory controller MCU. Also, interrupt requests from the channel control unit CHPi connected to other storage control unit MCU,
This has the advantage that it can be sent to any interrupt destination central processing unit CPUj at the same timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing counter synchronization operation, and FIG. 3 is a diagram showing an example of the configuration of a data processing system. FIG. 4 is a block diagram showing a conventional interrupt processing mechanism. In the drawing, MCU0 and 1 are storage control devices,
CPU0 to 3 are central processing units, CHP0 and 1 are channel control units, MSU0 and 1 are main storage units, 1 is a counter, 2 is a decoder DEC, 3 is a group of interrupt pending latches, 4 is a selector (SEL), and 5 is an interrupt Control unit, 6 is a correction adder (CA), 70 to 76,
80 to 84 are latches, 9 is a counter synchronization mechanism,
Reference numeral 91 indicates a '0' decoder (DEC), and reference numeral 92 indicates a mismatch detection mechanism.

Claims (1)

[Claims] 1. For two storage control devices MCU, from a channel control device CHP directly connected to only one of each storage control device MCU, or indirectly through another storage control device MCU For synchronizing interrupt permission signals and interrupt requests when processing multiple interrupts in chronological order from the connected channel control device CHP to the central processing unit CPU directly connected to the storage control device MCU. A synchronization control circuit that sets an interrupt request from one channel control device CHP to a group of interrupt pending latches of a directly connected storage control device MCU, and sends an interrupt request from one channel control device CHP to another storage control device through the storage control device MCU. A first switching mechanism that simultaneously sets the interrupt pending latches of the MCU and an interrupt enable signal (mask signals) to the interrupt mask latch section of the storage control device MCU in chronological order, and
a second switching mechanism that inputs an input signal to the interrupt mask latch unit of another storage control unit MCU through the interrupt mask latch unit of the other storage control unit MCU; A counter is provided for selecting the counter, and a third switching mechanism is provided that decodes one state of the counter and sends it to the other storage control unit MCU, and each storage control unit MCU selects the third switching mechanism. Further, means is provided for detecting a mismatch between the decoded signal within the own device and the decoded signal sent from another storage control unit MCU based on the decoded signal sent by the mechanism, and the mismatch detection means The counter is forcibly set to a predetermined state by the detected counter mismatch signal, and the above forced setting is canceled by the match signal obtained by the forced setting, so that the counter starts counting. The counters are synchronized by a synchronization mechanism 9 that synchronizes the counters provided in each storage control unit MCU, and the output signals of the synchronized counters are used to synchronize the counters. ,
A number specifying the corresponding interrupt enable signal is sent, and the interrupt enable signal and interrupt request are exchanged between the two storage control units MCU based on the first, second, and third switching mechanisms. A synchronized interrupt control circuit characterized in that it performs synchronization with a synchronized interrupt control circuit.