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JPH0370887B2 - - Google Patents
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JPH0370887B2 - - Google Patents

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Publication number
JPH0370887B2
JPH0370887B2 JP25906585A JP25906585A JPH0370887B2 JP H0370887 B2 JPH0370887 B2 JP H0370887B2 JP 25906585 A JP25906585 A JP 25906585A JP 25906585 A JP25906585 A JP 25906585A JP H0370887 B2 JPH0370887 B2 JP H0370887B2
Authority
JP
Japan
Prior art keywords
hole
conductive material
pilot hole
reference unit
fired
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP25906585A
Other languages
Japanese (ja)
Other versions
JPS62118505A (en
Inventor
Riichi Naganuma
Norio Sato
Hiromitsu Ogawa
Eiji Mishiro
Masayo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25906585A priority Critical patent/JPS62118505A/en
Publication of JPS62118505A publication Critical patent/JPS62118505A/en
Publication of JPH0370887B2 publication Critical patent/JPH0370887B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Coils Or Transformers For Communication (AREA)

Description

【発明の詳細な説明】 〔概要〕 積層チツプインダクタの製造方法であつて、非
導電材上に多数の同形コイル導体パターンを形成
して、それぞれ90゜回転して積重ね、切断、焼成
して側面に形成したスルーホールを接続して積層
チツプインダクタの量産を可能にした。
[Detailed Description of the Invention] [Summary] A method for manufacturing a multilayer chip inductor, in which a large number of coil conductor patterns of the same shape are formed on a non-conductive material, each is rotated by 90 degrees, stacked, cut, fired, and the side surface is formed. By connecting the through-holes formed in

〔産業上の利用分野〕[Industrial application field]

本発明は、混成集積回路等に用いる積層チツプ
インダクタの製造方法に係り、とくに量産を可能
にした積層チツプインダクタの製造方法に関す
る。
The present invention relates to a method of manufacturing a laminated chip inductor for use in hybrid integrated circuits, etc., and particularly to a method of manufacturing a laminated chip inductor that enables mass production.

近年、電子機器は電子部品の小形化に伴なつ
て、ユニツト化された回路基板上に搭載するチツ
プ形部品たとえば、セラミツク基板等に形成した
チツプ形インダクタが出現しているが、このチツ
プ形インダクタはセラミツク基板上にスパイラル
となつているので、スペースフアクタが悪く高密
度実装に適さないので、スペースフアクタが良好
で高密度実装に適する積層チツプインダクタの製
造方法の開発が強く要望されている。
In recent years, with the miniaturization of electronic components in electronic devices, chip-shaped components mounted on unitized circuit boards, such as chip-shaped inductors formed on ceramic substrates, have appeared. Since the inductor is spirally formed on a ceramic substrate, the space factor is poor and it is not suitable for high-density mounting.Therefore, there is a strong demand for the development of a manufacturing method for multilayer chip inductors that has a good space factor and is suitable for high-density mounting. .

〔従来の技術〕[Conventional technology]

従来のチツプインダクタは、リング状の磁性材
に導体からなるコイルを巻回するか、または誘電
体たとえばセラミツク等からなる基板上に導体パ
ターンをスパイラルに形成した構造である。
A conventional chip inductor has a structure in which a coil made of a conductor is wound around a ring-shaped magnetic material, or a conductive pattern is spirally formed on a substrate made of a dielectric material such as ceramic.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来のインダクタにあつては、いずれも平
面的構成のためスペースフアクタが悪く、高密度
実装を阻害し量産が困難で高価になる等の問題点
があつた。
All of the conventional inductors mentioned above have problems such as a poor space factor due to their planar configuration, which hinders high-density packaging, making mass production difficult and expensive.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記の問題点を解決してスペースフ
アクタが良好で高密度実装に適する積層チツプイ
ンダクタの製造方法を提供するものである。
The present invention solves the above problems and provides a method for manufacturing a laminated chip inductor that has a good space factor and is suitable for high-density packaging.

すなわち、4個を基準単位Aとし、縦、横同数
の基準単位Aの複数個+1/2基準単位Aの寸法
の非導電材上に、該基準単位Aを4等分する十字
状の切断線の4分線の中央にスルーホールの下孔
を穿設し、前記基準単位Aの1個の中心に環状の
一部を除き、その両端に連なるパターンが前記下
孔に達する導体パターンを形成した前記非導電材
それぞれ90゜回転して複数枚積み重ね、さらに上
面にダミー非導電材を重ね、切断線に沿つて切断
し焼成したるのち、全面に導体を塗布後切断面を
前記スルーホールの下孔の1/2以下に研磨し焼
成したことことによつて解決される。
That is, with four pieces as a reference unit A, a cross-shaped cutting line that divides the reference unit A into four equal parts is placed on a non-conductive material with dimensions equal to a plurality of reference units A in the same number vertically and horizontally + 1/2 reference unit A. A pilot hole for a through hole was bored in the center of the quarter line of the reference unit A, and a conductor pattern was formed in which a ring-shaped part was removed at the center of one of the reference units A, and the pattern that continued at both ends reached the pilot hole. Each of the non-conductive materials is rotated 90 degrees and stacked, a dummy non-conductive material is layered on top, cut along the cutting line, fired, and then the conductor is applied to the entire surface and the cut surface is placed under the through hole. This problem can be solved by polishing and firing the holes to less than 1/2.

〔作用〕[Effect]

上記積層チツプインダクタの製造方法は、同一
磁性材からなる板上に4個を基準単位とした複数
個+1/2基準単位を縦、横同数(完成時の数は
奇数)とし、しかも基準単位に同心で同形の導体
パターンを形成し、それぞれを90゜回転して積重
ねてこれを切断し焼成して製造するので量産化に
適する。
The manufacturing method of the above-mentioned multilayer chip inductor is to make multiple units of 4 + 1/2 standard units on a plate made of the same magnetic material, the same number vertically and horizontally (the number when completed is an odd number), and the standard unit. It is suitable for mass production because it is manufactured by forming concentric and identical conductor patterns, rotating them 90 degrees, stacking them, cutting them, and firing them.

〔実施例〕〔Example〕

第1図は、本発明の一実施例を説明する導体パ
ターンを形成した斜視図である。
FIG. 1 is a perspective view showing a conductor pattern formed thereon, explaining one embodiment of the present invention.

図において、磁性材等からなる非導電材1上
に、4個で基準単位Aを形成する。そして縦、横
同数(図面では各3.5枚)の基準単位Aの複数個
+1/2基準単位Aの大きさの非導電材1上に、基
準単位Aを4等分する十字状の切断線9の4分線
の中央にスルーホール2の下孔21を穿設する。
そして基準単位Aの1個の中心に環状の一部を除
き、その両端に連なるパターンが前記下孔21に
達する導体パターン5を形成したものである。
In the figure, four reference units A are formed on a non-conductive material 1 made of a magnetic material or the like. Then, on the non-conductive material 1 having the same number of reference units A in the vertical and horizontal directions (3.5 sheets each in the drawing) + 1/2 reference unit A, cross-shaped cutting lines 9 are placed on the non-conductive material 1 that divides the reference unit A into four equal parts. The pilot hole 21 of the through hole 2 is bored in the center of the quarter line.
Then, a conductor pattern 5 is formed in the center of one of the reference units A, with a ring-shaped part removed, and the pattern continuing at both ends reaches the pilot hole 21.

第2図は、本発明の一実施例を説明する図で、
同図aは分解斜視図、bは組立斜視図で、cは回
路表示図で、第1図と同等の部分については同一
符合を付している。
FIG. 2 is a diagram illustrating an embodiment of the present invention.
In the figure, a is an exploded perspective view, b is an assembled perspective view, and c is a circuit diagram, in which parts equivalent to those in FIG. 1 are given the same reference numerals.

図において、第1図で説明した磁性材等からな
る非導電材1をそれぞれ90゜回転して積み重ね、
第1枚目の磁性材1の導体パターン5の一方の半
円のスルーホール2が、第2枚目の90゜異なつた
半円のスルーホール2と合致し、そして第2枚目
の半円のスルーホール2は第3枚目の90゜異なつ
た半円のスルーホール2と合致する。このように
して所用枚数の非導電材1を積重ねたのち、さら
に上面にダミー非導電材6を積重ね切断線9に沿
つて個々に切断し焼成したるのち、全面に導体を
塗布後切断面を前記スルーホール2の下孔21の
1/2以下に研磨し焼成すれば第2図bの如き積
層チツプインダクタとなる。そしてこの積層チツ
プインダクタを回路表示で示したものが第2図c
である。
In the figure, the non-conductive materials 1 made of magnetic material etc. explained in FIG. 1 are each rotated 90 degrees and stacked.
One semicircular through hole 2 of the conductor pattern 5 of the first sheet of magnetic material 1 matches the semicircular through hole 2 of the second sheet, which is different by 90 degrees, and then The through hole 2 matches the semicircular through hole 2 of the third sheet, which is 90° different. After stacking the required number of non-conductive materials 1 in this way, dummy non-conductive materials 6 are further stacked on the top surface, cut individually along cutting lines 9 and fired, and after coating the entire surface with a conductor, the cut surface is If the through hole 2 is polished to less than 1/2 of the diameter of the pilot hole 21 and fired, a multilayer chip inductor as shown in FIG. 2b is obtained. The circuit representation of this multilayer chip inductor is shown in Figure 2c.
It is.

なお、本実施例では非導電材に基準単位Aを
縦、横3.5個について説明したが、完成時の数は
奇数となれば良く1.5,2.5,3.5,4.5・・・100.5
個等であつても良い。また、導体パターンは円状
について説明したが、円状に限らず三角、四角等
の多角形であつても構わない。さらに導体パター
ンを形成する非導電材を磁性材について説明した
が、磁性材に限らず絶縁材であつても構わない。
In addition, in this example, the reference unit A is 3.5 pieces vertically and horizontally on the non-conductive material, but the number when completed is 1.5, 2.5, 3.5, 4.5...100.5 as long as it is an odd number.
It may be individual. Furthermore, although the conductor pattern has been described as being circular, it is not limited to the circular shape, but may be polygonal, such as triangular or square. Further, although the non-conductive material forming the conductive pattern is described as a magnetic material, it is not limited to a magnetic material, and may be an insulating material.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかよように、本発明によれ
ば積層チツプインダクタの量産が可能となり、コ
ストダウンが期待できるとともに搭載部品の高密
度実装に極めて有効である。
As is clear from the above description, the present invention enables mass production of multilayer chip inductors, can reduce costs, and is extremely effective for high-density mounting of mounted components.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を説明する導体パ
ターンを形成した斜視図、第2図は、本発明の一
実施例を説明する図で、同図aは分解斜視図、b
は組立斜視図で、cは回路表示図である。 図において、1は非導電材、2はスルーホー
ル、5は導体パターン、6はダミー非導電材、7
は積層間の導通部、9は切断線、21は下孔、を
それぞれ示す。
FIG. 1 is a perspective view of a conductor pattern formed thereon, illustrating an embodiment of the present invention, and FIG. 2 is a diagram illustrating an embodiment of the present invention.
is an assembled perspective view, and c is a circuit diagram. In the figure, 1 is a non-conductive material, 2 is a through hole, 5 is a conductive pattern, 6 is a dummy non-conductive material, 7
9 indicates a conductive portion between the laminated layers, 9 indicates a cutting line, and 21 indicates a pilot hole.

Claims (1)

【特許請求の範囲】[Claims] 1 4個を基準単位Aとし、縦、横同数の基準単
位Aの複数個+1/2基準単位Aの寸法の非導電
材1上に、該基準単位Aを4等分する十字状の切
断線9の4分線の中央にスルーホール2の下孔2
1を穿設し、前記基準単位Aの1個の中心に環状
の一部を除き、その両端に連なるパターンが前記
下孔21に達する導体パターン5を形成した前記
非導電材1をそれぞれ90゜回転して複数枚を積み
重ね、さらに上面にダミー非導電材6を積重ね、
切断線9に沿つて切断し焼成したるのち、全面に
導体を塗布後切断面を前記スルーホール2の下孔
21の1/2以下に研磨し焼成したことを特徴と
する積層チツプインダクタの製造方法。
1. With 4 pieces as the reference unit A, cut a cross-shaped cutting line dividing the reference unit A into four equal parts on the non-conductive material 1 with the dimensions of the same number of reference units A in the vertical and horizontal directions + 1/2 reference unit A. Pilot hole 2 of through hole 2 in the center of the quarter line of 9
1, and a ring-shaped part is removed at the center of one of the reference units A, and a conductor pattern 5 is formed at both ends of the non-conductive material 1, with the pattern extending to the pilot hole 21. Rotate and stack a plurality of sheets, further stack a dummy non-conductive material 6 on the top surface,
Manufacture of a multilayer chip inductor characterized in that it is cut along the cutting line 9 and fired, then coated with a conductor over the entire surface, polished to less than 1/2 of the diameter of the pilot hole 21 of the through hole 2, and fired. Method.
JP25906585A 1985-11-18 1985-11-18 Manufacture of laminated chip inductor Granted JPS62118505A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25906585A JPS62118505A (en) 1985-11-18 1985-11-18 Manufacture of laminated chip inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25906585A JPS62118505A (en) 1985-11-18 1985-11-18 Manufacture of laminated chip inductor

Publications (2)

Publication Number Publication Date
JPS62118505A JPS62118505A (en) 1987-05-29
JPH0370887B2 true JPH0370887B2 (en) 1991-11-11

Family

ID=17328832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25906585A Granted JPS62118505A (en) 1985-11-18 1985-11-18 Manufacture of laminated chip inductor

Country Status (1)

Country Link
JP (1) JPS62118505A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH071821B2 (en) * 1989-12-11 1995-01-11 サンケン電気株式会社 Wiring board
JPH04118910A (en) * 1990-02-23 1992-04-20 Taiyo Yuden Co Ltd Manufacture of laminated chip inductor
CA2158784A1 (en) * 1994-11-09 1996-05-10 Jeffrey T. Adelman Electronic thick film component termination and method of making the same
US8056199B2 (en) 2008-10-21 2011-11-15 Tdk Corporation Methods of producing multilayer capacitor
JP4816708B2 (en) * 2008-10-21 2011-11-16 Tdk株式会社 Manufacturing method of multilayer capacitor
US10269481B2 (en) 2016-05-27 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked coil for wireless charging structure on InFO package
CN112687462B (en) * 2020-12-11 2022-06-07 全南群英达电子有限公司 Magnetic head magnetic core punching and riveting integrated machine

Also Published As

Publication number Publication date
JPS62118505A (en) 1987-05-29

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