JPH0370905B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a MOS type memory device, and more particularly to a MOS type random access memory device that sequentially reads charges accumulated in a capacitor section.

(Prior Art) There is a strong demand for an improvement in the degree of integration of integrated circuit devices, and there is also a need to miniaturize elements to the utmost limit. In MOS type integrated circuit devices, miniaturization of elements is achieved by miniaturizing transistors such as channel length and width, and reducing wiring width and spacing.

In MOS type memory devices, in addition to the reduction in the dimensions of the transistors and interconnections described above, reduction in the area of the capacitor portion for storing charge as a signal has become an important issue. In other words, it is a so-called 1-transistor, 2-capacitor MOS in which the charge accumulated in one capacitor is read out by one MOS transistor.
In type RAM memory, the area occupied by the capacitor is larger than the area occupied by the transistor, and there has been a need to reduce the area occupied by the capacitor. On the other hand, if the capacitor itself becomes too small, the amount of charge stored as a signal will become small, and the readout signal will become too small to be detected as a signal, or alpha rays may pass through the capacitor or the silicon substrate near it. Due to the effect of minority carriers that occur when Ta.

Figures 1a to 1d are cross-sectional views showing the structure of a conventional MOS type memory device and its manufacturing process in order of process.As shown in Figure 1a, the conventional MOS type memory device first has a resistance of 10Ωcm. A silicon nitride film 102 is selectively formed on a p-type silicon substrate 101, and this silicon nitride film 102 is used as a mask.
P ⁺ diffusion layers 103, 103' and thick silicon oxide films 104, 104' in the field portions are formed.

Next, as shown in FIG. 1b, a silicon nitride film 1
After removing part of 02, p ⁺ layer 105, n ⁺ layer 1
06, oxidize the silicon substrate 101,
After forming a thin capacitive silicon oxide film 107, a polycrystalline silicon layer 108 forming a MOS type capacitor with the silicon substrate 101, and the polycrystalline silicon 10
A silicon oxide film 109 covering 8 is formed.

Next, as shown in FIG. 1c, a silicon nitride film 1
After removing all 02, p ⁺ which acts as a bit line
A diffusion layer 110, a gate oxide film 111, and a gate polycrystalline silicon layer 112 are formed.

Finally, as shown in FIG. 1d, the phosphor glass film 1
13. When aluminum wiring 114 is formed
A MOS type memory device is obtained.

In this conventional MOS type memory, charge is accumulated in the MOS type capacitor formed between the silicon substrate 101 and the polycrystalline silicon layer 108.
The value of MOS type capacitance is mainly due to the thin silicon oxide film10
The thickness and dielectric constant of the silicon oxide film 107 are determined by the size of the region where the capacitive part is formed, that is, the size of the thin silicon oxide film 107. However, as the thickness of the silicon oxide film 107 becomes thinner, current flows more easily, so it cannot be reduced below a certain value. In addition, even if a film with a large dielectric constant is tried to be used in place of the silicon oxide film 107, there is a problem that there is no suitable film, and since the area of this capacitive part cannot be reduced below a certain value, as mentioned above, A major drawback was that it hindered the high integration of MOS memory devices.

As shown in IEDM'82, Extended Abstract page 806, a conventional and improved method to solve this problem is to use anisotropic etching to dig down the silicon substrate in the area corresponding to the capacitive part to make it concave. There was a method of effectively increasing the area of the capacitor section by using the wall surface of the capacitor as a capacitor.
However, in this conventional method, anisotropic etching is usually performed by reactive etching in plasma, but damage from that process remains in the silicon substrate, and the charge accumulated in the capacitance decays quickly, or the side surface of the recess. The drawback is that it is difficult to dope the impurities by ion implantation.

(Objective of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a MOS type memory device having a capacitor in which a large amount of charge is stored in the capacitor and the attenuation of the stored charge is small.

(Structure of the Invention) The MOS type memory device of the present invention includes a silicon epitaxial layer grown on one main surface of a silicon substrate, an insulator formed on the surface of the silicon epitaxial layer, and a silicon epitaxial layer grown on one principal surface of a silicon substrate. The device has a MOS capacitor formed of a conductive material formed thereon, and is configured by storing charge in the MOS capacitor.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIGS. 2A to 2D are cross-sectional views shown in order of steps to explain the first embodiment of the present invention and its manufacturing method, and the first embodiment can be formed by the following steps.

First, as shown in FIG. 2a, a silicon nitride film 202 is selectively formed on a p-type silicon substrate 201, and using this as a mask, p ⁺ diffusion layers 203, 20 are formed.
3' field silicon oxide film 204, 20
After forming 4', a silicon epitaxial layer 205 is selectively grown on the surface of the silicon substrate which will become a capacitive part.

Next, as shown in FIG. 2b, the p ⁺ layer 206,
forming an n ⁺ layer 207 in a silicon epitaxial layer 205 of the same conductivity type as the silicon substrate 201;
A thin silicon oxide film 208 is formed on the surface of the silicon epitaxial layer 205, a polycrystalline silicon layer 209 serving as a capacitor electrode is formed on the silicon oxide film 208, and the polycrystalline silicon layer 209 is covered with a silicon oxide film 210.

Next, as shown in FIG. 2c, after removing the silicon nitride film 202, the n ⁺
A layer 211, a gate oxide film 212, and a polycrystalline silicon layer 213 that will become a gate electrode are formed.

Finally, as shown in FIG. 2d, the present embodiment is completed by forming a phosphor glass layer 214 and an Al wiring 215.

According to the first embodiment of the present invention formed as described above, the capacitance of the MOS type memory device is formed on the surface of the silicon epitaxial layer 205 selectively grown on the silicon substrate. Since the side surface of the epitaxial layer 205 is also used as a capacitor, the effective area of the capacitor part is large, and therefore, there is a great advantage that a larger amount of charge can be stored in the capacitor part. Furthermore, since the silicon epitaxial layer 205 is formed by, for example, thermal decomposition of SiH ₂ Cl ₂ (dichlorosilane) at 950°C,
There is no damage to the surface of the silicon epitaxial layer 205, and the charge accumulated in the MOS type capacitor formed thereon has the advantage of being retained for a long time. Furthermore, the silicon epitaxial layer 205
can be formed into a trapezoidal shape, which also has the advantage that impurity implantation by ion implantation is easy.

FIGS. 3a and 3b are cross-sectional views showing a second embodiment of the present invention in the order of steps. The second embodiment can be formed by the following steps.

First, as shown in FIG. 3a, a silicon substrate 3 is
A silicon nitride film 302 is selectively formed on the surface of the p ⁺ layer 3 using this silicon nitride film as a mask.
03, 303' and field oxide films 304, 30
After forming a p ⁺ layer 305 and an n ⁺ layer 306 on the surface of the silicon substrate 301 from which a part of the silicon nitride film 302 was removed, a silicon epitaxial layer 307 of the same conductivity type as the silicon substrate 301 is formed. grow selectively.

Next, as shown in FIG. 3b, a silicon epitaxial layer 3 is formed by the same method as in the first embodiment.
P ⁺ layer 308, N ⁺ layer 309 formed in 07,
Thin silicon oxide film 310, polycrystalline silicon layer 3
11. From silicon oxide film 312, n ⁺ layer 313, gate oxide film 314, polycrystalline silicon layer 315, phosphor glass film 316, aluminum wiring 317
Obtain a MOS type memory device.

The second embodiment of the present invention obtained as described above
In MOS type memory devices, the charge is in the p ⁺ layer 3
05 and the n ⁺ layer 306 and the MIS capacitance formed between the silicon epitaxial layer 307 and the polycrystalline silicon layer 311.
In addition to the advantage that the side surface of 7 can also be used as a capacitance section, it also has the great advantage of being able to further increase the capacitance value.

FIG. 4 is a sectional view for explaining the third embodiment of the present invention, and the same parts as in FIG. 3 are designated by the same numbers, but in the third embodiment of the present invention,
When growing the silicon epitaxial layer 407, the p ⁺ layer and the n ⁺ layer are grown alternately from above the n ⁺ layer 306, and finally the surface of the epitaxial layer 407 is selectively grown by ion implantation or thermal diffusion. ⁺ layer
By forming the p ⁺ layer, the n ⁺ layer 408 and the p ⁺ layer 40
9 is formed, and a thin oxide film 410 and a polycrystalline silicon film 411 as an insulating film of a MOS type diode are formed.

In this third embodiment of the present invention, the charge is
In addition to the p-n junction formed by the n ⁺ layer 305 and p ⁺ layer 306 of the MOS type capacitor board, the n ⁺ layer 408 and
Since it is also accumulated in the pn junction formed by the p ⁺ layer 409, the capacitance value increases dramatically, which has the great advantage of making it possible to reduce the planar area of the capacitor section.

(Effects of the Invention) As explained above, according to the present invention, it is possible to form a capacitor in which the amount of charge stored in the capacitor is large and the attenuation of the stored charge is small. can be done reliably
A MOS type memory device is obtained.

[Brief explanation of drawings]

1A to 1D are cross-sectional views shown in the order of steps to explain the structure and manufacturing method of an example of a conventional MOS type memory device, and FIGS.
3A and 3B are cross-sectional views shown in the order of steps to explain the structure and manufacturing method of the second embodiment of the present invention, and FIGS. FIG. 4 is a cross-sectional view of a third embodiment of the present invention. 101, 201, 301...Silicon substrate, 1
02,202,302...Silicon nitride film, 10
3,103',203,203',303,30
3'...p ⁺ layer, 104, 104', 204, 20
4', 304, 304'...field part oxide film,
105, 207, 305, 308, 409...
p ⁺ layer, 106, 110, 207, 211, 30
6,309,313,408...n ⁺ layer, 107,
109, 111, 208, 210, 212, 31
0, 312, 314, 410... silicon oxide film, 108, 112, 209, 213, 311,
315...polycrystalline silicon layer, 205, 307,
407...Silicon epitaxial layer, 113,
214,316...phosphorus glass film, 114,21
5,317...Aluminum wiring.

Claims (1)

[Claims] 1 p-layers and n-layers formed on the surface of a semiconductor substrate; p-layers formed on the surface of the semiconductor substrate alternately so as to selectively form a comb-like shape;
It consists of a convex region made of an n-layer multilayer film, a thin insulating film formed on the surface of the convex region, and a conductive film formed on the insulating film, and of the multilayer film, the semiconductor substrate The layers of the same conductivity type as p are electrically connected to this semiconductor substrate, the layers of the multilayer film that are of a different conductivity type from the semiconductor substrate are electrically connected to each other, and
- A MOS type memory device characterized in that charge is accumulated at the n-junction and at the MIS interface on the surface.