JPH0375838B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a game clock that is capable of audibly announcing the time remaining in a game such as Shogi or Go in which the playing time of the opponents is determined in advance.

(b) Prior Art Conventional game clocks are disclosed in Japanese Patent Application Laid-open Nos. 16381-1981 and 16382-1982.

All of these conventional game clocks are designed to provide audio notification of the remaining time every predetermined period of time after the start of the game.

(c) Problems to be Solved by the Invention When the remaining time is notified at regular intervals as in the above-mentioned prior art, when there is a considerable amount of time remaining,
Even if you notify the system at regular intervals, it will have little effect as there is still some psychological leeway, but when the time is running low, there will often be a situation where there is a stalemate, and in such cases there are no warning signs. If you inform them, ``How much time do you have left...'' instead, it has a big psychological impact, and often causes people to panic and not be able to think accurately.

In such a case, even a winnable game may end up being a loss, which is a serious problem for the players.

(d) Means for Solving the Problems The present invention allows players to be informed of the time they have in a reasonable manner and without affecting the game. In particular, the moment when the opponent stops thinking is when his or her turn ends, and at this time, the voice notification does not have much of an effect.

Therefore, in the present invention, when one player's turn ends, that is, when a switch is operated to stop the counter that counts the remaining time and activate the counter that counts the other player's time. A voice announcement is made. However, at the beginning of the game, because both players move quickly, the intervals between switch operations are short and they do not need much time information, so having a voice notification every time a switch is operated would make it noisier.
It is possible that it will interfere with the game.

Therefore, in the present invention, when both sides make quick moves, such as at the beginning of the game, audio notifications are made at regular intervals, and when both sides gradually become stuck, as at the end of the game, they make only one move. This system provides an audio notification every time a switch is operated, which would take a very long time to proceed.

The structure of the audio game clock of the present invention includes a reference signal generator, a bistable switch, and two sets in which counting and stopping of clock pulses from the reference signal generator are performed in opposition to each other by operation of the bistable switch. a subtraction counter; an audio signal generation circuit that generates an audio signal based on the count value of the subtraction counter; and a sound generation circuit that generates audio based on the audio signal from the audio signal generation circuit;
a fixed time detection circuit that outputs a detection signal every time the count value of the subtraction counter is subtracted by a certain value; an operation detection circuit that detects that the bistable switch is operated; and an operation time interval of the bistable switch. an operation interval detection circuit that detects that the operation interval has exceeded a certain time; and in response to a signal from the operation interval detection circuit, the constant time detection circuit A detection signal is applied to the audio signal generation circuit as an operation signal, and when the operation time interval of the bistable switch exceeds a certain time, a detection signal from the operation detection circuit is applied as an operation signal to the audio signal generation circuit. It is characterized by consisting of a gate circuit.

(e) Examples Examples of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing the circuit configuration of a voice game clock according to an embodiment of the present invention.

2 is an oscillator that outputs a reference signal, and 4 is a frequency dividing circuit that divides the frequency of the reference signal as appropriate.

6 is a bistable switch, 8 is a flip-flop (hereinafter abbreviated as "FF") which inputs the signal from this bistable switch 6 to the set input S and reset input R, respectively; 10 is a start switch;
12 is a display changeover preset switch, and 14 is a time set switch.

16 and 18 are and games, and frequency dividing circuit 4
The clock signal from the start switch 10 and the signal from the start switch 10 are both inputted, and furthermore, the signals C ₁ and C ₂ from the output Q of the FF8 are inputted, respectively.

20 and 22 are subtraction counters, which are operated by inputting signals from AND gates 16 and 18.

24 is a set time counter that is set by operating the time set switch 14, and 26 and 28 are set time counters that are set by operating the display changeover preset switch 12 and inputting pulses generated via the inverter 30 and one-shot multibrator 32. Counter 20, 22 subtracts from count value
This is a preset circuit that presets the

Numerals 34 and 36 are addition counters, which are reset by pulses from the one-shot multivibrator 32 and operated by the output signals of the AND gates 16 and 18.

Decoder drivers 38 and 40 input signals from the subtraction counters 34 and 36, and display sections 42 and 44 input signals from the decoder drivers 38 and 40 to display the consumed time. In this embodiment, the addition counter 34 and the decoder
A switching circuit 46 is provided between the driver 38 and the switching circuit 46 is configured to switch and output the signals from the addition counter 34 and the set time counter 24 when the signal from the display switching preset switch 12 is input. Therefore, the display section 42 displays the set time and the consumed time.

48 is the signal A ₁ from the subtraction counters 20 and 22,
This is a zero time detection circuit that inputs A ₂ and detects when the remaining time has run out.

50 is a fixed time detection circuit which inputs signals A ₁ and A ₂ and detects the remaining time divided into regular intervals such as every 10 minutes, and also determines whether to notify the remaining time of the first player or the second player. Output signal E ₃ .

52 inputs the signals C ₁ and C ₂ and detects when the time required for one move of each opponent becomes longer and the operation interval of the bistable switch becomes longer than a certain time, and sends an audio notification every certain time. This is a switching circuit that switches the notification to correspond to the switch operation.

Reference numeral 54 denotes an end voice code output circuit which stores the codes of the end voices "Sentenokachi" and "Gotenokachi", inputs signals B ₅ and B ₆ from the zero time detection circuit 48, and switches and outputs the end voice code. It is.

Reference numeral 56 designates a time voice code output circuit, which stores codes for time voice "sente", "gote", "ato", "jikan", and "pun", and subtracts counters 20, 2.
2. Signals A ₁ , A ₂ , B ₁ , B ₃ , E _{3 ,} etc. from the zero time detection circuit 48 and fixed time detection circuit 50 are inputted, and time audio codes are sequentially output.

58 inputs code signals from the end voice code output circuit 54 and the time voice code output circuit 56;
This is a multiplexer that switches and outputs input signals according to the output state of the FF 60.

62 is a voice that stores data necessary for voice
ROM 64 is an audio signal generation circuit that reads necessary data from the audio ROM 62 in response to a signal from the multiplexer 58 and outputs an audio signal.

66 is a voice start circuit, and a zero time detection circuit 4
8 and signals B ₇ and J ₁₁ from the switching circuit 52, a signal M ₃ is applied to the audio signal generating circuit 64 to output an audio signal.

68 is a sound generation circuit, and the audio signal generation circuit 64
It generates sound by inputting audio signals from the.

Next, the display operation of the consumed time will be explained using FIG. Note that the voice notification operation of the time limit will be described later with reference to FIG. 2 and subsequent drawings.

First, operate the time set switch 14 to set the time on the set time counter 24, and then operate the display changeover preset switch 12. This operation signal is input, and the switching circuit 46 changes the signal from the set time counter 24. The signal is now in an output state and is applied to the display unit 42 via the decoder/driver 38.

Therefore, the set time is displayed on the display section 42. At this time, the one-shot multivibrator 32, which receives the operation signal of the display changeover preset switch 12 via the inverter 30, outputs a pulse and applies this pulse to the preset circuits 26, 28 and addition counters 34, 36.

In response to this pulse, the preset circuits 26 and 28 preset the count value of the set time counter 24 into the subtraction counters 20 and 22, respectively, and the subtraction counters 34 and 36 are each reset by this pulse.

Next, when the bistable switch 6 is turned on in the manner shown and the FF 8 is set and its output signal _C1 is at the H level, when the start switch 10 is turned on, the ungate 16 is opened. The clock signal from the frequency divider circuit 4 is generated at its output, and the subtraction counter 20 inputs the clock signal.
and the addition counter 34 operates.

The count value of the addition counter 34 is applied to the switching circuit 46, and the display switching preset switch 1
2 is in the off state, this switching circuit 46
The count value of the addition counter 34 is outputted to the output of the display unit 42 via the decoder/driver 38.
Displays the time consumed by one opponent, for example, the first move.

Then, when bistable switch 6 is switched,
An H level signal is applied to the reset input R of FF8, FF8 is reset, and the signal _C2 from its output becomes H level.

At this time, if the start switch 10 is turned on, the ungate 18 is opened, and a clock signal is generated at the output of the ungate 18.

This clock signal is input to the subtraction counter 22.
and the addition counter 36 operates, and the addition counter 36
The count value is applied to the decoder/driver 40, and the time consumed by the second player, the other opponent, is displayed on the display section 44.

Next, the detailed circuit configuration of the audio notification section shown in FIG. 1 will be explained using FIGS. 2 to 5.

2 is a diagram showing detailed circuit configurations of the zero time detection circuit 48, end audio code output circuit 54, time audio code output circuit 56, and audio reorganization circuit 66 shown in FIG. FIG. 4 is a diagram showing a detailed circuit configuration of the fixed time detection circuit 50 shown in the figure;
This figure is a diagram showing a detailed circuit configuration of the switching circuit 52 shown in FIG. 1, and FIG. 5 is a diagram showing a detailed circuit configuration of the audio signal generation circuit 64 shown in FIGS. 1 and 2.

The zero time detection circuit 48 (FIG. 2) includes a "0" hour detection circuit 70 and a "0" minute detection circuit 72, which receive the signal _A1 indicating the count value of the subtraction counter 20.
A “0” time detection circuit 74 and a “0” minute detection circuit 76 which input the signal A ₂ indicating the count value of the subtraction counter 22, and signals B ₁ and B ₃ outputted by the “0” time detection circuits 70 and 74. and "0" minute detection circuit 72,7
AND gate 78 inputs signals B ₁ and B _{2 of the signals B 2 and B 4 outputted by 6} , AND gate 80 inputs signals B ₃ and B ₄ , and its output signals B ₅ and B ₆ are input. It consists of an OR gate 82 and a one-shot multivibrator 84 which inputs its output signal and outputs a pulse as an output signal _B7 .

The end voice code output circuit 54 includes a "SENTENOKACHI" code ROM 86 that stores the code for the voice "SENTENOKACHI" and a "GOTENOKACHI" code ROM 88 that stores the code for the voice "GOTENOKACHI".
It is comprised of a multiplexer 90 which inputs these output signals and signals B ₅ and B ₆ from the zero time detection circuit 48 and switches and outputs signals from the code ROMs 86 and 88.

The time audio code output circuit 56 outputs "SENTE",
"Sente" code ROM92 that stores the codes of "Gote", "Ato", "Jikan", and "Pun", respectively;
“Gote” code ROM94, “Ato” code ROM
96, “Jikan” code ROM98, “Pun” code ROM100, and this code ROM92,94
a multiplexer 102 that switches and outputs the signals from the subtraction counters 20 and 22 according to the signal E ₃ ; a multiplexer 104 that switches and outputs the signals A ₁ and A ₂ from the subtraction counters 20 and ₂₂ according to the signal E 3;
A multiplexer 106 inputs signals from 02, 104 and code ROMs 96 to 100, a counter 108 that sequentially outputs the input signals from this multiplexer 106, and a counter 108 that inputs signals B ₁ and B ₃ to one input of each and outputs a signal E. AND gate 110 which inputs ₃ with one side unchanged and the other side inverted,
112, OR gates 114 and 116 that input the output signals of the AND gates 110 and 112 of the outputs Q ₂ and Q ₃ of the counter 108, respectively, an AND gate 118 that inputs the output signals N ₂ and N ₃ thereof, and the output signal thereof. The AND gate 120 inputs N ₄ and the clock signal φ ₁ , and the counter 10 inputs the output signal N ₅ and the signal H from the audio signal generation circuit 64.
8, and a one-shot multivibrator 124 which receives the signal from the output _Q6 of _the counter 108 and outputs the signal _N6 .

The voice start circuit 66 includes an OR gate 126 that inputs the signals B ₇ and J ₁₃ from the zero time detection circuit 48 and the constant time detection circuit 50, and signals K and N from the voice signal generation circuit 64 and the time voice code output circuit 56. OR gate 128 where ₆ is input and this OR gate 1
Set input S for signals from 26 and 128, respectively.
and a reset input R, and an AND gate 132 which receives its output signal _M2 and a clock signal _φ1 .

The constant time detection circuit 50 (FIG. 3) receives signals A ₁ ,
Decoders 134 and 13 each input A ₂ and output code signals divided at regular intervals such as every 10 minutes.
6, and OR gates 138 and 140 inputting the outputs of the respective decoders 134 and 136, respectively.
One-shot multibrator 142, 144 inputs signals C ₁ and C ₂ from FF 8, respectively, signals from OR gates 138, 140 and switching circuit 52.
AND gates 146 and 148 input E ₁ , J ₆ and E ₂ and J ₈ respectively, and AND gates 146 and 148 input the signals from the one-shot multivibrators 142 and 144 as they are, and input the inverted signals J ₆ and J ₈ respectively. Gates 150, 152 and AND gates 146, 1
It consists of OR gates 154 and 156 which input the output signals of 50, 148 and 152, respectively, and an FF 158 which inputs the output signals to set input S and reset input R, respectively.

The switching circuit 52 (FIG. 4) includes a counter 16 which inputs the signals C ₂ and C ₁ to the reset input R, respectively.
0, 162 and their output signals J ₁ and J ₈ to their respective set inputs S, and input a signal I obtained by inverting the signal from the start switch 10 by an inverter 11 to the reset input R;
One-shot multivibrators 168 and 170 input signals C ₂ and C ₁ , respectively, and FF 164,
The output signals J ₅ and J ₇ of 166 are input to one input, respectively, to create one-shot multivibrators 168 and 17.
AND gates 172 and 174 input the output signals J ₃ and J ₄ of 0 to other inputs, respectively, and FF 164,
AND gates 176 and 1 input the output signals J ₆ and J ₈ of 166 into one input, respectively, and input the signals E ₁ and E ₂ from the fixed time detection circuit 50 into other inputs, respectively.
78, and an OR gate 180 which inputs all the output signals of the AND gates 172 to 178 and outputs a signal _J13 .

The audio signal generation circuit 64 (FIG. 5) has a start address designation ROM 182 and an end address designation ROM 1 that input signals from the multiplexer 58 and designate a start address and an end address.
84, an address counter 186 that operates by inputting the signal _M3 from the voice start circuit 66 to the clock input φ, and its output signal and end address designation.
A digital comparator 188 that compares the output signal of the ROM 184, an AND gate 190 that inputs the output signal to one input terminal and inputs the signal L from the FF 60 to the other input terminal, and an AND gate 190 that inverts only this signal L. It is comprised of an AND gate 192 that inputs data read from the audio ROM 62, a DA converter 194 that inputs data read from the audio ROM 62, and a low-pass filter 196 that inputs its output signal.

Next, the operation of the circuit shown in FIGS. 2 to 5 will be explained using the time charts shown in FIGS. 6 to 12.

As mentioned above, the audio notification of the game clock in this embodiment is made at regular intervals when the operation interval of the bistable switch 6 is within a certain period of time, and when this operation interval exceeds a certain period of time, the audio notification of the game clock is made. Notifications will be made depending on the operation. Therefore, the fixed time detection circuit 50 (Fig. 3) and the switching circuit 52 (Fig. 4)
The operation will be explained first using the time chart shown in FIG.

As mentioned above, the subtraction counters 20 and 22 operate corresponding to the first move and the second move, respectively, and now, as shown in FIG. 6, the bistable switch 6 is turned on in the direction shown in FIG. 1, and the signal is output. When _C1 is at H level and the subtraction counter 20 is operating, the decode 134 in the fixed time detection circuit 50 inputs the signal _A1 from the subtraction counter 20 and outputs a pulse to each output every 10 minutes. . The pulse output by this decoder 134 is the output signal of the OR gate 138.
Occurs on E ₁ .

On the other hand, the counter 160 in the switching circuit 52 is released from reset when the signal _C2 becomes L level, and starts counting by inputting the clock signal φ. Since the FF 164 is reset by the signal I from the inverter 11 in the initial state, its output signals J ₅ and J ₆ are normally L and H, respectively.
level, and in this state, the AND gate 176 is in an open state.

Therefore, the pulse generated in the signal E ₁ becomes the output signal J ₁₀ of the AND gate 176 in the switching circuit 52.
The signal is generated through the OR gate 180.
Occurs on J ₁₃ and starts voice notification operation. Also,
Since the signal _J6 is at H level, the fixed time detection circuit 50
The AND gate 146 inside is in an open state,
The pulse generated in the signal _E1 is applied to the set input S of the FF 158 via the AND gate 146 and the OR gate 154 to set it. Therefore, the signal _E3 becomes H level, and the player is in a state where the time remaining for the first move is notified.

After that, as shown in FIG. 6, when the bistable switch 6 is switched and the signal _C2 becomes H level,
The subtraction counter 22 operates, and the decoder 136 in the fixed time detection circuit 50 outputs a pulse to each output every 10 minutes, and this pulse is sent to the OR gate 140.
Generated via signal E ₂ .

On the other hand, the counter 160 in the switching circuit 52 returns to the original reset state again when the signal C ₂ becomes H level before counting up, and when the signal C ₁ becomes L level, the counter 160 again returns to its original reset state.
2 starts counting. In addition, the output signals J ₇ and J ₈ of the FF166 are each at the L level similarly to the FF164, thereby causing the AND gate 1
78 is in the open state.

The pulse generated in this signal _E2 is transmitted to the switching circuit 5.
A signal _J13 is generated through an AND gate 178 and an OR gate 180 in J2 to start the audio notification operation. Furthermore, since the signal J ₈ is at the H level, the AND gate 148 in the fixed time detection circuit 50 is in an open state, and the pulse generated in the signal E ₂ is passed through the AND gate 148 and the OR gate 156.
Applied to reset input R of FF 158 to reset it. Therefore, the signal _E3 goes to L level, and the player is in a state where he/she is notified of the time remaining on the draw.

Thereafter, if the bistable switch 6 is switched before the counter 162 counts up, the counter 162 is reset, the counter 160 starts counting again, and the above operation is repeated.

Now, when the signal C ₁ is at H level and the signal C ₂ is at L level, and the counter 160 is operating, if the first player is thinking for a long time, before the bistable switch 6 is operated. The counter 160 counts up and generates a pulse in its output signal _J1 . The FF 164 is set by this pulse, and its output signals J ₅ and J ₆ become H and L levels, respectively. Therefore, the AND gate 172 is opened instead of the AND gate 176, and the signal
Even if a pulse occurs on E ₁ , no pulse will occur on signal J ₁₃ .

Here, the bistable switch 6 is operated and the signal C ₂
When the signal becomes H level, a pulse is output from the one-shot multivibrator 168, a pulse is generated in the signal _J13 via the AND gate 172 and the OR gate 180, and audio notification is started.

Furthermore, when the signal _C2 becomes H level, the one-shot multivibrator 142 in the fixed time detection circuit 50 outputs a pulse, and the AND gate 150, which is in an open state because the signal _J6 has already become L level, A pulse is generated in the output signal of the OR gate 154. As a result, the FF 158 enters the set state, and the signal _E3 goes to H level to notify the time remaining for the first move.

After that, when the signal C ₂ becomes H level and the counter 162 operates and counts up and a pulse is generated in its output signal J ₂ , the FF 166 is set and its output signals J ₇ and J ₈ are set to H, respectively. Become L level. Therefore, when the AND gate 174 becomes open and the signal C ₁ becomes H level, the pulse output from the one-shot multivibrator 170 becomes the output signal J ₁₁ of the AND gate 174.
and the output signal of the OR gate 180
It occurs on J ₁₃ and audio notification starts.

Also, the AND gate 1 in the fixed time detection circuit 50
52 becomes open because the signal J ₈ becomes L level, and the pulse output from the one shot multivibrator 144 when the signal C ₁ becomes H level is the AND gate 152 and the OR gate 156.
to reset it. Therefore, the signal _E3 goes to L level, and the player is in a state where he/she is notified of the time remaining on the draw.

In this way, when the time taken for each player to make one move is within a certain period of time, a pulse is generated in the signal J ₁₃ at a certain period of time to start the notification operation, and when the time period exceeds the certain period, the bistable switch 6 is activated. Each time it is operated, a pulse is generated to start the notification operation.

Next, the operation of the circuit shown in FIGS. 2 and 5 will be explained.

As mentioned above, pulses are generated in the output signal _J11 of the switching circuit 52 at fixed time intervals until the time required for one move by each opponent exceeds a fixed time.

Now, a pulse is generated in the output signal _E1 of the fixed time detection circuit 50, and in response to this, as described above, a signal is generated.
When _E3 becomes H level, the multiplexer 104 in the time audio code output circuit 56 becomes in a state to output the signal _A1 from the subtraction counter 20, and the multiplexer 102 outputs the signal A1 from the subtraction counter 20.
The code ROM 92 is now ready to output signals, and these output signals are applied to the multiplexer 106 along with the output signals of the other code ROMs 96-100.

As will be described later, the outputs _Q0 to _Q5 of the counter 108
When successively becomes H level, this multiplexer 1
All the signals sequentially output from the multiplexer 106 are applied to the multiplexer 58, and since the normal signal L is at the L level, the multiplexer 58 transfers the signal from the multiplexer 106 to the audio signal generating circuit 64.
to be applied.

On the other hand, when a pulse is generated in the signal _J13 , the counter 108 in the time audio code output circuit 56 is reset and its output _Q0 becomes H level, and a pulse is also generated in the signal ₁ via the OR gate 126. FF 130 is set by the pulse generated in this signal _M1 .

When FF130 is set, its output signal M ₂
becomes H level, which causes AND gate 1
32 becomes open, and the clock signal _φ1 is generated as its output signal _M3 .

The address counter 186 in the audio signal generation circuit 64 (FIG. 5) is activated when this signal _M3 is input, and has already been input to the multiplexers 102, 106, 58.
A signal from the "Sente" code ROM 92 is applied to the start address designation ROM 182 via the start address designation ROM 182, and the address counter 186 reads data from the audio ROM 62 from the start address a of the audio "Sente" corresponding to this signal. Converter 194, low pass filter 196 and sound generation circuit 6
The voice "sente" is emitted through the address counter 8, and the output signal of the address counter 186 at this time is also applied to the digital comparator 188.

On the other hand, the signal from the multiplexer 58 is also applied to the end address designation circuit 184, and this end address designation circuit 184 applies the end address a+b of the voice "Sente" corresponding to the input signal to the digital comparator 188.

In this way, when the end address a+b from the end address designation ROM 184 of the final address of the voice "Sente" designated by the address counter 186 is applied to the digital comparator 188, the digital comparator 188 detects that the input signals match. Generate one pulse in the output signal.

This pulse is generated at the output signal H of the AND gate 192, which is normally open, and is applied to the clock input φ of the counter 108 through the OR gate 122 (FIG. 2), which advances the count of the counter 108. The output _Q1 is set to H level.

When the output _Q1 of this counter 108 becomes H level, the multiplexer 106 outputs the signal from the "AT" code ROM 96, and similarly to the operation described above, the start address designation ROM 182 in the audio signal generation circuit 64 and the end address designation
The ROM 184 sequentially outputs the start address c and end address c+d of the voice "ato". Therefore, the address counter 186 reads data from the audio ROM 62 according to the start address, and outputs the audio "ato" from the sound generation circuit 68.
is issued, and at this time digital comparator 1
The final address and end address c+d of the voice "ato" designated by the address counter 186 are applied to 88, and this digital comparator 188 detects that the input signals match and generates a pulse again in its output signal.

This pulse is generated by the signal H, similar to the operation described above.
occurs, and the counter 108 increments the count.

In this way, the counter 108 advances the count by the pulses sequentially generated in the signal H, and the multiplexer 106 outputs "sente", "ato", "ichi", etc.
Each code signal of "Jikan", "Sanjiyutsu", and "Pun" is outputted, and the sound "Sente at Ichi Jikan Sanjiyutsu Pun" is outputted through the multiplexer 58, the audio signal generation circuit 64, and the sound generation circuit 68 as shown in FIG. is emitted.

When this sound is emitted, the final pulse generated in the signal H causes the output _Q6 of the counter 108 to go to the H level, which causes a pulse to be output from the one-shot multivibrator 124, which resets the FF 130 via the OR gate 128. The AND gate 132 is closed and the notification operation ends.

Thereafter, when the bistable switch 6 shown in FIG.
A pulse is generated in the output signal _E2 of _the fixed time detection circuit 50 which inputs the signal _A2 from
A pulse is generated in the output signal _J13 of.

In this way, when the signal _E3 becomes L level, the multiplexer 10 in the time audio code output circuit 56
4 and 102 are switched to output the signal A ₂ and the signal from the "trowel" code ROM 94, respectively.

Therefore, as described above, the pulse generated in the signal _J13 causes the output signal of the voice start circuit 66 to
When the clock signal _φ1 is generated at _M3 , a pulse is generated in the output signal H of the audio signal generation circuit 64, the counter 108 is activated, and the multiplexer 106 sequentially outputs "gote", "ato", "san", " Jikan”, “
The code signals "nijiyu" and "pun" are output, and the sound "gote" is outputted through the multiplexer 58, the sound generation circuit 64, and the sound generation circuit 68 as shown in FIG.
Ato San Jikan Nijiyu Pun” is uttered.

After that, if the first player does not make any progress for a certain period of time,
As described above, when the bistable switch 6 is operated, a pulse is generated in the output signal _J13 of the switching circuit 52.

As shown in FIG. 8, when the bistable switch 6 is switched and the signal C ₂ is set to H level, the signal J ₁₃ is activated periodically at the rising edge of the signal C ₂ as described above.
A pulse is generated.

At this time, the bistable switch 6 is switched to the direction of measuring the holding time of the second hand, but as described above, the output signal E ₃ of the fixed time detection circuit 50 is high.
level, so multiplexer 104, 102
are respectively signal _A1 and "Sente" code ROM92
It is now ready to output signals from.

Therefore, the voice "Sente ato ichi jikan sanjiyutsu pun" is emitted by the same operation as the time limit notification for the first move described above.

Also, if the second mover does not move forward for a certain period of time, the bistable switch 6 is switched and the signal _C1 goes to H level, and the duration of the first move is measured, as in the operation described above. The voice says, “Gote ato ichi jikan nijiyutsu pun.”
It is uttered as follows.

Thereafter, when the remaining time of one or both of the first move and the second move becomes less than one hour, the "0" time detection circuits 70 and 74 in the zero time detection circuit 48 output the signals A ₁ and A ₂ from the subtraction counters 20 and 22, respectively. It is detected that the time has changed from 0 to 0, and the output signals B ₁ and B ₃ are set to H level.

Now, when the signal E ₃ is at H level and the signal B ₁ goes to H level while the time for the first move is being measured, the output signal of the AND gate 110 in the time audio code output circuit 56 goes to H level, and the OR gate 116 is activated. Via the signal _N3 occurs. Therefore, the AND gate 118 is in an open state, and as mentioned above, the signal
A pulse is generated at J ₁₃ to start the voice notification operation, and the counter 108 is advanced. When the output Q ₂ or Q ₃ of the counter 108 becomes H level, the output signal N ₂ of the OR gate 114 also goes to H level. , and the output signal _N4 of the AND gate 118 also becomes H.
become the level.

Therefore, the AND gate 120 is also opened, and the clock signal _φ1 is generated as its output signal _N5 .

The clock signal φ ₁ generated on the signal N ₅ is applied to the counter 108 via the OR gate 122.
Fast forward that count. Therefore, when the outputs Q _{2 and} Q ₃ of the counter 108 for outputting the audio code of the hour digit from the multiplexer 106 go to H level, the count of the counter 108 is immediately fast-forwarded, and the audio code of the hour digit, for example, the audio ”,
Before the "time" code is output from the multiplexer 106, the next minute digit audio code is output. As a result, the audio signal generation circuit 64 reads out the audio code excluding the audio code of the hour digit from the audio ROM 62, and the sound generation circuit 68 emits the audio "Sente ato gojiyu pun" as shown in FIG.

Next, when the signal E ₃ is at the L level and the signal B ₃ goes to the H level while measuring the duration of the second hand, the output signal of the AND gate 112 in the time audio code output circuit 56 goes to the H level, and this causes Then, the output signal _N3 of the OR gate 116 becomes H level. The subsequent operation is the same as that described above, and the sound generation circuit 68 emits the sound ``Gote Ato Sanjiyutsu Pun'' as shown in FIG.

In addition, if the remaining time for one or both of the first move and the second move becomes less than one hour, and the first move or the second move does not proceed for a certain period of time, the bistable switch 6 is operated as shown in Figure 10. when the signal
A pulse generated at _J13 causes an audio notification of the remaining time by an operation similar to that described above.

After that, when one of the opponents runs out of time, the "0" time detection circuit 70 and the "0" minute detection circuit 72 or the "0" time detection circuit 74 and the "0"
The minute detection circuit 76 detects this and outputs its output signal B ₁ , B ₂ or
B ₃ and B ₄ become H level.

That is, when the time for the first move runs out, the signal B ₁ ,
_B2 goes to H level, and the output signal _B5 of AND gate 78 goes to H level.When the time on the back side runs out, signals _B3 and _B4 go to H level, and the output signal _B6 of AND gate 80 goes to H level. Becomes H level.

Therefore, the output signal of AND gate 78 or 80 corresponding to the opponent whose time runs out first
B ₅ or B ₆ becomes H level and is applied to the multiplexer 90 in the end audio goat output circuit 54.

This multiplexer 90 is in a state where it outputs the signal from the "Gotenokachi" code ROM 88 when the signal B ₅ goes to H level, and also when the signal B ₆ goes to H level.
When you reach the level "Senteno Kachi" code ROM8
The state is such that the signal from 6 is output.

Further, when one of the signals B ₅ and B ₆ goes to H level, the output of the OR gate 82 goes to H level, thereby causing the one shot multivibrator 84
A pulse is generated in the output signal _B7 of.

When a pulse is generated in this signal _B7 , the FF 60 is set and its output signal L becomes H level.

When this signal L becomes H level, the multiplexer 58 switches to a state in which it outputs the signal from the multiplexer 90 in the end audio code output circuit 54, and the audio signal generation circuit 64 which inputs this signal
The start address specification ROM 182 and the end address specification ROM 184 inside are the voice "Gotenokachi".
Or memorize the start address and end address of "Senteno Kachi".

On the other hand, the pulse generated in signal B ₇ is also generated in output signal M ₁ of OR gate 126 to set FF 130, thereby generating clock signal φ ₁ in output signal M ₃ of AND gate 132. This signal M ₃ causes the audio signal generation circuit 64 to read the data of the audio ROM 62 from the address specified by the start address designation ROM 182 mentioned above, and output the data to the D-A converter 194 and the low-pass filter 1.
96 and the sound generation circuit 68, the voice "Gotenokachi" or "Sentenokachi" is generated.

At this time, when the address counter 186 specifies the end address of the voice "Gotenokachi" or "Sentenokachi", the digital comparator 188 detects that the output signal of the address counter 186 and the output signal of the end address designation ROM 184 match. Output pulse. This pulse is generated in the output signal K of the AND gate 190, which is in an open state because the signal L is at the H level.
The FFs 60 and 130 are reset and the audio notification operation is ended.

In this way, in this embodiment, each opponent's 1
Until the time it takes to complete the rotation exceeds a certain amount of time, the elapsed time is audibly announced at predetermined intervals, and when the elapsed time is exceeded, the elapsed time is audibly announced in response to the operation of the bistable switch 6. .

(f) Effects of the Invention According to the present invention, an audio notification is provided at regular intervals at the beginning of the gate where the opponent moves quickly, and when a stalemate occurs towards the end of the game, an audio notification is provided in response to the switch operation. It is possible to make voice announcements without affecting the psychological state of the person.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of a game clock according to an embodiment of the present invention, and FIG. 2 is a diagram showing a zero time detection circuit, an end voice code output circuit, a time voice code output circuit, and a voice start circuit shown in FIG. 1. 3 is a diagram showing a detailed circuit configuration of the fixed time detection circuit shown in FIG. 1, and FIG. 4 is a diagram showing a detailed circuit configuration of the switching circuit shown in FIG. 1. , FIG. 5 is a diagram showing a detailed circuit configuration of the audio signal generation circuit shown in FIGS. 1 and 2, and FIGS. 6 to 12 are time charts. 2... Oscillator, 4... Frequency dividing circuit, 6... Bistable switch, 20, 22... Subtraction counter, 48...
... Zero time detection circuit, 50 ... Fixed time detection circuit, 5
2...Switching circuit, 54...End audio code output circuit, 56...Time audio code output circuit, 58...
Multiplexer, 62... Audio ROM, 64...
Audio signal generation circuit, 66...Audio start circuit, 68
...pronunciation circuit.

Claims (1)

[Scope of Claims] 1. A reference signal generator, a bistable switch, and two sets of subtraction counters in which clock pulses from the reference signal generator are counted and stopped in a reciprocal manner by operation of the bistable switch. , an audio signal generation circuit that generates an audio signal based on the count value of the subtraction counter; a sound generation circuit that generates audio based on the audio signal from the audio signal generation circuit; a fixed time detection circuit that outputs a detection signal every time the bistable switch is operated; an operation detection circuit that detects that the bistable switch is operated; and an operation detection circuit that detects that the operation time interval of the bistable switch exceeds a predetermined time. an operation interval detection circuit; and in response to the signal from the operation interval detection circuit, the detection signal from the fixed time detection circuit is operated to the audio signal generation circuit until the operation time interval of the bistable switch reaches a predetermined time or more. a selection gate circuit that applies the detection signal from the operation detection circuit as an operation signal to the audio signal generation circuit when the operation time interval of the bistable switch exceeds a certain time. A voice game clock.