JPH0375905B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image memory device used in a pattern recognition device or the like. Conventionally, address generation in an image memory device is performed using the first
As shown in the figure, a method of directly specifying a memory address by a program, or a method of incrementing the directly specified value by +1 as shown in FIG. 2, etc., have been implemented. By the way, conventional image memory devices have the following problems and demands. That is, (1) The image data is a two-dimensional data array as shown in FIG. 3, but the image memory has a one-dimensional array and structure as shown in FIG. For this reason, conventionally, reading and writing two-dimensional data was calculated by a program and the results were specified, making it difficult to increase the speed. (2) It takes a certain amount of time for memory address data to become readable and writable after the address is specified (until the address data used last time is replaced with the address data used this time).
This results in wasted time after address specification. (3) Since data in the image memory is processed by repeatedly reading and writing several times, address generation must be simple and fast. (4) An image memory device that stores a large amount of image data needs to be able to easily expand its memory capacity. (5) It is desirable to be able to generate a new address signal when data at a certain address is read and written to the same address, and vice versa. This invention was made in view of the above circumstances.
The object is to provide an image memory device that can read and write a large amount of image data simply and quickly, and one-dimensional array data as if it were two-dimensional array data. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 5, 1 is a memory address calculator, 2 is an address modification register, and 3 is an image memory. Signals are input to the address calculator 1 and the address modification register 2 from a computer and other control devices 21, respectively. In other words, the calculation unit 1
A control signal is input to the CM terminal via the control bus 4 to designate an operation. The address signal of the image memory 3 is input to the A terminal via the address bus 5, and the address modification register 2 is input to the B terminal.
The address modification signal output from the address modification signal is input.
The address modification register 2 receives the data from the data bus 6 and the control signal from the control bus 4, and transfers the address modification data to the address calculator 1.
send to The memory address calculator 1 performs various address calculations based on the input signals, and sends an address signal to the image memory 3 from the Q terminal via the memory address bus 7. Further, read signals and write signals are sent from the control device 21 to the image memory 3. Image data is transmitted via the image data bus 8 in accordance with the address signal generated as described above. Reference numeral 9 denotes a decoder, to which the control signal 4 is input together with the write signal and the read signal, and the transmission of the image data is completed, and this completion signal causes the specification by the read and write post-calculation commands to be input. If there is, a memory address data latch signal is output to the address calculator 1. and,
This address calculator 1 calculates the memory address again and prepares for the next data transmission. FIG. 6 shows a specific configuration of the memory address arithmetic unit 1, in which the register 10, the arithmetic unit 11
and a register 12. The following table shows an example of the arithmetic functions of this memory address arithmetic unit 1.

[Table] Next, the operation of the present invention will be described with reference to FIG. 7 regarding an example of a projection method for image processing. Image data group (M+1) of two-dimensional data shown in Figure 8
When converting (N+1) into one-dimensional data using a projection method and compressing the data, the X-axis projected image Px()
is Px()= _N 〓 ^J=0 P{I+(M+1)J}, and the image memory address x is X=I+(M
+1) Must be generated by calculation J. Similarly, the Y-axis projected image P _Y (J) is P _Y (J)= _M 〓 ^I=0 P{I+(M+1)J}. However, I; X-axis projected image Ith J; Y-axis projected image Jth M+1; number of image memories in the X-axis direction N+1; number of image memories in the Y-axis direction It can be seen that the sum of image data from 0 to M is calculated while adding +1. Furthermore, it can be seen that the X-axis projection image is obtained by calculating the sum of image data from 0 to M while sequentially adding +1 to the address of the image memory. Also, the X-axis projected image is 0 while adding the value of M+1.
It is to find the sum of image data of ~N, and N
At the time of the second addition, an analysis is generated from the upper analysis of the adder in the memory address arithmetic unit 1, so by adding this to the analysis of the lowest order, the memory address modification shown in FIG. 8 is possible. That is, in the present invention, whereas memory addresses were previously generated by specifying absolute addresses, a method is adopted in which memory addresses are specified by relative addresses in a secondary array as shown in FIG. 7 using a hardware configuration. Therefore, the operation efficiency is high and high speed is possible. In general, image memory has a large capacity, and all image data is not processed, but only the part shown by P in Figure 9 is processed, and the part shown by Q, which is slightly shifted from this position, is processed. The main method is to sequentially move the processing target (specified by relative address). Therefore, when performing pattern recognition and image processing, the relative address designation is processed by hardware in a separate system from the program, which simplifies the program. Further, after data is transmitted from the image memory, the next memory address is calculated in advance by hardware and set in the register 12, so that reading and writing can be performed almost at the operating speed of the memory element. (In the example, a memory element with an access time of 55 nsec was used.
80nsec, 8KB). Furthermore, since it is a relative address system, the memory capacity can be expanded regardless of the size of the memory address bus. Furthermore, since memory addresses are generated by hardware, the number of program steps is reduced and processing speed is improved. Furthermore, since it is possible to specify in a program that a memory address is calculated when reading and writing to the image memory, flexible address modification is possible. In addition, the present invention calculates and sets the image memory address using dedicated hardware different from the control device (corresponding to the CPU), and performs high-speed reading of image memory data using hardware independent of the CPU control software. Enable writing. In addition, since there is the above-mentioned memory address calculator and address modification means, partial processing of the image memory (specifying only a certain part of one screen) and +n (n is 1 or more), which is different from the unique designation of +1 as shown in Fig. 2, are performed. , continuous designation in the vertical direction (horizontal direction, diagonal direction designation, etc. can be arbitrarily selected) as shown in FIG. 8. Furthermore, the program for the control device can be greatly simplified since it is only necessary to perform operations at the nodes of address arithmetic control. Figure 10 shows the one-dimensional memory as the two-dimensional value (X,
2 ₁ is an address modification register in the vertical (Y) direction, and 2 ₂ is an address modification register in the horizontal (X) direction. The present invention can be applied as temporary storage (high-speed image memory buffer) for video signals such as television signals, which require high-speed memory because they are high-speed signals of about 100 nsec/pixel. Further, it can be used as an image memory of an image data processing device.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams showing conventional memory address generation methods, Figure 3 is a diagram in which the array of memory elements has been rearranged into an array of two-dimensional image data, and Figure 4 shows the array of memory elements. 5 is a block diagram showing one embodiment of the present invention, FIG. 6 is a block diagram showing an enlarged part of the memory address calculator in FIG. 5, and FIG. 7 is a block diagram showing the operation of the above embodiment. FIG. 8 is a diagram showing an example of the sequence of memory address specification in the above embodiment, FIG. 9 is a diagram showing cutting out a partial image of the image memory and movement of the cutting position, and FIG. FIG. 3 is a block diagram showing another embodiment. 1...Memory address calculator, 2...Address modification register, 3...Image memory, 9...Decoder, 12...Register, 21...Control device.

Claims (1)

[Scope of Claims] 1. An image memory 3 capable of reading and writing image data in a two-dimensional array, and an apparatus that executes a program, controls reading and writing of the image memory 3, and executes the program. A control device 21 that causes separate hardware to perform address calculations for the image memory 3 in parallel, and the hardware includes: an arithmetic unit 11 that selectively performs a plurality of types of calculations;
A register 12 is provided between the arithmetic unit 11 and the image memory 3, and supplies a memory address to the image memory 3 and provides feedback as an input for calculation to the arithmetic unit 11. , a memory address calculator 1 that performs calculations for two-dimensional relative addressing of the image memory 3 based on address signals from the address bus 5, address modification signals, and calculation designation signals from the control device 21; , address modification means 2 which receives data and control signals from the control device 21 and supplies the address modification signal to the memory address calculator 1;
and, in accordance with a control signal from the control device 21, the arithmetic unit 1 is operated in parallel with the image data processing by the control device 21 and the access to the image memory 3.
1 to perform address calculation, after the access to the image memory 3 is completed, the memory address from the calculation unit 11 is transferred to the register 12, and an address for the next image memory access and address calculation is generated. and a decoder 9 for controlling the register 12.