JPH0379714B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video interface device that samples a video input signal from a video signal sending device using a sampling clock and outputs the sample as a video output signal. It is related to.

[Conventional technology]

A video interface device samples a video input signal sent from a video signal sending device and sends it to a color printer or the like. In such a video interface device, sampling is performed using a sampling clock. Therefore, if the sampling clock and the video input signal do not have an appropriate phase relationship, the video input signal will not be properly latched into the sampling circuit, and accurate sampling will not be possible. For example, in a printer's video interface device, dropped dots and dots are misaligned, and in a color printer, color misregistration occurs. For this reason, video interface devices require measures to adjust the sampling clock and video input signal to have an appropriate phase relationship.

Conventionally, video interface devices that have taken such measures have, for example, compared the print results of a printer with image data on a CRT on the video signal sending side to determine whether or not the phase relationship is appropriate. In some cases, a selective delay circuit is used to change the phase of the sampling clock so that the phase relationship is appropriate.

However, such a video interface device has the problem that it is troublesome because it is impossible to determine whether the image is suitable or not unless it is printed.

[Problem that the invention seeks to solve]

The present invention has been made in order to eliminate the above-mentioned problems, and an object thereof is to realize a video interface device that can determine in real time whether or not the phase relationship between a video input signal and a sampling clock is appropriate while sampling. do.

[Means for solving problems]

The present invention provides a video interface device that samples a video input signal from a video signal transmission device using a sampling clock and outputs the sample as a video output signal, comprising: a change in the video input signal or a delayed signal of the signal; an error detection circuit that detects a latching error in a video input signal sampling circuit based on the state of the video output signal at the time; A video interface device comprising a selective delay circuit that changes the phase relationship between a video input signal and a sampling clock so that the video input signal and the sampling clock are latched.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a video interface device according to the present invention.

In FIG. 1, 10 is an interface control circuit, 20 is a write/read control circuit, 30 is an address counter, 40 is a memory, 50 is a clock oscillator, 60 is a phase synchronization circuit, 70 is a selective delay circuit, and 80 is a sampling circuit. 90 is an error detection circuit, and 100 is an error display means.

VSYNC, HSYNC and VIDEO IN are vertical synchronization signal, horizontal synchronization signal and video input signal,
These are sent from a video signal sending device.

An interface control circuit 10 controls the entire device.

The write/read control circuit 20 receives a horizontal synchronization signal
Based on HSYNC, the vertical synchronization signal VSYNC, and commands from the interface control circuit 10, a signal is sent to the address counter 30 to control writing and reading of the memory 40.

The memory 40 stores information sampled by the sampling circuit 80.

The clock oscillator 50 is a sampling clock.
Generate CLK.

The phase synchronization circuit 60 receives the sampling clock from the clock oscillator 50 and the horizontal synchronization signal HSYNC.
In response to this, these signals are synchronized, and the signals are sent to the address counter 30 and the selective delay circuit 70.

The selective delay circuit 70 changes the phase relationship between the video input signal and the sampling clock based on the signal from the error detection circuit 90.

The sampling circuit 80 includes the selective delay circuit 70
The video input signal VIDEO IN is sampled and outputted as a video output signal by timing with the sampling clock CLK1 from .

The error detection circuit 90 detects whether the video input signal is latched to the sampling circuit 80 based on the video input signal and the video output signal.

The error display means 100 includes an error detection circuit 90
Displays an error message when an error is detected.

Next, the specific structure of the portion that characterizes the present invention will be explained.

FIG. 2 is a diagram showing the main part of FIG. 1. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals.
The same applies to the following figures.

In the selective delay circuit 70, 71 is a delay means, which provides five types of delay times τ ₁ to _{τ 5} to the sampling clock sent from the phase synchronization circuit 60. Reference numeral 72 denotes a changeover switch, which switches the sampling clocks having five types of delay times so that they are selectively sent to the sampling circuit 80.

The sampling circuit 80 is a D-type flip-flop circuit, and the D terminal receives a video input signal.
VIDEO IN (hereinafter referred to simply as VIDEO IN), T
The sampling clock CLK1 from the selective delay circuit 70 is applied to the terminal, and the video output signal VIDEO OUT (hereinafter simply referred to as VIDEO
OUT) is output.

In the error detection circuit 90, 91 is a delay circuit that provides a delay time τ to VIDEO IN. Below, the signal given this delay time is
DELAYED VIDEO. 92 and 93 are D
This is a type of flip-flop circuit. The flip-flop circuit 92 has VIDEO OUT and
Signals from the delay circuits 91 are applied to the T terminals, and the circuit e ₁ is output from the terminals. The flip-flop circuit 93 has VIDEO on the D terminal.
Signals from the delay circuit 91 are applied to the OUT and T terminals, respectively, and a signal e ₂ is output from the Q terminal. 94 is an OR gate, which calculates the OR of signals e ₁ and e ₂ and outputs the result.

In the error display means 100, 101 is a mono multivibrator, and 102 is an LED. When an error is detected by the error detection circuit 90, the mono multivibrator 101 receives the error signal ERROR from the OR gate 94 and outputs the LED 10.
2 to display an error message.

[Effect]

Next, the operation of such a video interface device will be explained.

3 and 4 are time charts for explaining the operation.

input to flip-flop circuit 80
When the phases of VIDEO IN and the rising edge of sampling clock CLK are not within the range D as shown in Figure 3, VIDEO IN is transmitted correctly;
As shown in FIG. 4, when it is within the range of D, it will not be transmitted correctly. Here, the range of D is occupied by the data set-up time _tDS and data hold time _tDH of the flip-flop circuit 80.

The correctness or failure of signal transmission is detected as follows.

Assuming that the times during which VIDEO IN is in the HIGH state and the LOW state are t _WH and t _WL , the delay time τ of the delay circuit 91 is shorter than t _WH - t _DS .

Here, the data propagation delay time of flip-flop circuit 80 and the data set-up time and data hold time of flip-flop circuits 92 and 93 are ignored.

The flip-flop circuit 92 connects the VIDEO OUT
is transmitted to the terminal at the rising edge of DELAYED VIDEO. Furthermore, the flip-flop circuit 93 is
Transmit VIDEO OUT to terminal Q at the falling edge of DELAYED VIDEO. That is, the flip-flop circuit 92 outputs a LOW signal from the terminal if VIDEO OUT is in the HIGH state when the rising edge of DELAYED VIDEO is input, and the flip-flop circuit 93 outputs a LOW signal from the terminal when the rising edge of DELAYED VIDEO is input.
VIDEO OUT is input when the falling edge of
When in the LOW state, a LOW level signal is output from the Q terminal.

As shown in the time chart in Figure 3,
If VIDEO IN is transmitted correctly,
VIDEO OUT at the start of DELAYED VIDEO
is in HIGH state and DELAYED VIDEO
VIDEO OUT is in the LOW state when the signal falls. As a result, the signals e ₁ and e ₂ remain in the LOW state, and the output of the OR gate 94 is at the LOW level, so no error is detected.

On the other hand, as shown in the time chart in Figure 4,
If VIDEO IN is not transmitted correctly, the signal shown by the broken line that should be transmitted is not transmitted, _so VIDEO
Since OUT is in the LOW state, the signal _e1 is in the HIGH state. As a result, the output signal of the OR gate 94 becomes HIGH. The mono multivibrator 101 receives this signal and lights up the LED 102 to display an error message.

When an error is displayed, the delay means 71
In this case, a delay time is added to the sampling clock so that the LED 102 is not turned on. This provides a proper phase relationship.

Such error detection can be done using DELAYED
This is done at each change point (rise and fall) of VIDEO.

In the time chart for explaining operation, the period of VIDEO IN is equal to t _WH + t _WL . Since t _WH =t _WL in a normal TTL level video signal, such a case is also explained in the present invention.

FIG. 5 is a diagram showing the main part of another embodiment of the interface device according to the present invention.

In this device, only a flip-flop circuit 92 is provided, and a delay circuit 91 and an OR gate 94 are provided.
is omitted.

According to the apparatus having such a configuration, error detection is performed based on the video output signal at the rising edge of the video input signal.

According to such a device, the configuration can be simplified compared to the device shown in FIG. especially,
This is effective when processing R, G, and B color video signals.

Note that only the flip-flop circuit 93 may be provided.

Further, the video input signal may be an R, G, B color video signal. In this case, it is necessary to provide three error detection circuits 90 in parallel.

〔effect〕

According to such a video interface device, the following effects can be obtained.

The error detection circuit 90 detects whether the phase relationship between the video input signal and the sampling clock is appropriate when the video input signal or its delayed signal changes. This makes it possible to determine in real time whether the phase relationship between the video input signal and the sampling clock is appropriate. Further, the implementation means is an inexpensive circuit shown in FIGS. 2 and 5.

Further, when an error is detected by the error detection circuit 90, the phase of the sampling clock is changed by the selective delay circuit 70 so that the phase relationship is appropriate. This allows for reliable sampling.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a video interface device according to the present invention, and FIG.
3 and 4 are explanatory diagrams of the operation of the device shown in FIG. 1, and FIG. 5 is a block diagram showing the main portion configuration of another embodiment of the video interface device according to the present invention. It is a diagram. 50... Clock oscillator, 70... Selective delay circuit, 80... Sampling circuit, 90... Error detection circuit.

Claims (1)

[Scope of Claims] 1. A video interface device that samples a video input signal from a video signal transmission device using a sampling clock and outputs the sample as a video output signal, comprising: a delay of the video input signal or the signal; an error detection circuit that detects a latching error in a video input signal sampling circuit based on the state of the video output signal when the signal changes; A video interface device comprising a selective delay circuit for changing the phase relationship between a video input signal and a sampling clock so that the signal is properly latched.