JPH0379715B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video interface device that samples a video input signal from a video signal sending device using a sampling clock and outputs the sample as a video output signal. It is related to.

[Conventional technology]

A video interface device samples a video input signal sent from a video signal sending device while keeping timing with a sampling lock, and sends the sample as a video output signal to a color printer or the like. In such a video interface device, if the sampling clock and the video input signal do not have an appropriate phase relationship, the video input signal will not be properly latched into the sampling circuit, and accurate sampling will not be possible. For example, in a printer's video interface device,
Dropped dots and misaligned dots occur, and in color printers, color misalignment occurs. For this reason, video interface devices require measures to adjust the sampling clock and video input signal to have an appropriate phase relationship.

A video interface device equipped with such measures is disclosed in the patent application filed in 1983 by the present applicant.
No. 239900 "Video Interface Device" was published. In this video interface device, a phase synchronization circuit consisting of a flip-flop circuit and a logic circuit makes the sampling clock have a phase difference within a certain range with respect to the video input signal.

[Problem that the invention seeks to solve]

However, even with this video interface device,
Sampling is still incomplete due to the frequency difference between the sampling clock and the dot clock pulse of the video signal transmitting device, the waveform disturbance of the video input signal, and the like. As a result, printers connected to this video interface device also have problems in that dot misalignment, color misalignment, etc. occur in printing.

The present invention has been made in order to eliminate the above-mentioned problems, and it is an object of the present invention to realize a video interface device that can re-sample a video input signal that has been sampled in error and perform sampling more completely. purpose.

[Means for solving problems]

The present invention provides a video interface device that samples a video input signal sent from a video signal transmission device using a sampling clock and outputs the sample as a video output signal. A pseudo synchronous clock generation circuit that generates a phase difference within a range, a memory in which a sampled video input signal is stored, a video input signal and a video output signal are input, and a delay signal of the video input signal is input at the rising and falling edges. An error detection circuit that checks sampling errors for each raster of data based on the state of the video output signal at the time, and an error detection circuit that checks the raster address of each raster until the sampling error is checked. is set in the raster counter, and the raster address set in the raster counter when an error is detected by the error detection circuit, the data sampled in error is processed in the next and subsequent frame cycles. A video interface device characterized by comprising a control circuit for resampling.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a video interface device according to the present invention.

In FIG. 1, 10 is a clock oscillator, 20 is a pseudo synchronous clock generation circuit, 30 is a sampling circuit, 40 is a memory, 50 is a buffer, 60 is an address counter, 70 is a write/read control circuit,
80 is a raster counter circuit, 90 is an error detection circuit, 100 is an error signal sending circuit, and 110 is a control circuit.

VSYNC, HSYNC, and VIDEO IN are a vertical synchronization signal, a horizontal synchronization signal, and a video input signal, which are provided from a video signal transmission device.

The clock oscillator 10 is a sampling clock.
Output CLKI.

The pseudo synchronous clock generation circuit 20 converts the sampling clock CLK1 into the video input signal VIDEO IN.
(hereinafter simply referred to as VIDEO IN), a clock signal CLK2 with a phase difference within a certain range is output.

The sampling circuit 30 samples VIDEO IN in accordance with the clock signal CLK2, and outputs it as a video output signal VIDEO OUT (hereinafter simply referred to as VIDEO OUT).

The sampled data is stored in the memory 40.

Buffer 50 regulates the flow of data written to memory 40 and the flow of data read from memory 40.

The address counter 60 is set with an address for reading and writing to the memory 40.

The write/read control circuit 70 receives a horizontal synchronization signal
Based on HSYNC, clock signal CLK2, write request signal (hereinafter referred to as WR signal) from raster counter 80, and write clock signal (hereinafter referred to as RDCLK signal) from control circuit 110,
Sends a signal to the address counter 80 and sends a signal to the memory 40.
control writing and reading.

The raster counter circuit 80 includes a control circuit 110.
The raster address is set by The raster counter circuit 80 also receives a vertical synchronization signal.
Based on VSYNC, the horizontal synchronization signal HSYNC, and a write signal (hereinafter referred to as WRITE signal), a WR signal is sent to the write/read control circuit 70, and a write enable signal (hereinafter referred to as WE signal) is sent to the memory 40. , a write end signal (hereinafter referred to as a WREND signal) is sent to the control circuit 110, respectively.
Here, the raster address corresponds to the number of scanning lines on the screen of the video signal sending device.

The error detection circuit 90 connects VIDEO IN and VIDEO
OUT is input, and sampling errors are checked based on these signals.

In the error signal detection circuit 100, 101 is an AND gate, and 102 is a D type flip-flop. The AND gate 101 receives the output of the error detection circuit 101 and the WE signal. In the flip-flop 102, a voltage at a predetermined level is applied to the D terminal, the output of the AND gate 101 is applied to the CK terminal, and the WRITE signal is applied to the CLK terminal. When a sampling error occurs, the error signal (hereinafter simply referred to as the ERROR signal) generated from the Q terminal of the flip-flop 102 becomes _true (High Level). this
When the ERROR signal is sent to control circuit 110, control circuit 110 prevents the erroneously sampled data from being read from memory 40.

The control circuit 110 includes a CPU, memory and I/O
Consists of ports.

For example, a printer is connected to the I/O port.

When an error is detected by the error detection circuit 90, the CPU reads the raster address of the erroneously sampled video input signal and samples the video input signal again in the next and subsequent frame periods. For each raster video input signal, the raster address of that video input signal is set in the raster counter circuit 80 until the error detection circuit checks for errors. Therefore, when an error is detected by the error detection circuit 90, the video input signal to be sampled again is determined based on the raster address set in the raster counter circuit 80.

If a sampling error is detected, the control circuit 110 resets the flip-flop 102 by setting the WRITE signal to a low level for a short period of time before performing the next sampling.

FIG. 2 is a diagram showing the main part configuration of FIG. 1.
Components in FIG. 2 that are the same as those in FIG. 1 are given the same reference numerals. The same applies to the following figures.

In the pseudo synchronous clock generation circuit 20, 21
2 is a flip-flop circuit, and 22 is a logic circuit.

The flip-flop circuit 21 is a D-type flip-flop circuit, and the sampling clock CLK1 from the clock oscillator 10 is applied to the D terminal, and the horizontal synchronizing signal HSYNC is applied to the T terminal.

The logic circuit 22 is an exclusive OR gate,
The exclusive OR of the sampling clock CLK1 and the output of the Q terminal of the flip-flop circuit 21 is calculated and output. Output CLK2 of exclusive OR gate 22
is applied to sampling circuit 30 and write/read control circuit 70.

The sampling circuit 30 is a D-type flip-flop circuit, and the D terminal has VIDEO IN,
The clock signal CLK2 from the pseudo synchronous clock generation circuit 20 is given to the T terminal, and the clock signal CLK2 from the Q terminal is given.
VIDEO OUT is output.

In the error detection circuit 90, 91 is a delay circuit that provides a delay time τ to VIDEO IN. Below, the signal given this delay time is
DELAYED VIDEO. 92 and 93 are D
This is a type of flip-flop circuit. The flip-flop circuit 92 has VIDEO OUT and
Signals from the delay circuit 91 are applied to the T terminals, and a signal _e1 is output from the terminals. The flip-flop circuit 93 has VIDEO on the D terminal.
Signals from the delay circuit 91 are applied to the OUT and T terminals, respectively, and a signal e ₂ is output from the Q terminal. 94 is an OR gate, which calculates the OR of signals e ₁ and e ₂ and outputs the result.

FIG. 3 is a diagram showing a specific configuration of the raster counter circuit 80 of FIG. 1.

In FIG. 3, 81 is a presettable raster counter, 82 is a first flip-flop circuit, 83 is a gate circuit, and 84 is a second flip-flop circuit.

A presettable raster counter (hereinafter simply referred to as raster counter) 81 is an up counter whose set value is variable. This raster counter 81
A raster address is set by the control circuit 110 from the terminals A to I. This raster address is loaded by applying the vertical synchronization signal VSYNC to the LD terminal of the raster counter 81. The raster counter 81 counts up each time the horizontal synchronizing signal HSYNC is applied to the CK terminal.

The first flip-flop circuit 82 is a D-type flip-flop, and the D terminal has a WRITE
signal is given, and the CK terminal receives a vertical synchronization signal.
VSYNC is applied and the WR signal is output.
The WR signal is applied to write/read control circuit 70 and gate circuit 90.

The gate circuit 83 is a NAND gate, and outputs the inverted logical product of the outputs Q _A to Q _I of the raster counter 81 and the WR signal. This output signal is the WE signal.

The second flip-flop circuit 84 is a D-type flip-flop, and a HIGH level voltage is applied to the D terminal, a WE signal is applied to the CK terminal, and a PR signal is applied to the CK terminal.
A WRITE signal is given to each terminal, and a WREND signal is output from the Q terminal. this
The WREND signal is applied to the I/Q port of control circuit 110.

The first flip-flop circuit 82, the gate circuit 83, and the second flip-flop circuit 84 constitute a write timing monitoring section.

Next, the operation of such a video interface device will be explained.

First, the operation of the pseudo synchronous clock generation circuit 20 will be explained.

4 and 5 are time charts for explaining the operation of the pseudo synchronous clock generating circuit 20. FIG.

In these time charts, Figure 4 shows that timing clock CLK1 is activated at the rising edge of the horizontal synchronization signal.
In the case of being in the HIGH state, FIG. 5 shows the case of being in the LOW state.

The frequency of the sampling clock CLK1 is the same as the frequency of the basic clock on the video signal transmission device side that generates the video signal, but since any oscillator actually has an error in frequency, the frequency of the basic clock does not completely match. In addition, the frequency of the horizontal synchronizing signal HSYNC is ideally a value of 1/n (n is an integer) of the frequency of the sampling clock CLK1, but in reality, for the above-mentioned reason, the frequency of the horizontal synchronizing signal HSYNC and the sampling clock CLK1 are The phases of are not completely matched.

In the case shown in Figure 4, the sampling clock starts at the rise time _t1 of the horizontal synchronization signal HSYNC.
The phase of CLK1 is reversed and the sampling clock
It becomes CLK2.

On the other hand, in the case shown in FIG. 5, sampling clocks CLK1 and CLK2 become in phase after time _t1 .

From time _t1 , sampling clock CLK2
If the time required to transition from the LOW state to the HIGH state is D, then the maximum value for this time D is
D _MAX and minimum value D _MIN are as follows in the cases shown in FIGS. 4 and 5.

In the case of Figure 4, the situation is as follows.

D _MIN = t _DH (MIN) + d (1) D _MAX = t _WH - t _DS (MIN) + d (2) Here, t _DH : Minimum data hold time of flip-flop circuit 21 t _DS : Minimum data of flip-flop circuit 21 Setup time _tWH : Time during which sampling clock CLK1 is in HIGH state d: Data propagation delay time of exclusive OR gate 22 On the other hand, in the case of FIG. 5, the following is true.

D _MIN = t _DH (MIN) + d (3) D _MAX = t _WL - t _DS (MIN) + d (4) Here, t _WL : Time that the sampling clock CLK2 is in the LOW state Now, as an ideal state, t _{If WH} = t _WL = t _c1/2 (t _c1 is the period of sampling clock CLK1), t _DS (MIN) = t _DH (MIN) = 0, then equations (1) and (3)
Equations (2) and (4) have the same value, and in both Figures 4 and 5, D _MIN = d (5) D _MAX = (t _c1/2 ) + d (6) Therefore, D _MAX − D _MIN =t _c1/2 (7) from equations (5) and (6). As shown in equation (7), the phase of the sampling clock CLK1 with respect to the originally random horizontal synchronization signal HSYNC can be made to have a phase difference within 180° by the pseudo synchronization clock generation circuit 20.

In reality, t _DH (MIN) and t _DS (MIN) are values greater than 0, but if a high-speed element such as a shot key TTL is used as a flip-flop circuit, it is possible to make them sufficiently smaller than the period t _c1 . can.
In addition, t _WH and t _WL are adjusted by adjusting the oscillation circuit so that t _WH ≒
t _WL is fully possible.

Figure 6 shows horizontal synchronization signal HSYNC and video signal
This is a time chart of the VIDEO.

As shown in Figure 6(a) and (b), the video signal
The start of the VIDEO display period is the horizontal synchronization signal
This occurs a certain period of time L after the rise of HSYNC. Here, the clock cycle on the video signal transmission device side is t _c2
Then, L=n t _c2 (n is an integer). This causes the sampling clock CLK2 to be
The phase difference with respect to VIDEO IN is also within a certain range.

Next, the operations of the sampling circuit 30 and the error detection circuit 90 will be explained.

FIGS. 7 and 8 are time charts for explaining the operations of the sampling circuit 30 and the error detection circuit 90.

input to flip-flop circuit 30
When the phases of VIDEO IN and the rising edge of sampling clock CLK are not within the range E as shown in Figure 7, VIDEO IN is transmitted correctly;
As shown in FIG. 8, if it is within the range of E, it will not be transmitted correctly. Here, the range of E is the data setup time t _DS of the flip-flop circuit 30
and the data hold time _tDH .

The correctness or failure of signal transmission is detected as follows.

Assuming that the times during which VIDEO IN is in the HIGH state and the LOW state are t _WH and t _WL , the delay time τ of the delay circuit 91 is shorter than t _WH - t _DS .

Here, the data propagation delay time of flip-flop circuit 30 and the data set-up time and data hold time of flip-flop circuits 92 and 93 are ignored.

The flip-flop circuit 92 connects the VIDEO OUT
is transmitted to the terminal at the rising edge of DELAYED VIDEO. Moreover, the flip-flop circuit 93 is
Transmit VIDEO OUT to terminal Q at the falling edge of DELAYED VIDEO. That is, the flip-flop circuit 92 outputs a LOW signal from the terminal if VIDEO OUT is in the HIGH state when the rising edge of DELAYED VIDEO is input, and the flip-flop circuit 93 outputs a LOW signal from the terminal when the rising edge of DELAYED VIDEO is input.
VIDEO OUT is input when the falling edge of
When in the LOW state, a LOW level signal is output from the Q terminal.

As shown in the time chart in Figure 7,
If VIDEO IN is transmitted correctly,
VIDEO OUT at the start of DELAYED VIDEO
is in HIGH state and DELAYED VIDEO
VIDEO OUT is in the LOW state when the signal falls. As a result, the signals e ₁ and e ₂ remain in the LOW state, and the output of the OR gate 94 is at the LOW level, so no error is detected.

On the other hand, as shown in the time chart of Figure 8,
If VIDEO IN is not transmitted correctly, the signal shown by the broken line that should be transmitted is not transmitted, _so VIDEO
Since OUT is in the LOW state, the signal _e1 is in the HIGH state. As a result, the output signal of the OR gate 94 becomes HIGH.

Such error detection can be done using DELAYED
This is done at each change point (rise and fall) of the VIDEO.

In the time chart for explaining operation, the period of VIDEO IN is equal to t _WH + t _WL . Since t _WH =t _WL in a normal TTL level video signal, such a case is also explained in the present invention.

Next, the operation of the raster counter circuit 80 will be explained.

FIG. 9 is a flowchart illustrating the operation of the raster counter circuit 80.

A raster address is set in the raster counter 81 by a signal sent through the I/O port of the control circuit 110 from a side that uses data, such as a printer. Since this set value n uses an up counter as the raster counter 81, n=cl, where l is the designated line number and c is the overflow value of the raster counter 81. This raster address is loaded into the raster counter 81 by applying VSYNC to the raster counter 81.

Here, when a write instruction occurs, WRITE
The signal becomes HIGH level.

In this state, the raster counter 81 counts up every time HSYNC is sent from the rising edge of VSYNC (time t ₃ ). 1 HSYNC
The signal sent accordingly corresponds to data for one scanning line on the screen.

Eventually, when the HSYNC of the specified line reaches the raster counter, the raster counter 81 overflows (all Q _A to Q _I become HIGH level), and the WE signal output by the Nandogade 83 becomes
becomes LOW level. This time is time _t5 .
At this time, the address counter 60 counts and outputs dot addresses in the horizontal direction of the screen in response to a signal from the write/read control circuit 70, and thereby the data of the designated line is transferred to the sampling circuit 30.
The data is written to the memory 50 through the process.

When the scanning of the designated line is completed, the WE signal becomes HIGH level again, and writing to the memory 40 becomes impossible. This time is time _t5 . At the same time, the WREND signal output from the second flip-flop circuit 84 becomes LOW level.

The side that uses data is the I/O of the control circuit 110
Completion of writing to the memory 40 is detected by receiving a LOW level WREND signal through the port. Thereafter, the side using the data sets the WRITE signal to LOW level at an arbitrary time, sends out a read clock, and reads the contents of the memory 40 while sequentially specifying read addresses.

Note that VIDEO IN may be an R, G, B color video signal.

Next, the operation of the control circuit 110 will be explained.

FIG. 10 is a flowchart showing the operation procedure of the control circuit 110. This operation is performed by the control circuit 1
This is done based on the firmware in 10.

VIDEO IN is sampled for each raster (one scanning line on the screen of the video signal transmitting device) and written to the memory 40.

Once one scanning line worth of data has been written,
A sampling error is checked based on the signal from the error signal sending circuit 100. The determination as to whether or not there is a sampling error is X.

If there is no sampling error, that is, judgment
If is YES, data for the next scanning line is written.

If there is a sampling error, that is, judgment
If is NO, the error data is sampled again in the next and subsequent frame cycles (the next and subsequent cycles of the vertical synchronization signal VSYNC). Since the raster address of the erroneous data is still set in the raster counter 81 at the time when judgment

When sampling is retried, the phase relationship between VIDEO IN and clock signal CLK2 is not the same as the previous time. Therefore, after sampling is attempted several times, data without sampling errors is written to the memory 40. This error-free data is read from memory 40 and printed out on a printer connected to the video interface device.

〔effect〕

According to the video interface device according to the present invention, the following effects can be obtained.

That is, when a sampling error occurs, a signal indicating that there is an error is sent to the control circuit 110. At this time, the control circuit 110 samples the erroneously sampled data again in the next and subsequent frame cycles based on the raster address set in the raster counter. This allows more complete sampling and improves the reproducibility of the screen of the video signal sending device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment of the video interface device according to the present invention, FIGS. 2 and 3 are diagrams showing the specific configuration of the device shown in FIG. 1, and FIG.
1 to 10 are explanatory views of the operation of the apparatus shown in FIG. 1. DESCRIPTION OF SYMBOLS 10... Clock oscillator, 20... Pseudo synchronous clock generation circuit, 30... Sampling circuit, 40... Memory, 80... Raster counter circuit, 81... Raster counter, 90... Error detection circuit, 100... Error signal sending circuit, 110... Control circuit .

Claims (1)

[Claims] 1. In a video interface device that samples a video input signal sent from a video signal sending device using a sampling clock and outputs the sample as a video output signal, the sampling clock is used as the video input signal. A pseudo synchronous clock generation circuit which maintains a phase difference within a certain range, a memory in which a sampled video input signal is stored, and a video input signal and a video output signal are input,
An error detection circuit that checks sampling errors for each raster of data based on the state of the video output signal at the rise and fall of the delayed signal of the video input signal; Until an error is checked, an error is detected based on the raster counter in which the raster address of the data is set, and the raster address set in the raster counter when an error is detected by the error detection circuit. A video interface device comprising: a control circuit that samples the sampled data again in the next and subsequent frame cycles.