JPH0379798B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to MOS (metal-insulator-semiconductor)-RAM
(Random Access Memory) device.

Conventionally, static type and dynamic type MOS-RAM devices have been known.

A static MOS-RAM is unsuitable for increasing storage capacity because it has a large number of elements constituting a memory cell. On the other hand, dynamic MOS-RAM is
Since the number of elements constituting the memory cell is small, it is possible to increase the storage capacity, but since the stored information is stored in the capacitor in the form of charge, it decreases over time due to leakage current and the like. Therefore, in order to always store accurate information in memory cells, read the information before it is lost.
There is a drawback that it is difficult to handle, as it is necessary to amplify this and write it into the same memory cell again, a so-called refresh operation.

The purpose of this invention is to
A new MOS-RAM that is as easy to handle as RAM
The goal is to provide equipment.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of one embodiment of the invention.

In the figure, each circuit block surrounded by dotted lines is manufactured using known semiconductor integrated circuit manufacturing technology.
Formed on one semiconductor substrate such as silicon, for example, terminals D0 to D7, A0 to A1
4, , , and Vcc, Vss are external terminals, and power is supplied to the terminals Vcc, Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array in which well-known 1MOS type memory cells composed of a storage capacitor and an address selection MOSFET (insulated gate field effect transistor) are arranged in a matrix. ing. In this embodiment, although not particularly limited, the memory cells are arranged in a two-intersection manner in which their input/output nodes are coupled to a pair of complementary data lines D arranged in parallel.

The circuit symbol PC1 is a data line precharge circuit, which receives a precharge pulse φ _PCW and shorts the complementary data line D.
It consists of a MOSFET that precharges to Vcc/2.

The circuit symbol SA indicates a sense amplifier, which is connected to the power supply voltage Vcc and the circuit ground potential Vss by a power switch, although this is not particularly limited.
It is composed of a CMOS (complementary MOS) latch circuit provided with a MOSFET, and its pair of input/output nodes are coupled to the complementary data line D.
Timing pulses φpa1, pa1 and φpa2,
pa2 is for controlling the power switch MOSFET. Power switch MOSFET
is turned off immediately before precharging, and the complementary data lines D maintain the Vcc and Vss levels in a floating state. And the above precharge
By turning on the MOSFET, the complementary data line D,
is precharged.

Note that the timing signals φpa1 and pa1 are mutually complementary signals, and the timing signals φpa
2, and pa2 are also mutually complementary signals.

A column switch, designated by the circuit symbol C-SW, couples a selected complementary data line to a common complementary data line in accordance with a column selection signal.

The circuit symbol R-ADB is a row address buffer, which receives external address signals from external terminals A0-A8 and forms internal complementary address signals a0-a8.

The circuit symbol C-ADB is a column address buffer, which connects external terminals A9 to A1.
4 to form internal complementary address signals a9 to a14.

The circuit symbol R-DCR is a row address decoder, which receives internal complementary address signals a0 to a via a multiplexer MPX, which will be described later.
8 and forms the M-ARY word line selection signal. This word line selection signal is transmitted to M-ARY in synchronization with the word line selection timing signal φx.

A column address decoder is designated by the circuit symbol C-DCR, and receives internal complementary address signals a9 to a14 to form an M-ARY data line selection signal. This data line selection signal is
It is transmitted to column switch C-SW in synchronization with data line selection timing signal φy.

The circuit symbol PC2 is a precharge circuit for the common complementary data line, and includes, but is not limited to, a MOSFET similar to the above that shorts the common complementary data line in response to the precharge pulse φpcd.
It is made up of.

The circuit symbol MA indicates the main amplifier, which has the same circuit configuration as the sense amplifier SA described above. Timing pulse φma1, ma1
and φma2, ma2 are the power switches
It is for controlling MOSFET.

Note that the timing signals φma1 and ma1 are mutually complementary signals, and the timing signals φma2 and ma2 are also mutually complementary signals.

The circuit symbol DOB is the data output buffer, and the read timing pulse φ
rw sends read data from the main amplifier MA to external terminals D0 to D7, respectively.
Note that during writing, this DOB is made inactive (output high impedance) by the read timing pulse φrw.

The circuit symbol DIB is a data input buffer, which transmits write data from external terminals D0 to D7 to a common complementary data line in response to a write timing pulse φrw. Note that when reading, this DIB is set by the write timing pulse φrw.
is disabled.

The various timing signals mentioned above are formed by the following circuit blocks.

The circuit symbol REG indicates address signals a0 to a8 (or 0
8) and detects the rising or falling edge of the signal.

Although not particularly limited, the circuit symbol CEG is an edge trigger circuit that receives address signals a9 to a14 (or 9 to 14) and detects their rising or falling edges.

These edge trigger circuits REG and CEG include, but are not particularly limited to, an exclusive OR circuit that receives address signals a0 to a8, address signals a9 to a14, and their delayed signals, respectively, and an OR circuit that receives their output signals. Any of address signals a0 to a8, address signals a9 to
Edge detection pulses φr and φc are respectively formed in synchronization with the change timing of a14.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as a representative above. In addition to the edge detection pulses φr and φc, this timing generation circuit also uses a write enable signal supplied from an external terminal.
The series of timing pulses is formed in response to the chip select signal.

The circuit symbol MPX is a multiplexer, which is an automatic refresh circuit described later.
According to the control signal φref from REF, the internal complementary address signals a0 to a8 formed by the address buffer R-ADB and the internal complementary address signal a0 formed by the automatic refresh circuit REF are
~ a8 are selectively transmitted to the decoder R-DCR.

The circuit symbol Vbb-G indicates a substrate bias voltage generation circuit.

The circuit symbol REF is an automatic refresh circuit, which includes a refresh address counter, a timer, etc., and is activated by setting a refresh signal from an external terminal to a low level.

That is, when the refresh signal is set to low level while the chip selection signal is high level, the automatic refresh circuit REF switches the multiplexer MPX by the control signal φref,
An internal address signal from a built-in refresh address counter is transmitted to the row decoder R-DCR to perform a refresh operation (auto refresh) by selecting one word line. Further, when the refresh signal is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this time.

FIG. 2 shows a circuit diagram of a specific embodiment of the main circuits shown in FIG. 1 above. In the following explanation, unless otherwise specified, MOSFET
is an n-channel MOSFET.

In the memory array M-ARY, a pair of rows are shown as a representative, and a switch MOSFET Q15 is connected to a pair of complementary data lines D arranged in parallel.
The input/output nodes of each of the plurality of memory cells constituted by Q18 and MOS capacitors are distributed and coupled with a predetermined regularity as shown in the figure.

The precharge circuit PC1, like MOSFETQ14 shown as a representative, has complementary data lines D,
It is composed of a switch MOSFETQ14 provided between the two.

The sense amplifier SA consists of the representative p-channel MOSFETs Q7 and Q9 and the n-channel MOSFETs.
CMOS (complementary type) consisting of MOSFETQ6 and Q8
(MOS) latch circuit, and its pair of input/output nodes are coupled to the complementary data line D. In addition, the above latch circuit may include, but is not limited to, a parallel p-channel MOSFETQ12,
Power supply voltage Vcc is supplied through Q13, and circuit ground voltage Vss is supplied through parallel n-channel MOSFETs Q10 and Q11. These power switch MOSFETQ10, Q11 and MOSFETQ12,
Q13 is a sense amplifier provided in other similar rows
Commonly used for SA.

Complementary timing pulses φpa1, pa1 that activate the sense amplifier SA are applied to the gates of MOSFETQ10, Q12, and MOSFETQ11,
The above timing pulse φpa is applied to the gate of Q13.
Complementary timing pulses φpa2, pa2 delayed from φpa1, pa1 are applied. The reason for this is that the minute read voltage from the memory cell causes the sense amplifier to
When operating the SA, the drop in the level of the data line is caused by a relatively small conductance.
This can be prevented by limiting the current using MOSFETQ10 and Q12.

Then, after increasing the difference in complementary data line potential by the amplification operation in the SA, MOSFETs Q11 and Q13 with relatively large conductance are turned on to speed up the amplification operation. By performing the amplification operation of the sense amplifier SA in two stages in this way, high-speed reading can be performed while preventing the complementary data line from falling on the high level side.

One circuit of the row decoder R-DCR (four word lines) is shown as a representative, and for example, an n channel that receives address signals a2 to a6.
MOSFETQ32~Q36 and p channel
The word line selection signals for the four lines mentioned above are formed by a NAND circuit using a CMOS circuit composed of MOSFETs Q37 to Q41.

The output of this NAND circuit is a CMOS inverter.
It is inverted by IVI and transmitted to the gates of MOSFETs Q24 to Q27 through cut MOSFETs Q28 to Q31.

Furthermore, four word line selection timing signals φx00 to φx11 formed by a combination of the decode signal formed by the address signals a0 and a1 and the timing pulse φx are applied to the MOSFETs Q24 to φx11.
It is transmitted to each word line via Q27.

Also, between each word line and the ground potential,
MOSFETs Q20 to Q23 are provided, and by applying the output of the NAND circuit to their gates, the word line is fixed at the ground potential when not selected.

The above word line has MOSFETQ1 for reset.
MOSFETs Q1 to Q4 are provided, and when these MOSFETs Q1 to Q4 are turned on in response to a reset pulse φpw, the selected word line is reset to the ground level.

The column switch C-SW selectively couples the complementary data line D and the common complementary data line CD, like the MOSFETs Q42 and Q43 shown as representatives.

The gates of these MOSFETs Q42 and Q43 are
A selection signal from column decoder C-DCR is supplied.

A precharge MOSFET Q44 constituting a precharge circuit PC2 similar to the above is provided between the common complementary data lines CD.

This common complementary data line CD is connected to a main amplifier with a circuit configuration similar to that of the sense amplifier SA mentioned above.
A pair of MA input/output nodes are connected.

Although the block diagram of FIG. 1 shows a x8 bit configuration, this embodiment shows a memory array with a x1 bit configuration. That is, in FIG. 1, input/output is performed in units of 8 bits, but in the embodiment shown in FIG. 2, input/output is performed in units of 1 bit. In order to obtain the above-mentioned x8-bit configuration, it is necessary to prepare 8 sets of the above-mentioned memory arrays, or to form 8 pairs of common complementary data lines CD, so that the output of one column decoder C-DCR can be used to generate 8 pairs of data lines. The complementary data line D may be coupled to the corresponding common complementary data line CD. In this case, it goes without saying that eight sets of the main amplifier MA, input buffer DIB, and output buffer DOB are prepared.

The edge trigger circuit REG includes, but is not particularly limited to, exclusive OR circuits EX0 to EX8, delay circuits DL0 to DL8, and
It consists of a NOR gate circuit G1 and an inverter IV4.

That is, the address signals a0 to a8 are respectively applied to one input of the exclusive OR circuits EX0 to EX8. In addition, the above address signals a0 to a
8 are applied to the other inputs of exclusive OR circuits EX0 to EX8 through delay circuits DL0 to DL8, respectively.

And these exclusive OR circuits EX0~EX
The output of 8 is input to the NOR gate circuit G1,
The change detection timing signal φr of the address signal is passed through the inverter IV4.

When the address signal ai changes, different potentials are applied to both input terminals of the exclusive OR circuit EXi for a time corresponding to the delay time of the delay circuit. For this reason, the edge trigger circuit
When any one of the address signals a0 to a8 changes, REG outputs, for example, a high-level edge detection pulse φr.

Further, the edge trigger circuit CEG has the same circuit configuration as the edge trigger circuit REG. Therefore, when any one of the address signals a9 to a14 changes, the edge trigger circuit CEG outputs, for example, a high level edge detection pulse φc.
Output.

The above automatic refresh circuit REF includes, but is not particularly limited to, an address counter CONT that forms a refresh address signal, and a timer circuit TM.
It consists of

This timer circuit TM is activated by setting a refresh control signal from an external terminal to a low level. That is, the chip selection signal
Refresh control signal when CS is high level
When RESH is brought low, the multiplexer
The switching signal φref of MPX is output, the multiplexer MPX is switched to the address counter CONT side, and the internal address signals a0 to a8 formed by this address counter CONT are transmitted to the address decoder R-DCR and converted into one signal. Performs refresh operation (auto refresh) by word line selection operation.

Since the address counter CONT is incremented each time the refresh control signal is input, all memory cells can be refreshed by repeating the above operation for the number of word lines.

Further, if the refresh control signal is kept at a low level, the timer circuit is activated and generates a pulse at regular intervals, so that the address counter CONT is incremented and a continuous refresh operation is performed during this time.

FIG. 3 shows a circuit diagram of an embodiment of the multiplexer MPX.

In this example, although not particularly limited,
Two 3-state output circuits made up of CMOS circuits and one CMOS inverter IV3 are used. One three-state output circuit is composed of p-channel MOSFETs Q86, Q87 and n-channel MOSFETs Q88, Q89, which are connected in series.

The gates of MOSFETQ86 and Q89 above are input terminals
IN1 (R-ADB) and the above MOSFETQ87
The gate of Q88 has the above automatic refresh circuit.
A switching signal φref formed by REF and a signal ref inverted by inverter IV3 are applied.

Other 3-state output circuits are similar to the above.
Consists of MOSFETQ90 or Q93. and,
The gates of MOSFETQ90 and Q93 above are input terminals IN
2 (CONT) and the above MOSFETQ91 and Q92
Contrary to the above case, there is a switching signal on the gate of
ref and φref are applied.

Now, if the switching signal φref is at a low level and ref is at a high level, MOSFETs Q87 and Q88 are turned on and transmit the address signal from the input terminal IN1 (R-ADB) to the output terminal OUT (R-DCR).

In addition, when the switching signal φref is at high level, ref
When is at low level, MOSFETs Q91 and Q92 are turned on and transmit the address signal from the input terminal IN2 (CONT) to the output terminal CUT (R-DCR).

In addition, in the multiplexer MPX of this example,
An output is formed that is inverted with respect to the input. Therefore, for example, the output of the multiplexer MPX should be transmitted to the row decoder R-DCR via an inverter, or the relationship between the outputs of the row address buffer R-ADB and address counter CONT and the input of the row decoder R-DCR should be adjusted appropriately. Set.
That is, for example, as shown in FIG.
Configures one circuit of row decoder R-DCR
In order to supply address signals a2 to a6 to the NAND circuit, a multiplexer corresponding to the output terminals that output these address signals is required.
The input terminal of MPX has an address buffer R-
Address signals 2 to 6 from ADB (also address signals 2 to 6 from address counter CONT)
Make sure that it is supplied.

FIG. 4 shows a timing diagram of the auto-refresh operation.

Note that in the figure, the timing signals pa1 and pa2 are omitted to make the drawing easier to read.

When the refresh control signal is set to low level (the chip selection signal is set to high level), the switching signal φref becomes high level, the edge trigger circuit REG detects a change in the address signal ai from the address counter CONT, and the edge detection pulse is detected by the edge trigger circuit REG. φr is transmitted to the timing generation circuit TG. This timing generation circuit TG generates timing pulses φpa1, φpa1,
φpa2 to low level (timing pulse pa1,
φpa2 is set to high level), the power switch MOSFET of the sense amplifier SA is turned off, and the complementary data lines D are held in a floating state at the Vcc and Vss levels according to the previous operation.

In addition, by setting the precharge pulse φpcw to high level and turning on the precharge MOSFET, the complementary data line D is short-circuited to Vcc/2.
Precharge to.

After waiting the time required for this precharge, the precharge pulse φpcw is set to a low level.

Then, the word line selection timing signal φx is set to high level. This allows multiplexer
One word line determined by address signals a0 - a8 from MPX is selected. Therefore, a plurality of memory cells coupled to the selected word line are selected, and the MOS capacitance of each memory cell is connected to the data line D (or) via the switch MOSFET.
is combined with That is, each complementary data line D,
An input/output node of one memory cell is coupled to one data line D (or). Therefore, a read level appears on the data line D due to charge dispersion between the accumulated charge in the memory cell and the precharge charge on the data line D. The figure shows a case where the information stored in the memory cell is at a low level.

Note that the other data line remains at the precharge level as no memory cell is coupled thereto.

Next, after waiting for the time required for the reading, the timing pulses φpa1 and φpa2 are set to high level to operate the sense amplifier SA. This results in
The complementary data line D is amplified to low level and high level. Since this amplified signal is transmitted to the memory cell, a refresh operation can be performed.

Further, when the refresh control signal is set to a high level, predetermined timing signals such as the word line selection timing signal φx are reset.

In self-refresh operation, a signal corresponding to the above-mentioned refresh control signal is sent to the timer circuit.
This is done by generating it at regular intervals using TM.

In the write or read operation, the column switch C-SW is selected by the column switch selection timing signal φy, which is generated later than the word line selection timing signal φx, and the timing pulses φma1, ma1 and φma2, ma2,
Due to φrw, when reading, the main amplifier
MA and data output buffer DOB operate, and writing is performed by operating data input buffer DIB (not shown).

In the MOS-RAM device of this embodiment, the change timing of the address signal is detected to form all internal timing signals necessary for write, read, and refresh operations. Therefore, external timing control can be simplified, making it easy to handle like static RAM.

The memory cell is a dynamic type 1MOS
Since a type is used, a large memory capacity can be achieved.

Two operation modes are available for the refresh operation. For example, during write or read access, all refresh control signals are repeatedly set to low level for the number of word lines at approximately every 2 ms, and data retention or power outage is selected. At the time of (battery backup), it is sufficient to simply keep the refresh control signal at a low level, so that the refresh operation can be performed by a simple external control circuit.

Furthermore, the precharge operation of the memory array in this embodiment is achieved by simply shorting a pair of complementary data lines, a common complementary data line, to an intermediate level of about Vcc/2, which is similar to that of a conventional dynamic RAM. Compared to those that charge up from 0 volts to the Vcc level, the amount of level change is small, and the gate voltage of the precharge MOSFET can be turned on in a sufficiently unsaturated state even if the normal logic level Vcc is used. Operation can be performed at high speed and with low power consumption.

As mentioned above, since the precharge level is set to an intermediate level of approximately Vcc/2,
Even when reading a memory cell, it can be turned on in a fully unsaturated state even if the normal logic level Vcc is used as the gate voltage (word line selection voltage) of the switch MOSFET of the memory cell. The entire charge of the information storage capacitor can be read out without using a bootstrap voltage as shown in FIG.

In addition, since the read reference voltage uses the precharge level of the data line on which no memory cell is selected, it is different from conventional dynamic RAM.
A dummy cell that forms a read reference voltage is no longer necessary.

The invention is not limited to the above embodiments.

The configuration of the memory array is ×1 bit configuration or ×
Various modifications can be made depending on the N-bit configuration, etc.

Also, address buffer, address decoder,
The specific circuit configuration of peripheral circuits such as sense amplifiers is as follows.
It is possible to take various embodiments.

Further, the automatic refresh circuit may have any specific configuration as long as it has the above-mentioned functions.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of this invention, Fig. 2 is a circuit diagram showing a specific embodiment of its main circuits, and Fig. 3 shows an embodiment of its multiplexer. The circuit diagram, FIG. 4, is a timing diagram for explaining the auto-refresh operation. M-ARY...Memory array, PC1...Precharge circuit, SA...Sense amplifier, R-ADB...
...Row address buffer, C-SW...Column switch, C-ADB...Column address buffer,
R-DCR……Row address decoder, C-DCR
...Column address decoder, PC2...Precharge circuit, MA...Main amplifier, REG,
CEG...edge trigger circuit, TG...timing generation circuit, REF...automatic refresh circuit,
DOB...Data output buffer, DIB...Data input buffer, MPX...Multiplexer, Vbb
-G...Substrate bias circuit.

Claims (1)

[Claims] 1. An address buffer that receives an external address signal in accordance with a chip selection signal, an edge trigger circuit that detects the change timing of an internal address signal,
A timing generation circuit receives the output signal of this edge trigger circuit and generates a series of timing signals required for writing and reading dynamic memory cells, and an address signal generated internally based on an external refresh control signal. Therefore, the present invention includes an automatic refresh circuit that performs a self-refresh and/or auto-refresh operation of a dynamic memory cell, and a peripheral circuit for writing and reading the dynamic memory cell, which is configured with a CMOS circuit. Features
MOS-RAM device. 2. The MOS-RAM device according to claim 1, wherein the dynamic memory cell is comprised of an information storage capacitor and an address selection MOSFET. 3. Precharging of the complementary data line pair is performed by short-circuiting the complementary data line pair to which the input/output nodes of the dynamic memory cell are connected. The described MOS-RAM device.