JPH0812759B2 - Dynamic RAM - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (random access memory), for example, a type of precharging a data line by short-circuiting a pair of complementary data lines. It is related to a technology effectively used for a dynamic RAM.

[Background technology]

In a dynamic RAM using a 1MOS type memory cell composed of an address selection MOSFET (insulated gate type field effect transistor) and an information storage capacitor, a data line is precharged to a power supply voltage level and a pair of complementary Approximately 1/2 by simply shorting the data line
Has been proposed in which these complementary data lines are precharged to the power supply voltage level (for example, refer to Japanese Unexamined Patent Publication No. 57-82282 for the former. The latter has been previously proposed by the applicant of the present application. See Japanese Patent Application No. 57-164831.)

The latter half precharge method has the advantage that the data line precharge current can be reduced. However, the research by the inventor of the present application has revealed that the 1/2 precharge method has the following problems.

That is, as shown in the waveform diagram of FIG. 1, the precharge operation is performed at a high level H such as the power supply voltage Vcc on the pair of floating complementary data lines,
Utilizing the charge distribution operation caused by short-circuiting the low level L such as the ground potential Vss of the circuit, Vcc / 2
To get the precharge level of. Therefore,
Between the start of the precharge and the selection operation of the word line, the power supply voltage Vcc is the voltage Vcc 'as shown by the broken line in FIG.
When a so-called power supply bump is generated, the level of the word line selection signal φx is decreased by the power supply voltage Vc.
Only the level of c ′ rises. As a result, like the memory cell shown in FIG. 2, the precharge voltage Vcc / 2
Is supplied to the source, and the operating voltage (gate-source voltage) of the address signal selecting MOSFET Qm for supplying the selection signal φx of the word line W formed on the basis of the lowered power supply voltage Vcc ′ to the gate is small. Therefore, the reading out of the stored charges from the information storage capacitor Cs to the data line D becomes insufficient or impossible, resulting in a malfunction.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM with an improved operation margin for power supply bumps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
By short-circuiting a pair of complementary data lines, dividing the power supply voltage to form a power supply voltage of approximately 1/2, and supplying it to the complementary data lines, precharging according to fluctuations in the power supply voltage It is set to a level.

〔Example〕

FIG. 3 shows a circuit diagram of an embodiment of the semiconductor memory device according to the present invention. Although not particularly limited, each circuit element shown in the figure is formed on a semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. In the following description, the MOSFET (insulated gate field effect transistor) is an N-channel type unless otherwise specified.

A pair of rows of the memory array M-ARY is shown as a representative, and a pair of parallel complementary data lines D,
Address selection MOSFETs Q15 to Q18 and information storage
Input / output nodes of a plurality of memory cells each composed of a MOS capacitor are distributed and coupled with a predetermined regularity as shown in FIG. That is, taking one memory cell as an example, the address selection MOSFET Q1
One of the source and drain of 5 is connected to one data line D of the complementary data lines D. The other source and drain of the address selecting MOSFET Q15 are connected to the electrode on the diffusion layer side of the MOS capacitor that constitutes the information storage capacitor. The power supply voltage Vcc is applied to the gate side electrode of the MOS capacitor.

The precharge circuit PC1 is formed by a switch MOSFET Q14 that short-circuits the complementary data line D and the resistors R1 and R2 in series, like a circuit provided on the complementary data line D, which is shown as a representative. Pair of transmission gates for supplying the voltage of about Vcc / 2 to the pair of complementary data lines D,
It is composed of MOSFETs Q45 and Q46. Each MOSFET Q14, Q above
The precharge signal φpcw is commonly used for the gates of 45 and Q46.
Is supplied. Similar circuits are provided for other complementary data lines not shown. Although not particularly limited, in this embodiment, the divided voltage V formed by the resistors R1 and R2 is
cc / 2 is commonly supplied to other circuits. Also,
In order to reduce the current consumption, the resistance value of the resistors R1 and R2 is set to a high resistance value such that the combined resistance value is about 500 KΩ.

The sense amplifier SA is a p channel shown as a representative.
CM consisting of MOSFETs Q7 and Q9 and n-channel MOSFETs Q6 and Q8
It is composed of an OS latch circuit, and its pair of input / output nodes is coupled to the complementary data line D ,. Although not particularly limited, the latch circuit is supplied with the power supply voltage Vcc through P-channel MOSFETs Q12 and Q13 arranged in parallel and the ground voltage Vss of the circuit through N-channel MOSFETs Q10 and Q11 arranged in parallel. These power switches MOSFE
TQ10, Q11 and MOSFET Q12, Q13 are not particularly limited,
It is commonly used for the sense amplifiers SA provided in other similar rows.

Complementary timing signals φpa1 and pa1 for activating the sense amplifier SA are supplied to the gates of the MOSFETs Q10 and Q12, and complementary timing signals φpa2 and p1 delayed from the timing signals φpa1 and pa1 are supplied to the gates of the MOSFETs Q11 and Q13.
a2 is supplied. The reason for this is that when the sense amplifier SA is operated with a minute read voltage from the memory cell, the level drop of the data line is prevented by limiting the current with the MOSFETs Q10 and Q12 set to a relatively small conductance characteristic. Then, after increasing the potential difference between the complementary data lines by the amplification operation in the sense amplifier SA,
MOSFET Q1 set for relatively large conductance characteristics
1, Turn on Q13 to speed up its amplification operation. By thus performing the amplification operation of the sense amplifier SA in two stages, high-speed reading can be performed while preventing the complementary data line from falling on the high level side.

The row decoder R-DCR is composed of two row decoders R-DCR1 and R-DCR2. In the figure, the second
Row decoder R-DCR2 circuit (for 4 word lines)
Is shown as a representative, and for example, the address signal 2
-NAND by CMOS circuit composed of N-channel MOSFETs Q32-Q36 and P-channel MOSFETs Q37-Q41
The four word line selection signals are formed by the (nand) circuit. The output of the NAND circuit is inverted by the CMOS inverter IV1 and transmitted to the gates of the transmission gate MOSFETs Q24 to Q27 as the switch circuits through the cut MOSFETs Q28 to Q31.

The first row decoder R-DCR1 (not shown) is 2
The word line selection timing signals φx to 4 are passed through a switch circuit composed of a transmission gate MOSFET and a cut MOSFET similar to the above which are selected by a decode signal formed by bit complementary address signals a0,0 and a1,1 (not shown). Common word line selection timing signals φx00 to φx11
To form. These word line selection timing signals φx0
0 to φx11 is transmitted to each word line through the transmission gates MOSFETs Q24 to Q27. Row decoder R-DCR1
By dividing the row decoder into two, such as R and DCR2, the pitch (interval) of the row decoder R-DCR2 and the pitch of the word lines can be matched, so that no wasted space is generated on the semiconductor substrate. Circuit elements can be arranged.

In addition, MOSFET Q20 is connected between each word line and ground potential.
To Q23 are provided, and the output of the NAND circuit is applied to the gates thereof to fix the word line in the non-selected state to the ground potential. In addition, in the above word line,
Reset MOSFETs Q1 to Q4 are provided, and when the reset pulse φpw is received to turn on these MOSFETs Q1 to Q4, the selected word line is reset to the ground level.

The column switch C-SW is connected to the MO shown as a representative.
Like the SFETs Q42 and Q43, the complementary data line D and the common complementary data line CD, ▲ ▼ are selectively coupled. These MOS
A selection signal from the column decoder C-DCR is supplied to the gates of the FETs Q42 and Q43.

A precharge circuit PC2 constituted by a MOSFET Q44 for short-circuiting the common complementary data lines CD, ▲ is provided between the common complementary data lines CD, ▼. Since the signal amplified by the sense amplifier SA is transmitted to the common complementary data line CD, ▲ ▼, since the signal amplitude is large, a MOSFET or a voltage dividing circuit for power supply bumps such as the precharge circuit PC1. Is omitted.

A pair of input / output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier SA is coupled to the common complementary data line CD, ▲ ▼.

The output terminal of the main amplifier MA is connected to the input terminal of the data output buffer DOB. The data output buffer DOB receives the timing signal rw formed during the read operation and is put into an operating state, and outputs its output signal from the external terminal I / O. Further, the write signal supplied from the external terminal I / O is activated by receiving the timing signal φrw formed during the write operation, and forms a complementary write signal to the common data line CD, ▲ ▼. Tell.

The automatic refresh circuit REF is not particularly limited,
It includes an address counter for forming a refresh address signal and a timer circuit. This timer circuit has a refresh control signal ▲ ▼ from the external terminal.
It is activated by setting to low level. That is,
When the refresh control signal ▲ ▼ is set to the low level while the chip selection signal ▲ ▼ is at the high level, the switching signal φref of the multiplexer MPX is output and the multiplexer MPX is switched to the address counter side.
Complementary address signal a generated by this address counter
0 to a 8 (The address signal 0 of the inverse phase and the address signal a0 of phase with the address signal supplied from the outside
And are expressed as a complementary address signal a 0. This also applies to other complementary address signals. ) Is transmitted to the address decoder R-DCR to perform a refresh operation (auto refresh) by a single word line selection operation. This refresh control signal ▲ ▼
Since the step-up operation of the address counter is performed every time the input is made, all the memory cells can be refreshed by repeating the above operation for the number of word lines. Also,
When the refresh control signal ▲ ▼ is kept at the low level, the timer circuit operates to generate a pulse at constant time intervals, so that the address counter is stepped and the refresh operation is continuously performed during this period.

Next, the operation of this embodiment circuit will be briefly described. When the chip selection signal () becomes low level, an address buffer circuit (not shown) is activated and receives an address signal from an external terminal to form a complementary address signal.
Address signal supplied from this address buffer circuit
The address signal change detection circuit EG detects a change in ai and outputs the address signal change detection pulse φ to the timing generation circuit.
Tell TG. The timing generation circuit TG receives the timing signal φpa1, the timing signal φpa1, in response to the address signal change detection pulse φ.
Set φpa2 to low level (timing signals pa1 and pa2 are high level) and power switch MOSFET of sense amplifier SA
Is turned off, and the complementary data line D is held in the floating state at Vcc and Vss levels according to the previous operation.

Next, set the precharge signal φpcw to high level,
By turning on the precharge MOSFETs Q14, Q45, Q46, etc., the complementary data line D is short-circuited and precharged to Vcc / 2. At this time, in this embodiment, the MOSFET Q1
Depending on the ON state of 4, the precharge operation of Vcc / 2 by short-circuiting the complementary data line D, as described above, and Vcc / formed by dividing the power supply voltage Vcc at that time by resistors R1 and R2.
2 is supplied to the complementary data line D through the MOSFETs Q45 and Q46, respectively. Therefore, when the power supply voltage Vcc in the previous operation state is different from the power supply voltage Vcc in the precharge period, in other words, when a power supply bump occurs, the divided voltage causes the precharge of the complementary data line D, The charge level is corrected. The divided voltage formed by the voltage dividing resistor has a high output impedance, but since the voltage level to be corrected according to the power supply bump is small, the level can be corrected relatively quickly, and Its current consumption is minimized.

The precharge pulse φpcw is set to the low level after waiting the time required for the precharge. Then, the word line selection timing signal φx is set to the high level. Thus, one word line determined by the complementary address signal a 0 to a 8 supplied through a multiplexer MPX is selected. Therefore, a plurality of memory cells coupled to the selected word line are selected, and the information storage MOS capacitor of each memory cell is coupled to the data line D (or) via the address selection MOSFET. That is, the input / output node of one memory cell of each complementary data line D, is coupled to one data line D (or). Therefore, the read level appears on the data line D (or) due to the charge distribution of the accumulated charge of the memory cell and the precharge charge of the data line D. The other data line (or D)
Remains at the precharge level since the memory cells are not coupled.

Next, after waiting for the time required for the reading, the timing pulses φpa1 and φpa2 are set to high level, and the timing pulses pa1 and pa2 are set to low level to operate the sense amplifier SA. As a result, the complementary data line D, is amplified to low level and high level. Since this amplified signal is transmitted to the memory cell, the lost stored information is rewritten. At this time, the word line is boosted by the operation of a bootstrap circuit (not shown), although not particularly limited, so that the amplified high level is directly written in the information storage MOS capacitor without level loss.

The refresh operation is the same as the above operation except that the address signal is generated by the automatic refresh circuit REF, and therefore the description thereof is omitted.

Further, in the subsequent write or read operation, the column switch C-SW is selected by the column switch selection timing signal φy formed later than the word line selection timing signal φx, and the timing pulse φma1, ma1
And φma2, ma2, and φrw, the main amplifier MA and the data output buffer DOB operate at the time of reading, and the data input buffer DIB operates at the time of writing.

In the RAM of this embodiment, the change timing of the address signal is detected and all the internal timing signals necessary for the write, read and refresh operations are formed. Therefore, since the timing control from the outside can be simplified, it becomes as easy to handle as an internal synchronous static RAM. Since the memory cell uses a dynamic 1MOS memory cell, a large memory capacity can be realized.

〔effect〕

(1) In the pre-charge operation, by supplying a voltage of about 1/2 formed by dividing the power supply voltage to the complementary data line, 1 /
The precharge level set to the power supply voltage of 2 can be used. As a result, the consistency with the selection level of the word line can be ensured, and the reading of the memory cell can be stably performed. Therefore, the operation margin can be expanded with respect to the fluctuation of the power supply.

(2) By providing a MOSFET that short-circuits the complementary data line, the capacitance in the complementary data line is short-circuited to quickly form a precharge level according to the power supply voltage at the time of the previous operation. The corresponding relatively small level is corrected by a high resistance voltage dividing circuit that divides the power supply voltage. As a result, the effect that the complementary data line can be precharged at high speed and with low current consumption is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, a dynamic RA whose peripheral circuit is composed of a dynamic circuit and is supplied with an external address signal by being multiplexed with the address strobe signals ▲ ▼ and ▲ ▼.
The same applies to M when precharging Vcc / 2 in the same manner as above.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention is a dynamic RAM that uses a dynamic memory cell including an information storage capacitor and a MOSFET for selecting an address signal, and can be widely used for a Vcc / 2 precharge system.

[Brief description of drawings]

FIG. 1 is a waveform diagram for explaining an example of operation in a Vcc / 2 precharge system, FIG. 2 is a circuit diagram showing an embodiment of a memory cell, and FIG. 3 is a dynamic diagram according to the present invention. It is a circuit diagram which shows one Example of a type RAM. M-ARY …… Memory array, PC1 …… Precharge circuit,
SA: Sense amplifier, C-SW: Column switch, R-
DCR: Row address decoder, C-DCR: Column address decoder, PC2: Precharge circuit, MA: Main amplifier, EG: Address signal change detection circuit, TG: Timing generation circuit, REF: Automatic refresh Circuit, DOB
... Data output buffer, DIB ... Data input buffer, MPX ... Multiplexer

Claims (1)

[Claims] 1. A CMOS inverter circuit comprising a plurality of amplifying sections in which inputs and outputs are cross-connected to each other, and a relatively small power supply voltage and a circuit ground potential common to the plurality of amplifying sections. A first P-channel type MOSFET and a first N-channel type MOSFET having a current limiting action by a conductance characteristic and a first P-channel type MOSFET and a first P-channel type MOSFET having a relatively large conductance characteristic. Sense amplifier composed of a second P-channel MOSFET and a power switch MOSFET composed of a second N-channel MOSFET, which are turned on later than the N-channel MOSFET of FIG. A plurality of pairs of complementary data lines each having one end connected to an input / output node consisting of a pair and arranged in parallel, and orthogonal to the plurality of pairs of complementary data lines. A word line formed of a plurality consisting disposed so that, at the intersection between one of the data lines among the word lines and a pair of complementary data lines, a gate connected to a word line,
Address selection MOSFET having one source and drain connected to the data line, and such address selection MOSF
A dynamic memory cell including a capacitor for information storage, which is composed of a MOS capacitor in which an electrode on the diffusion layer side is connected to the other source and drain of ET and a power supply voltage is applied to the electrode on the gate side, and Switch provided for each complementary data line and short-circuiting the corresponding complementary data line pair.
A plurality of precharge circuits composed of a MOSFET and a pair of second switch MOSFETs for supplying a precharge voltage to the complementary data lines, and a plurality of precharge circuits obtained by dividing the power supply voltage by half. And a precharge circuit of the sense amplifier are arranged side by side on one end side of the complementary data line, and a P-channel MOSFET and an N-channel MOSFET of the amplification unit are provided. A pair of common source lines whose sources are commonly connected and a control signal line and a precharge voltage supply line to which the gates of the MOSFETs of the precharge circuit are commonly connected are extended to be parallel to the word lines. Dynamic RAM, which is characterized by being arranged as follows.