JPH0380378B2 - - Google Patents
Info
- Publication number
- JPH0380378B2 JPH0380378B2 JP60070314A JP7031485A JPH0380378B2 JP H0380378 B2 JPH0380378 B2 JP H0380378B2 JP 60070314 A JP60070314 A JP 60070314A JP 7031485 A JP7031485 A JP 7031485A JP H0380378 B2 JPH0380378 B2 JP H0380378B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- capacitor
- light emitting
- resistor
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Optical Communication System (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、光送信器の高速化に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to speeding up an optical transmitter.
第3図は例えば電子通信学会技術研究報告
QE82−96に示された従来の光送信器の回路構成
を示す図であり、図において1は信号入力端子、
2はFET、3はこのFETのバイアス用抵抗、4
はバイアス用電源端子、5はFETのソース端子、
6は半導体発光素子、7は半導体発光素子と
FETのドレイン間に接続された抵抗、8はこの
抵抗に並列接続されたコンデンサ、9は同軸短絡
反射線路である。第4図は、第3図の各部の信号
波形を示す図である。
Figure 3 is an example of the Institute of Electronics and Communication Engineers technical research report.
It is a diagram showing the circuit configuration of the conventional optical transmitter shown in QE82-96, in which 1 is a signal input terminal;
2 is FET, 3 is bias resistor for this FET, 4
is the bias power supply terminal, 5 is the FET source terminal,
6 is a semiconductor light emitting device; 7 is a semiconductor light emitting device;
A resistor is connected between the drains of the FET, 8 is a capacitor connected in parallel to this resistor, and 9 is a coaxial short-circuited reflection line. FIG. 4 is a diagram showing signal waveforms at each part in FIG. 3.
従来の光送信器は上記のように構成され、信号
入力端子1に第4図aに示すような2値信号が加
えられると、信号が“High”のときFET2は導
通し、信号が“Low”のときはFET2はしや断
となるので、FET2のドレイン電圧は第4図b
のようになる。また、FET2のドレインには同
軸短絡反射線路9が接続されていて、同軸短絡反
射線路9をパルスが往復する遅延時間を、伝送す
る信号波形のパルス幅と同じ時間に設定すれば、
FET2のドレイン電圧が“Low”から“High”
に変化するときに、第4図cに示す様にFET2
のドレイン電圧と逆極性のパルスがFET2のド
レインに加わる。したがつて、FET2のドレイ
ン電圧は第4図dのように変化することになる。
第4図dに示した電圧波形が抵抗7とコンデンサ
8で構成された微分回路を通して発光素子6に印
加される。したがつて、波形の変化点での駆動イ
ンピーダンスは小さくなり、定常状態では抵抗7
の値となる。その結果、発光素子6の駆動電流に
はピーキングがかかり、その波形は第4図eのよ
うになる。そのため、発光素子6の光出力波形の
立上り、立下り時間は速くなる。 The conventional optical transmitter is configured as described above, and when a binary signal as shown in FIG. ”, FET2 is suddenly disconnected, so the drain voltage of FET2 is as shown in Figure 4b.
become that way. In addition, a coaxial short-circuited reflection line 9 is connected to the drain of the FET 2, and if the delay time for the pulse to go back and forth on the coaxial shorted reflection line 9 is set to the same time as the pulse width of the signal waveform to be transmitted,
The drain voltage of FET2 changes from “Low” to “High”
As shown in Figure 4c, when FET2 changes to
A pulse of opposite polarity to the drain voltage of is applied to the drain of FET2. Therefore, the drain voltage of FET2 changes as shown in FIG. 4d.
The voltage waveform shown in FIG. 4d is applied to the light emitting element 6 through a differentiator circuit composed of a resistor 7 and a capacitor 8. Therefore, the drive impedance at the waveform change point becomes small, and in the steady state, the resistance 7
The value is . As a result, the driving current of the light emitting element 6 exhibits peaking, and its waveform becomes as shown in FIG. 4e. Therefore, the rise and fall times of the optical output waveform of the light emitting element 6 become faster.
以上の様に従来の光送信器は構成されていて、
同軸短絡反射線路9を用いて信号波形の立下り時
に逆バイアスパルスを印加することにより光出力
波形の立下り時間を速くしているので、伝送する
信号のパルス幅が変化すると同軸短絡反射線路9
の遅延時間を変化させなければならないという欠
点があつた。
The conventional optical transmitter is configured as described above.
By applying a reverse bias pulse at the falling edge of the signal waveform using the coaxial short-circuited reflection line 9, the fall time of the optical output waveform is made faster, so that when the pulse width of the transmitted signal changes, the coaxial short-circuited reflection line 9
The disadvantage was that the delay time of the delay time had to be changed.
この発明はこの様な欠点を解決するためになさ
れたもので、任意のパルス幅の信号で動作する高
速の光送信器を得ることを目的としている。 The present invention was made to solve these drawbacks, and aims to provide a high-speed optical transmitter that operates with signals of arbitrary pulse widths.
この発明による光送信器は、2個の電流切換ス
イツチを用い、それぞれの電流切換スイツチに接
続された半導体発光素子と抵抗間にコンデンサを
接続したものである。
The optical transmitter according to the present invention uses two current switching switches, and a capacitor is connected between a semiconductor light emitting element connected to each current switching switch and a resistor.
この発明においては、2個の電流切換スイツチ
間をコンデンサで結合しているため、任意のパル
ス幅の高速信号を駆動することができる。
In this invention, since the two current changeover switches are coupled by a capacitor, it is possible to drive a high-speed signal with an arbitrary pulse width.
第1図はこの発明の一実施例の回路構成を示す
図であり、1は信号入力端子、6は半導体発光素
子、10はゲート回路、11は第1の電流切換ス
イツチ、12,13は第1の電流切換スイツチを
構成するトランジスタ、14は第2の電流切換ス
イツチ、15,16は第2の電流切換スイツチを
構成するトランジスタ、17はコンデンサ、18
は抵抗、19,20は定電流源、21はバイアス
電圧印加端子である。第2図は第1図に示した回
路の各部の信号波形を示す図である。
FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, in which 1 is a signal input terminal, 6 is a semiconductor light emitting device, 10 is a gate circuit, 11 is a first current selection switch, and 12 and 13 are first and second current selector switches. 1 is a transistor constituting the current changeover switch, 14 is a second current changeover switch, 15 and 16 are transistors constituting the second current changeover switch, 17 is a capacitor, 18
is a resistor, 19 and 20 are constant current sources, and 21 is a bias voltage application terminal. FIG. 2 is a diagram showing signal waveforms at various parts of the circuit shown in FIG. 1.
上記のように構成された光送信器において、第
2図aに示したような2値信号が信号入力端子1
に印加されると、ゲート回路10を通して、第1
及び第2の電流切換スイツチ11,14に印加さ
れ、信号が“High”のときトランジスタ12,
14は導通しそれぞれ定電流源19及び20の電
流値の電流が流れトランジスタ13,16はしや
断となる。信号が“Low”のときトランジスタ
12,14はしや断となり、トランジスタ13,
16は導通となる。したがつて、トランジスタ1
2のコレクタ電圧は入力信号に対応して第2図b
の様になる。そこで、抵抗18の値を、半導体発
光素子6の内部抵抗より大きくしておけば、トラ
ンジスタ14のコレクタ電圧の変動分が第2図c
のようにコンデンサ17を通して半導体発光素子
6に印加される。したがつて、半導体発光素子6
を流れる電流は第2図dのように、その立上り及
び立下りにおいてピーキングがかかつた波形とな
り、その結果光出力波形の立上り、立下り時間は
速くなる。 In the optical transmitter configured as described above, a binary signal as shown in FIG. 2a is transmitted to the signal input terminal 1.
is applied to the first one through the gate circuit 10.
and the second current switching switches 11 and 14, and when the signal is "High", the transistors 12,
14 becomes conductive, and currents having the current values of constant current sources 19 and 20 flow, respectively, and transistors 13 and 16 are turned off. When the signal is "Low", transistors 12 and 14 are turned off, and transistors 13 and 14 are turned off.
16 is conductive. Therefore, transistor 1
The collector voltage of 2 corresponds to the input signal as shown in Fig. 2b.
It will look like this. Therefore, if the value of the resistor 18 is made larger than the internal resistance of the semiconductor light emitting element 6, the variation in the collector voltage of the transistor 14 can be reduced as shown in FIG.
The voltage is applied to the semiconductor light emitting device 6 through the capacitor 17 as shown in FIG. Therefore, the semiconductor light emitting device 6
As shown in FIG. 2d, the current flowing through the current has a waveform with peaking at its rise and fall, and as a result, the rise and fall times of the optical output waveform become faster.
この発明は以上説明したとおり、2個の電流切
換スイツチをコンデンサで結合することによりピ
ーキングをかけ、光出力波形の立上り、立下り時
間を速くしているため、任意のパルス幅の信号を
駆動できる効果がある。
As explained above, this invention applies peaking by coupling two current selection switches with a capacitor to speed up the rise and fall times of the optical output waveform, so it can drive signals with arbitrary pulse widths. effective.
第1図はこの発明の一実施例の回路構成を示す
図、第2図は第1図に示した回路構成の各部の信
号波形を示す図、第3図は従来の光送信器の回路
構成を示す図、第4図は第3図に示した回路構成
の各部の信号波形を示す図である。
図において、1は信号入力端子、2はFET、
3はバイアス用抵抗、4はバイアス用電源端子、
5はFETのソース端子、6は半導体発光素子、
7は抵抗、8はコンデンサ、9は同軸短絡反射線
路、10はゲート回路、11は第1の電流切換ス
イツチ、12,13はトランジスタ、14は第2
の電流切換スイツチ、15,16はトランジス
タ、17はコンデンサ、18は抵抗、19,20
は定電流源、21はバイアス電圧印加端子であ
る。なお、各図中同一符号は同一または相当部分
を示す。
Fig. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, Fig. 2 is a diagram showing signal waveforms of each part of the circuit configuration shown in Fig. 1, and Fig. 3 is the circuit configuration of a conventional optical transmitter. FIG. 4 is a diagram showing signal waveforms at various parts of the circuit configuration shown in FIG. 3. In the figure, 1 is a signal input terminal, 2 is a FET,
3 is a bias resistor, 4 is a bias power supply terminal,
5 is the source terminal of the FET, 6 is the semiconductor light emitting element,
7 is a resistor, 8 is a capacitor, 9 is a coaxial short-circuited reflection line, 10 is a gate circuit, 11 is a first current selection switch, 12 and 13 are transistors, and 14 is a second
current selection switch, 15 and 16 are transistors, 17 is a capacitor, 18 is a resistor, 19 and 20
is a constant current source, and 21 is a bias voltage application terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
換える第1及び第2の電流切換スイツチと、上記
第1及び第2の電流切換スイツチの端子間に接続
されたコンデンサと、上記コンデンサが接続され
た上記第2の電流切換スイツチの端子に接続され
た半導体発光素子と、上記コンデンサが接続され
た上記第1の電流切換スイツチの端子に接続され
た抵抗とを備えたことを特徴とする光送信器。1. The capacitor is connected to first and second current changeover switches that switch current paths in the same phase in response to binary data, and a capacitor connected between the terminals of the first and second current changeover switches. a semiconductor light emitting element connected to a terminal of the second current changeover switch, and a resistor connected to a terminal of the first current changeover switch connected to the capacitor. transmitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60070314A JPS61230438A (en) | 1985-04-03 | 1985-04-03 | Optical transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60070314A JPS61230438A (en) | 1985-04-03 | 1985-04-03 | Optical transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61230438A JPS61230438A (en) | 1986-10-14 |
| JPH0380378B2 true JPH0380378B2 (en) | 1991-12-24 |
Family
ID=13427866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60070314A Granted JPS61230438A (en) | 1985-04-03 | 1985-04-03 | Optical transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61230438A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0472318A3 (en) * | 1990-08-06 | 1994-08-10 | At & T Corp | Led pulse shaping circuit |
| EP1152532A3 (en) * | 2000-04-12 | 2003-10-29 | Infineon Technologies North America Corp. | Mos-gated photo-coupled relay having a reduced turn-on time |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5739593A (en) * | 1980-08-22 | 1982-03-04 | Nec Corp | Driving circuit of semiconductor light emitting element |
| JPS587941A (en) * | 1981-07-08 | 1983-01-17 | Nec Corp | High speed driving circuit for semiconductor light emitting element |
-
1985
- 1985-04-03 JP JP60070314A patent/JPS61230438A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61230438A (en) | 1986-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4859877A (en) | Bidirectional digital signal transmission system | |
| US3675144A (en) | Transmission gate and biasing circuits | |
| CA2077602A1 (en) | Low voltage swing output mos circuit for driving an ecl circuit | |
| JPS6451822A (en) | Buffer circuit and integrated circuit using the same | |
| KR900001026A (en) | Semiconductor circuits and signal processing systems using them | |
| US6380777B1 (en) | Output driver having controlled slew rate | |
| US5012128A (en) | High speed push-pull driver having current mirror pull-down | |
| US5134323A (en) | Three terminal noninverting transistor switch | |
| JPH0380378B2 (en) | ||
| JPH05335917A (en) | Transfer gate and dynamic frequency divider circuit using the same | |
| JP2853280B2 (en) | Output circuit | |
| US5324997A (en) | Delayed negative feedback circuit | |
| GB1288025A (en) | ||
| KR940023013A (en) | Integrated Circuit Signal Line Terminator | |
| JPH03172020A (en) | Semiconductor integrated circuit | |
| SU1091317A2 (en) | Flip-flop | |
| JP2871804B2 (en) | Waveform shaping circuit | |
| JPS622835Y2 (en) | ||
| JP2549707B2 (en) | Switch driver | |
| JPH0832421A (en) | Delay logic circuit element | |
| JPH04137910A (en) | Variable delay circuit | |
| JPS5918861Y2 (en) | Complementary FET chopper drive circuit | |
| SU1359901A1 (en) | Transistor switch | |
| JPH0193919A (en) | Level shifting circuit | |
| SU1277353A1 (en) | Method of reducing through currents in two-step amplifiers |