JPH038583B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a structure that improves the moisture resistance and ion resistance of a semiconductor device.

[Prior art]

Conventionally, the moisture resistance of semiconductor devices has been a problem, especially in plastic molded packages. Moisture inside the package or moisture entering from the outside through cracks in the package corrodes the metal layer of the semiconductor device, causing input/output terminals to deteriorate. This results in increased leakage current or inoperability. Ion resistance is
This is particularly a problem with non-volatile memories, such as FAMOS (Floating Gate Avalanche), which writes information by injecting electrons into the floating gate.
Non-volatile memory that stores electrons, such as non-volatile memory (such as injection MOS), has the effect of attracting alkali ions from within due to its electric charge, and the alkali ions are so attracted that they cancel out the electric field of the electrons stored in the memory transistor. The information “1” and “0” are reversed, causing a malfunction.

These defects in reliability characteristics are due to silicon dioxide (hereinafter referred to as SiO 2 ), which is a gate oxide commonly used in semiconductor devices, as well as silicon dioxide (hereinafter referred to as SiO ₂ ), which is a gate oxide commonly used in semiconductor devices. This is because the phosphosilicate glass membrane (hereinafter referred to as PSG membrane) provided under the body layer has the effect of adsorbing alkali ions.

Next, we will discuss the first conventional example to improve this drawback.
As shown in the figure. FIG. 1 is a sectional view of a chip end of a semiconductor device. 1 is a semiconductor substrate, 2 is an element part such as a transistor or diode formed on the semiconductor substrate 1, 3 is an SiO ₂ film for protecting the surface of the element part 2, and 4 is a
The PSG film (containing 5 to 15 mol% of phosphorus), 5, is a moisture-proof passivation film coated with glass or nitride.

In the conventional example shown in FIG. 1, the periphery of the semiconductor chip is covered with a passivation film 5 to prevent the SiO ₂ 3 and PSG film 4 from being directly exposed to the outside, so that alkali ions, impurities, etc. can enter from outside the side of the semiconductor chip. can be prevented.

However, the above techniques do not completely solve the problem of moisture resistance or ion resistance. In order to package a semiconductor chip into a semiconductor device, it is necessary to electrically connect the package lead legs and the internal circuit of the semiconductor chip.
is provided, and an electrode outlet (bonding pad) 7 is provided directly below it. A portion of the electrode outlet 7 may come off due to impact caused by contact with a needle during wafer testing or contact with a metal wire during package ring, and the PSG film 4 directly below may be exposed to the surface. Furthermore, the passivation film 5 around the electrode outlet 7 is likely to crack due to the impact described above. As a result, alkali ions, impurities, etc. tend to enter through cracks in the exposed PSG film or passivation film, resulting in a disadvantage in that reliability characteristics are significantly impaired.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to selectively or completely remove the PSG film and SiO ₂ film directly under or around the electrode outlet, and remove the PSG film of the internal circuit, The purpose is to provide a semiconductor device that can obtain high reliability characteristics by separating it from the SiO ₂ film and preventing alkali ions, impurities, etc. from being transmitted to the PSG film and SiO ₂ film of the internal circuit. It is said that

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIGS. 3 and 4, the same reference numerals as in the conventional example indicate the same or corresponding parts. FIG. 3 is a sectional view of the electrode outlet portion of this embodiment, and FIG. 4 is a plan view thereof. 8 is the same conductor layer (usually polycrystalline silicon) used for the gate of the transistor.

The structure of this embodiment is as follows:
As shown in Figure 3, remove the PSG film beyond the electrode outlet 7, and remove the PSG film 4 directly below the electrode outlet 7.
A and a PSG film 4b of the internal circuit are separated, and a passivation film 5 that does not allow moisture to pass through the separation part.
is formed. Since such a structure is used, a part of the electrode outlet 7 is removed and the PSG film 4a is exposed.
Even if alkali ions, impurities, etc. enter, they cannot proceed to the internal circuit. Furthermore, the distance of the PSG film 4b of the internal circuit from the passivation film hole 6 can be made longer than in the past, and even if a crack occurs in the passivation film 5, the intrusion of alkali ions, impurities, etc. into the PSG film 4b can be prevented. It can be reduced.

As described above, a semiconductor device with improved moisture resistance and ion resistance and excellent reliability characteristics can be obtained.

Note that the method for removing the PSG film is to use a normal MOS
It can be removed by plasma etching or the like using polycrystalline silicon used in semiconductor processes or a contact mask for connecting the diffusion layer and the metal layer. Since such a method is used, if the polycrystalline silicon 8 is not placed under the electrode outlet 7, the SiO ₂ film 3 will be etched and the electrode outlet 7 and the semiconductor substrate 1 will come into contact with each other, which is not preferable.

In addition, as in the other embodiments shown in FIG.
If the film 4b is made not to touch the edge of the polycrystalline silicon 8, part of the PSG film 4b and the SiO ₂ film 3 will be removed at the same time, and the passivation film 5 will be placed in the separated region, further improving moisture resistance and ion resistance. will improve.
Furthermore, if the PSG film directly below the electrode outlet 7 is removed as in still another embodiment shown in FIG.
It can also be expected that corrosion of the electrode outlet 7 can be prevented. This is because the PSG film 4a exists directly under the electrode outlet 7, and holes are generated in the electrode outlet 7, causing the PSG film 4
When a is exposed, the high concentration of phosphorus (5
This is because it has high hygroscopicity and may corrode the electrode outlet 7.

〔Effect of the invention〕

As described above, according to the present invention, since the PSG film under at least the end of the electrode outlet is removed, moisture resistance and ion resistance are improved, and since no additional process is required, the semiconductor device is inexpensive. This has the effect that a product with good reliability characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a chip end of a conventional semiconductor device, FIG. 2 is a cross-sectional view of an electrode outlet portion of a conventional semiconductor device, and FIG. 3 is a cross-sectional view of an electrode outlet portion of an embodiment of the present invention. 4 is a plan view of FIG. 3, FIG. 5 is a sectional view of the electrode outlet portion of another embodiment of the present invention, and FIG. 6 is a plan view of the electrode outlet portion of still another embodiment of the present invention. FIG. In the figure, 1 is a semiconductor substrate, 3 is a first insulating film (silicon oxide film), 4 is a second insulating film (phosphosilicate glass film), 5 is a third insulating film (passivation film), and 7 is an electrode. The outlet 8 is a conductive layer (polysilicon layer). Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate having a first insulating film on the surface and a semiconductor element formed therein, a semiconductor substrate having a first insulating film on a portion other than the region where the semiconductor element is formed. A second insulating film, a metal body layer, and a third insulating film are sequentially formed, and a part of the metal body layer electrically connected to a required location of the semiconductor element is not covered with the third insulating film. In a semiconductor device that is exposed to a portion of the first insulating film to form an electrode outlet, a conductive layer is buried in a portion of the first insulating film corresponding to the electrode outlet, reaching a peripheral position of the metal layer in the portion; The peripheral edge of the metal body layer is brought into contact with the conductive layer, and the entire portion of the second insulating film corresponding to the peripheral edge of the electrode outlet is removed, and the entire removed peripheral area is A semiconductor device characterized in that a third insulating film is inserted into the conductive layer so as to be in contact with the conductive layer. 2. All portions of the first and second insulating films corresponding to the peripheral edge portion of the electrode outlet were removed, and a third insulating film was inserted into the entire removed peripheral portion so as to be in contact with the semiconductor substrate. A semiconductor device according to claim 1, characterized in that: 3. The method according to claim 1 or 2, wherein the first insulating film is a silicon oxide film, the second insulating film is a phosphosilicate glass film, and the third insulating film is a glass film. Semiconductor equipment. 4. Claim 1 or 2, characterized in that the first insulating film is a silicon oxide film, the second insulating film is a phosphosilicate glass film, and the third insulating film is a silicon nitride film. semiconductor devices. 5. The semiconductor device according to any one of claims 1 to 4, wherein the conductor layer is a polysilicon layer.