JPH039625B2 - - Google Patents

Description

[Detailed Description of the Invention] Shallow PN as semiconductor device structures become finer
It is desired to create a bond with good control. PN junctions can be easily created using diffusion or ion implantation techniques, but controlling the junction depth requires measurement, which is currently more difficult to measure. The conventional method is
Mainly, the semiconductor substrate is polished diagonally, the scale in the depth direction is expanded, and the expanded PN junction cross section is measured for spreading resistance, and PN is etched by stain etching, etc.
The depth is determined by finding the junction and using the distance from the surface using a magnification factor. Another method is to perform etching from the surface at a known rate, such as electric field etching, and repeatedly measure the conductivity type of the surface to find a PN junction. All of the above methods involve destructive measurements and require a lot of man-hours. In general, the method of installing a MIS diode on the surface and measuring its capacitance is
The impurity concentration in the diffusion layers used for the source and drain of MOS transistors is too high and the depletion layer does not extend due to electrical breakdown, so it cannot be used to measure the PN junction depth.

An object of the present invention is to provide a method for non-destructively and electrically measuring the depth of a PN junction, while eliminating the drawbacks of the conventional methods described above.

In the present invention, the impurity concentration distribution is almost zero near the surface, and at a depth deeper than the measured junction depth, impurities of the opposite conductivity type to the surface-side impurities of the measured PN junction
It is constructed by measuring the capacitance of an MIS diode and a PN junction diode, which are provided on a semiconductor substrate with a stepwise high concentration.

The principle of the present invention is to measure the capacitance of the two diodes mentioned above, calculate the thickness of the depletion layer from the capacitance and the thickness of the insulating film for the MIS diode obtained by other means, and calculate the difference in thickness between the two diodes. The objective is to find the distance from the interface between the insulating film and the semiconductor to the position of the PN junction, that is, the depth of the PN junction.

A detailed explanation will be given below based on the figures. The figure schematically shows an example of measuring the depth of an n-type diffusion layer on a silicon substrate as an example of this measuring method. In the figure, 1 is a P-type substrate, 2 is a non-doped silicon layer formed by epitaxial growth, 3 is a gate oxide film, 4 is an N-type silicon gate electrode, 5, 6, and 7 are aluminum electrodes, and 8 is an N-type to be measured. diffusion layer, 9 is a gate terminal,
10 is a diffusion layer terminal, and 11 is a substrate terminal. In the case of the configuration shown in this figure, even if the potential difference between each terminal is zero, the region 2 is naturally depleted due to the difference in electron affinity between the substrate P-type silicon and the gate and diffusion layer N-type silicon. Now, the oxide film 3 under the silicon gate 4
The thickness of t _OX is the undoped silicon layer 2 below.
, that is, the distance from the interface between 3 and 2 to the interface between 1 and 2, is X ₁ , the thickness of the diffusion layer 8 is x _J , and the thickness of the non-doped silicon 2 under the diffusion layer 8, that is, 8 and Let x ₂ be the distance from the interface of 2 to the interface of 1 and 2. Also, the areas of the gate 4 and the diffusion layer 8 are respectively
Let them be S _G and S _D. The capacitance between electrodes 9 and 11 is C _G ,
If the capacitance between 10 and 11 is _CD , then C _G and C _D have the following relationship.

1/C _G =t _OX /E _OX S _G +x ₁ /E _Si S _G (1) 1/C _D =x ₂ /E _Si S _D (2) Here, E _OX and E _Si are the oxide film and silicon, respectively. is the dielectric constant of From this, it can be expressed as x ₁ =E _Si ·S _G (1/C _G −t _OX /E _OX S _G ) (3) x ₂ = E _Si S _D /C _D (4). t _OX can be measured by optical measurement using an ellipsometer, for example, or by applying a large positive bias to the gate of this MIS diode and connecting it to terminal 9, in a strongly inverted state.
It is determined from the capacity measured over 10 minutes. As is clear from the figure, once x ₁ and x ₂ are found, x _J can be found as x _J = x ₁ − x ₂ .

A device with the structure shown in the figure can be easily manufactured using a silicon gate process as follows. First, a silicon wafer with a P-type acceptor concentration of about 10 ¹⁹ /cm ³ is prepared. For example, if the junction depth to be measured is between 0 and 1 μm, a non-doped layer of about 1.2 to 1.5 μm is epitaxially grown on a silicon wafer. Next, an oxide film that will serve as a mask for later diffusion is grown using a vapor phase growth method. Next, the oxide film in the portions that will become the gate region and the diffusion layer region is selectively removed, and N-type polysilicon is grown in a vapor phase to selectively leave the portions that will become the gate region. Next, remove the oxide film in the area that should become the diffusion layer, form the diffusion layer using a process that measures the diffusion depth, and then open contact holes in the gate area and diffusion layer area using aluminum, for example. Form an electrode.

In this method, if silicon changes to an oxide film due to thermal oxidation etc. in the diffusion process, the distance x _J found by this measurement is the distance from the original surface to the PN junction, so it will decrease. The thickness of the grown silicon layer is determined from the thickness of the grown thermal oxide film, and this thickness is subtracted. A limitation of measurement in this method is that the heat treatment in the diffusion process is long, and the internal step-like impurity profile cannot be recognized as a step-like profile due to the diffusion of impurities. Therefore, this measurement method is more suitable for measuring shallow junctions than deep junctions, but since such areas are difficult to measure using conventional methods and are in particular areas where the need for measurement has increased recently, its benefits are limited. big.

As described above, according to the present invention, it is possible to easily and accurately determine the depth of a PN junction, especially a shallow PN junction, by simply and electrically measuring the depth of a PN junction, which conventional methods have poor accuracy, are destructive, and require a lot of man-hours. becomes possible.
Furthermore, the method of the present invention has the advantage that it can be applied not only to N-type layers in silicon but also to P-type layers and other semiconductor materials.

[Brief explanation of the drawing]

The figure is a schematic diagram of a cross-sectional structure of an example of a measurement device to which the present invention is applied, in which 1 is a P-type substrate, 2 is a non-doped layer, 3 is a gate oxide film, 4 is a gate electrode, 5,
6 and 7 are aluminum terminal electrodes, 8 is an N-type diffusion layer to be measured, 9 is a gate terminal, 10 is a diffusion layer terminal, 1
1 is a board terminal.

Claims (1)

[Claims] 1 The impurity concentration distribution is almost zero near the surface,
The MIS diode and the PN junction to be measured are located on the same surface of the semiconductor substrate, where the concentration is increased stepwise due to impurities of the opposite conductivity type to the impurities on the surface side of the PN junction to be measured at a depth deeper than the depth of the PN junction to be measured. 1. A method for measuring semiconductor characteristics, characterized in that the capacitance of a diode is measured, and the depth from the surface of a PN junction is determined from the MIS interface obtained from each capacitance value and the distance between the PN junction and the impurity step.