JPH0410100B2 - - Google Patents
Info
- Publication number
- JPH0410100B2 JPH0410100B2 JP57144116A JP14411682A JPH0410100B2 JP H0410100 B2 JPH0410100 B2 JP H0410100B2 JP 57144116 A JP57144116 A JP 57144116A JP 14411682 A JP14411682 A JP 14411682A JP H0410100 B2 JPH0410100 B2 JP H0410100B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- information
- instruction
- signal
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は情報処理装置に係り、業務実行時、論
理回路の診断を同時に実行していく診断装置に関
する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an information processing device, and more particularly, to a diagnostic device that simultaneously diagnoses a logic circuit when executing a task.
(2) 従来技術及び問題点
計算機の診断方式には種々の方法があるが、従
来技術は計算機のステイタス情報、データ情報の
オン／オフを、あるタイミングで読み取り、記録
し、障害発生時に、記録された情報をプリントア
ウトし、障害探索の一助として使用するものであ
る。(2) Prior art and problems There are various methods for diagnosing computers, but the conventional technology reads and records the computer's status information and data information on/off at a certain timing, and when a failure occurs, the recording is performed. This information can be printed out and used as an aid in troubleshooting.
ところがプリントアウトした内容から障害箇所
を発見する必要があり、診断に手間がかかつてい
た。 However, it was necessary to find the fault location from the printed information, which made diagnosis time-consuming.
(3) 発明の目的
本発明は、この様な点に鑑みてなされたもの
で、ハード命令の実行毎に診断を行なうことによ
り、障害発生箇所の発見を容易にした診断装置を
提供することを目的とする。(3) Purpose of the Invention The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a diagnostic device that facilitates finding the location of a failure by performing diagnosis every time a hardware instruction is executed. purpose.
(4) 発明の構成
上記目的は、本発明によれば、計算機の論理回
路内の任意信号を、計算機の各命令を実行してい
る時に、該命令毎の実行時間内のオン／オフの反
転回数を記憶する論理回路３，４，５，６，７
と、
前記各命令毎の前記任意信号の反転回数情報が
予め記憶された信号比較情報メモリ１１と、
該信号比較情報メモリ１１より実行中の命令に
対応した反転回数情報を読み出す回路９，１０，
１２と、
前記論理回路が記憶したオン／オフの反転回数
と、前記読み出された反転回数情報とを比較する
回路８と、
該比較回路８が不一致を検出したときには、前
記論理回路が記憶した前記任意信号の反転回数を
メモリ１５に記憶する回路１３，１４とを設けて
構成したことを特徴とする計算機の診断装置によ
つて達成される。(4) Structure of the Invention According to the present invention, the above object is to invert the on/off state of arbitrary signals in the logic circuit of a computer within the execution time of each instruction of the computer while executing each instruction of the computer. Logic circuits 3, 4, 5, 6, 7 that store the number of times
a signal comparison information memory 11 in which information on the number of times of inversion of the arbitrary signal for each instruction is stored in advance; circuits 9, 10 for reading out number of inversions information corresponding to the instruction being executed from the signal comparison information memory 11;
12; a circuit 8 that compares the number of on/off inversions stored in the logic circuit with the readout number of inversion information; and when the comparison circuit 8 detects a mismatch, the number of on/off inversions stored in the logic circuit is compared; This is achieved by a computer diagnostic device characterized in that it includes circuits 13 and 14 for storing the number of inversions of the arbitrary signal in a memory 15.
(5) 発明の実施例 以下本発明を実施例に基づいて説明する。(5) Examples of the invention The present invention will be explained below based on examples.
図は本発明の実施例を示す図で、１は計算機論
理回路、２は命令発生回路、３は命令オン／オフ
検出回路、４は信号オン／オフ検出回路、５，６
は反転検出カウンター、７は信号記録レジスタ
ー、８は比較回路、９は比較情報レジスタ、１０
は命令／アドレス変換回路、１１は信号比較情報
メモリ、１２はアドレス選択回路、１３は判定回
路、１４はメモリアドレス回路、１５はメモリで
ある。 The figure shows an embodiment of the present invention, in which 1 is a computer logic circuit, 2 is an instruction generation circuit, 3 is an instruction on/off detection circuit, 4 is a signal on/off detection circuit, 5, 6
is a reversal detection counter, 7 is a signal recording register, 8 is a comparison circuit, 9 is a comparison information register, 10
11 is an instruction/address conversion circuit, 11 is a signal comparison information memory, 12 is an address selection circuit, 13 is a determination circuit, 14 is a memory address circuit, and 15 is a memory.
以下動作について説明する。 The operation will be explained below.
計算機論理回路１から、障害診断に必要と考え
た任意の信号N0、N1、N2…Nnを信号オン／オ
フ検出回路４で各信号のオン／オフの反転を検出
する。この任意の信号は計算機の設計時に選定し
ておく。この検出時間は、命令発生回路２からの
命令オン／オフ検出回路３に導いた命令オン時間
により決めている。信号オン／オフ検出回路４で
検出された反転検出信号DN0、DN1、…DNnに
より反転検出カウンター５、反転検出カウンター
６を動作させ、カウントする。 From the computer logic circuit 1, arbitrary signals N0 , N1 , N2 , . This arbitrary signal is selected when designing the computer. This detection time is determined by the command on time guided from the command generation circuit 2 to the command on/off detection circuit 3. The inversion detection signals DN 0 , DN 1 , . . . DNn detected by the signal on/off detection circuit 4 operate the inversion detection counter 5 and the inversion detection counter 6 to perform counting.
カウントされた値CN0、CN1…C1Nn、C2N0、
C2N1…C2Nnを信号記録レジスター７にセツトす
る。 Counted values CN 0 , CN 1 …C 1 Nn, C 2 N 0 ,
C 2 N 1 ...C 2 Nn is set in the signal recording register 7.
一方、あらかじめ記録されている信号比転情報
メモリ１１より（命令／アドレス変換回路１０に
より選択されたアドレス）比較情報レジスター９
に反転回数をセツトする。そして比較回路８にお
いて信号記録レジスター７と比較情報レジスター
９の情報を比較する。比較情報を判定回路１３で
判断し不一致の特メモリに反転検出カウンター６
の情報を記録する。これにより異常と考えられる
信号情報の記録ができる。 On the other hand, from the signal ratio information memory 11 recorded in advance (the address selected by the instruction/address conversion circuit 10), the comparison information register 9
Set the number of reversals to . Then, the comparison circuit 8 compares the information in the signal recording register 7 and the comparison information register 9. The comparison information is judged by the judgment circuit 13 and a reversal detection counter 6 is stored in the special memory of the mismatch.
record information. This allows recording of signal information that is considered abnormal.
(6) 発明の効果
以上の如く本発明によれば、命令実行時に並行
して診断を行ないストアする様にしているので、
障害箇所の発見がきわめて容易である。(6) Effects of the Invention As described above, according to the present invention, diagnosis is performed and stored in parallel when an instruction is executed.
It is extremely easy to find the fault location.
図は本発明の実施例を示す図で、１は計算機論
理回路、２は命令発生回路、３は命令オン／オフ
検出回路、４は信号オン／オフ検出回路、５，６
は反転検出カウンター、７は信号記録レジスタ
ー、８は比較回路、９は比較情報レジスタ、１０
は命令／アドレス変換回路、１１は信号比較情報
メモリ、１２はアドレス選択回路、１３は判定回
路、１４はメモリアドレス回路、１５はメモリで
ある。
The figure shows an embodiment of the present invention, in which 1 is a computer logic circuit, 2 is an instruction generation circuit, 3 is an instruction on/off detection circuit, 4 is a signal on/off detection circuit, 5, 6
is a reversal detection counter, 7 is a signal recording register, 8 is a comparison circuit, 9 is a comparison information register, 10
11 is an instruction/address conversion circuit, 11 is a signal comparison information memory, 12 is an address selection circuit, 13 is a determination circuit, 14 is a memory address circuit, and 15 is a memory.
Claims (1)
各命令を実行している時に、該命令毎の実行時間
内のオン／オフの反転回数を記憶する論理回路
３，４，５，６，７と、 前記各命令毎の前記任意信号の反転回数情報が
予め記憶された信号比較情報メモリ１１と、 該信号比較情報メモリ１１より実行中の命令に
対応した反転回数情報を読み出す回路９，１０，
１２と、 前記論理回路が記憶したオン／オフの反転回数
と、前記読み出された反転回数情報とを比較する
回路８と、 該比較回路８が不一致を検出したときには、前
記論理回路が記憶した前記任意信号の反転回数を
メモリ１５に記憶する回路１３，１４とを設けて
構成したことを特徴とする計算機の診断装置。[Claims] 1. Logic circuits 3 and 4 that store the number of on/off inversions within the execution time for each instruction of an arbitrary signal in the logic circuit of the computer when executing each instruction of the computer. , 5, 6, 7, a signal comparison information memory 11 in which information on the number of times of inversion of the arbitrary signal for each of the instructions is stored in advance, and information on the number of times of inversion corresponding to the instruction being executed from the signal comparison information memory 11. Readout circuits 9, 10,
12; a circuit 8 that compares the number of on/off inversions stored in the logic circuit with the readout number of inversion information; and when the comparison circuit 8 detects a mismatch, the number of on/off inversions stored in the logic circuit is compared; A diagnostic device for a computer, comprising circuits 13 and 14 for storing the number of inversions of the arbitrary signal in a memory 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57144116A JPS5933561A (en) | 1982-08-20 | 1982-08-20 | Diagnostic system of computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57144116A JPS5933561A (en) | 1982-08-20 | 1982-08-20 | Diagnostic system of computer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5933561A JPS5933561A (en) | 1984-02-23 |
| JPH0410100B2 true JPH0410100B2 (en) | 1992-02-24 |
Family
ID=15354557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57144116A Granted JPS5933561A (en) | 1982-08-20 | 1982-08-20 | Diagnostic system of computer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933561A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147509A (en) * | 1974-10-23 | 1976-04-23 | Sumitomo Light Metal Ind | Seikeisei nosugureta kanetsukokagataaruminiumugokin |
| JPS5449040A (en) * | 1977-09-26 | 1979-04-18 | Nec Corp | Check unit for logic circuit |
-
1982
- 1982-08-20 JP JP57144116A patent/JPS5933561A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5933561A (en) | 1984-02-23 |
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