JPH0410221B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a pattern of polycrystalline silicon and a silicon compound without using a resist.

(b) Prior Art and Problems Microfabrication in the manufacturing process of semiconductor devices is mainly performed by the so-called lithography method. That is, for example, when shaping a conductor, semiconductor, or insulator film on a substrate into a desired shape and size, a desired pattern of a resist film is formed on the film and the resist film is used as a mask. Etching etc.
Alternatively, required pattern portions of the resist film are selectively removed, a film is formed thereon using a required material, and unnecessary portions of the film are peeled off together with the resist film.

In the lithography method that uses this resist to form a pattern, the resolution characteristics of the resist itself,
Properties such as photosensitive properties, adhesion, and etching resistance should be selected depending on the purpose, and the resist coating method, exposure, development treatment, and heat treatment before and after the resist should be carefully controlled. However, it still has the following problems.

For example, in order to miniaturize a pattern, it is necessary to reduce the thickness of the resist film, but reducing the thickness of the resist film increases the risk of pinholes and the like.

In exposure processing, as patterns become finer, a decrease in precision of resist patterns becomes a problem, such as light diffraction and copy rate, which have a large effect on image quality. For example, even when UV exposure is performed using a positive photoresist with excellent resolution characteristics, the light energy distribution in the resist film thickness direction becomes uneven due to the influence of light diffraction and standing waves, resulting in the end face after development becoming uneven. It is not vertical, and the pattern size is, for example, 1 [μ
m] or less, a so-called bridging phenomenon may occur in which the left and right end faces are not separated.

Furthermore, since the organic solvent used in the development process causes the resist to swell, a heat treatment called post-bake is required to remove the solvent and improve the adhesion of the resist. This is a factor in reducing pattern accuracy.

Furthermore, in the etching process after resist pattern formation, if the adhesion of the resist film is insufficient, the etching solution will enter between the resist film and the underlying layer in the wet etching process, resulting in a significant deterioration of pattern accuracy. . Furthermore, side etching, which appears particularly strongly in wet etching, greatly reduces the precision of the pattern obtained. Dry etching is increasingly being used to replace wet etching, which has many problems with pattern accuracy.
Dry etching generally has disadvantages such as poor selectivity due to differences in materials and requires a thicker resist film than wet etching.

(c) Object of the Invention In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device in which pattern formation is performed without using a resist.

(d) Structure of the Invention The object of the present invention is to form an amorphous silicon film on a semiconductor substrate, selectively irradiate the amorphous silicon film with an energy beam, and transform the amorphous silicon film into polycrystalline silicon. Alternatively, it is achieved by a manufacturing method in which the amorphous silicon film is converted into a film made of a compound with an element contained in the atmosphere in contact with the film, and the amorphous silicon film is selectively removed from the converted film. .

Furthermore, by forming a film containing impurities on the amorphous silicon film and then irradiating the energy beam, the impurities can be introduced into the polycrystalline silicon film to reduce its resistivity. can.

(e) Embodiments of the Invention The present invention will be specifically explained below using embodiments with reference to the drawings.

FIGS. 1a to 1c are cross-sectional views showing a first embodiment of a gate electrode of a MOS field effect transistor (MOS FET) according to the present invention.

Refer to FIG. 1a. A field oxide film 2 and a gate oxide film 3 are formed on a p-type silicon substrate 1 by a conventional technique.

An amorphous silicon film 4 is formed on the gate oxide film 3 and the feed oxide film 2 to a thickness of, for example, about 0.4 [μm] by, for example, electron beam evaporation.

Next, on the amorphous silicon film 4, a silicon dioxide film 5 doped with phosphorus P is formed to a thickness of, for example, about 0.6 [μm] by, for example, a sputtering method.
The thickness of this silicon dioxide film 5 is selected to minimize the reflectance when light is used as the energy beam as in this embodiment, and to have a sufficient amount of impurities for doping.

Refer to FIG. 1b. A region 4' of the amorphous silicon film 4 to be used as a gate electrode is selectively irradiated with an energy beam. In this example, a continuous wave argon (Ar) laser with an output of about 1 [W] is used as the energy beam, and scanning is performed at a speed of about 5 [cm/sec] with a beam diameter of about 1 [μm]. . The means for selecting the irradiation area may be by using a mask or by selective irradiation without using a mask. In addition, during this argon laser beam irradiation,
In this example, the temperature of the semiconductor substrate was set to 250 [℃]
It is heated to a certain degree.

The amorphous silicon in the region 4' irradiated with this energy beam is heated and grows crystal grains to become polycrystalline silicon. Further, in this process, the phosphorus doped into the silicon dioxide film 5 is diffused, and the polycrystalline silicon becomes n ⁺ type.

Refer to FIG. 1c. The silicon dioxide film 5 is removed using a hydrofluoric acid (HF)-based etching solution, and then hydrofluoric acid, nitric acid (HNO ₃ ),
The amorphous silicon film 4 is selectively removed using an etching solution containing phosphoric acid (H ₃ PO ₄ ) and perchloric acid (HClO ₄ ). This selective etching can also be carried out by reactive ion etching. As a result, a gate electrode 6 made of n ⁺ type polycrystalline silicon is formed.

An n-channel silicon gate MOS FET can be manufactured using the following conventional techniques. Furthermore, a p ⁺ type polycrystalline silicon gate electrode can be formed by doping the silicon dioxide film 5 with, for example, boron B and applying the same manufacturing method as in the above embodiment.

Furthermore, other components than the gate electrode, such as wiring, can also be formed in the same manner as in the embodiments described above. Even when the electrode or lower layer wiring to which this wiring is connected is made of a high melting point metal or its silicide, eutecticization is automatically performed by the energy beam irradiation of the present invention.

FIGS. 2a to 2c are cross-sectional views showing an embodiment of the present invention for forming a mask for selective ion implantation made of silicon oxide.

Refer to Figure 2a. As a semiconductor substrate for a high electron mobility field effect transistor, a semiconductor substrate with a thickness of about 1 [μm] is grown on a semi-insulating gallium arsenide compound (GaAs) semiconductor substrate 11 by a molecular beam crystal growth method. Non-doped gallium arsenide compound (GaAs) semiconductor layer 12
Then, an n-type aluminum-gallium-arsenic compound (AlGaAs) semiconductor layer 13 having a thickness of about 100 [nm] is formed. Furthermore, in order to prevent the AlGaAs layer 13 from being oxidized in the atmosphere, the aluminum nitride (AlN) film 1 is kept in a vacuum state after the crystal growth.
4 is formed to a thickness of about 200 [nm] by sputtering or the like. Note that 15 is an electron storage layer formed near the heterojunction interface of the GaAs layer 12.

Refer to FIG. 2b. An amorphous silicon film 16 is deposited on the aluminum nitride film 14 to a certain thickness by, for example, electron beam evaporation.
Form to a thickness of about 0.5 [μm] or more.

Next, in an oxidizing atmosphere, for example in contact with an oxygen stream, the region 16' of the amorphous silicon film 16 where the mask is to be formed is selectively irradiated with energy beams.
In this embodiment, like the previous embodiment, argon laser light is used.

The amorphous silicon in the region 16' irradiated with this energy beam is heated and oxidized to form a silicon oxide film 17.

Refer to FIG. 2c. Similar to the above embodiment, the amorphous silicon film 16 is etched by wet etching using an etching solution containing hydrofluoric acid, nitric acid, phosphoric acid, and perchloric acid (HClO ₄ ), or by reactive ion etching. By selectively removing the silicon oxide film 17, a mask is formed.

With this mask, for example, silicon can be
Source and drain formation region 1 of AlGaAs layer 13
8 is selectively implanted with ions.

A high electron mobility field effect transistor can be manufactured using the following conventional techniques.

(f) Effects of the Invention As explained above, according to the present invention, it is possible to form electrodes and wiring made of polycrystalline silicon, as well as patterns made of silicon compounds such as silicon oxide, without using a resist. In addition, as a means of pattern formation, it is possible to apply not only an optical method using a mask but also a direct writing method using a laser beam or an electron beam, and to manufacture a semiconductor device in which problems related to resists are eliminated. be able to.

[Brief explanation of drawings]

FIGS. 1a to 1c are cross-sectional views showing an embodiment of the present invention relating to the formation of a silicon gate electrode of a MOS field effect transistor, and FIGS. 2a to 2c are sectional views showing an embodiment of the present invention in which a mask is formed of silicon oxide. FIG. In the figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is an amorphous silicon film, 5 is a phosphorous-doped silicon dioxide film, and 6 is a silicon dioxide film doped with phosphorus.
is a silicon gate electrode, 11 is a semi-insulating GaAs substrate, 12 is a GaAs layer, 13 is an AlaAs layer, 14 is a
AlN film, 15 electron storage layer, 16 amorphous silicon film, 17 silicon oxide mask, 18
indicates the source and drain forming regions.

Claims (1)

[Claims] 1. Forming an amorphous silicon film on a semiconductor substrate,
When selected, the amorphous silicon film is irradiated with an energy beam to convert the amorphous silicon film into a film made of polycrystalline silicon or a compound with an element contained in the atmosphere in contact with the amorphous silicon film, and the converted silicon film is A method for manufacturing a semiconductor device, comprising the step of selectively removing the amorphous silicon film with respect to the film. 2 forming a film containing impurities on the amorphous silicon film, and then selectively irradiating the energy beam to convert the amorphous silicon film into a polycrystalline silicon film containing the impurities; A method for manufacturing a semiconductor device according to claim 1.