JPH0410249B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides TTL (transistor
Regarding logic) circuits, in particular, the input threshold voltage of TTL circuits using PNP transistors in the input stage was corrected without sacrificing high-speed operation.
Regarding TTL circuit.

TTL circuits are well known as a type of logic circuit based on bipolar integrated circuits (ICs). recent years,
With the increasing density and integration of ICs, epitaxial growth layers are becoming increasingly thinner, and with advances in lithography technology, the windows for electrodes are becoming smaller and smaller. For this reason, the withstand voltage of ICs against electrical shock is becoming lower.

Traditionally, it has been commonly used as an input stage element to increase the withstand voltage in the input stage of TTL circuits.
A Schottky diode with a high breakdown voltage is used instead of an NPN transistor, or a PNP transistor with a high breakdown voltage between the base and collector is used with the collector grounded.

However, the forward voltage drop of a Schottky diode and the forward voltage drop between the emitter and base of a PNP transistor are lower than the forward voltage drop between the base and emitter of an NPN transistor, so a Schottky diode is used in the input stage of a TTL circuit. The input threshold voltage when using a PNP transistor or an NPN transistor is different from that when using an NPN transistor. become.

A circuit called VTL (variable threshold logic) is known as a TTL circuit that corrects variations in input threshold voltage from a standard value. In this VTL, for example, between the anode of the Schottky diode in the input stage and the base of the next stage transistor, or between the power supply,
A resistor for correcting the input threshold voltage is connected, and the switching speed of the TTL circuit is slow due to the parasitic capacitance associated with the resistor for correcting the threshold voltage.

In view of the above-mentioned drawbacks of the conventional TTL circuit, an object of the present invention is to insert a resistor for correcting the input threshold voltage between the emitters of the input stage PNP transistor and the emitter resistor. The purpose of this invention is to correct the input threshold voltage in a TTL circuit using PNP transistors in each stage without impairing the withstand voltage and switching speed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in comparison with conventional examples based on the accompanying drawings.

FIG. 1 is a circuit diagram showing an example of a well-known basic TTL circuit. In Figure 1, T ₁ , T ₂ , T ₃ are
It is an NPN transistor. When the input voltage V _IN is at a low level (L level), the transistor T ₁ is on, the transistor T ₂ is off, and the transistor T ₃ is also off, and the output voltage V _OUT is at a high level (H level). When the input voltage V _IN is at H level,
_T1 is off, _T2 is on, _T3 is also on, and V _OUT is at L level. The input threshold voltage V _TH for turning on the transistor T ₃ is V _TH = V _FC (T ₁ ) + V _FE (T ₂ ) + V _FE (T ₃ ) − V _FE (T ₁ ). Here, V _FC (T ₁ ) is the base-collector forward voltage of T ₁ , V _FE (T ₂ ) is the base-emitter forward voltage of T ₂ , and V _FE (T ₃ ) is the base-to-emitter forward voltage of T ₃ .・
The emitter-to-emitter forward voltage, V _FE , is the base-to-emitter voltage of T ₁ , and each is about 0.8V, so V _TH is about 1.6V.

The circuit shown in Figure 1 uses an NPN transistor in the input stage, and its base-emitter breakdown voltage is approximately
The shortcoming is that it is extremely low at 7V, and is easily destroyed if the input voltage _VIN becomes high due to electrical shock.

Figure 2 shows a Schottky diode D in the input stage.
1 is a circuit diagram showing an example of a well-known DTL circuit using a DTL circuit. Since the Schottky diode has a withstand voltage of 20V or more, the TTL circuit shown in Figure 2 is more resistant to electrical shock than the circuit shown in Figure 1. In FIG. 2, the input threshold voltage V _TH for turning on transistor T ₂ is V _TH =V _FE (T ₁ )+V _FE (T ₂ )−V _F (D). Here, V _FE (T ₁ ) and V _FE (T ₂ ) are each about 0.8 V as in the case of Fig. 1, but the forward voltage drop V _F (D) of Schottky diode D is about
It is 0.4V. Therefore, V _TH is approximately 1.2V, which deviates significantly from the standard value, resulting in a shift in switching timing and a reduction in margin for the amplitude of the input voltage. Therefore, in a TTL circuit that uses a Schottky diode in the input stage, it is necessary to correct the input threshold voltage to the standard value of 1.6V.

FIG. 3 is a circuit diagram showing an example of a conventional TTL circuit in which input threshold voltage correction means is added to the circuit of FIG. 2. In FIG. 3, a resistor R for threshold voltage correction is connected between the anode of the input stage Schottky diode D of the circuit of FIG. 2 and the base of the next stage NPN transistor _T1 . be. The resistance value of the resistor R is set so that the voltage drop V(R) that occurs across R when the base current flows through the transistor _T1 is approximately 0.4V.
The input threshold voltage V _TH is V _TH =V _FE (T ₁ )+V _FE (T ₂ )−V _F (D)+V(R), which is about 1.6 V, which almost matches the standard value.
The circuit of Figure 3 is known as a VTL.

However, according to the conventional circuit shown in FIG. 3, when the resistor R is formed from a bulk impurity diffusion layer (for example, P-type), the diffusion layer for the resistance and the underlying epitaxial layer (for example, N-type) are A parasitic capacitance is formed between the two.

This parasitic capacitance, as shown by C in Figure 3, is
For example, there is a component connected in parallel to the resistor R, and another component connected to the power supply. (Only the parallel component is shown here.) Therefore, if you want to turn off the transistor _T1 by removing the charge accumulated in the base of the transistor _T1 , you must also remove the charge of the parasitic capacitance C. , the speed at which transistor _T1 turns off becomes slower. (Capacitance components attached to the power supply other than the parasitic capacitance C shown in the figure also delay the turning off of transistor _T1 for the same reason.) On the other hand, when turning on transistor _T1 , the relationship between R and C should be selected appropriately. For example, the transistor _T1 can be turned on more quickly, but as mentioned above, since the transistor _T1 turns off slowly, it has the disadvantage that the switching speed of the transistor _T1 is slow. (The capacitive component attached to the power supply acts in the direction of delaying the ON of _T1 .) FIG. 4 is a circuit diagram showing an example of a conventional TTL circuit using a PNP transistor in the input stage.
In FIG. 4, the base of the input stage transistor _Q1 is connected to the input terminal IN, the collector is grounded, and the emitter is connected to the power supply line _VCC via the emitter resistor _R1 .
Connected to the base of NPN transistor _Q2 . The collector of the transistor _Q2 is connected to the power supply line _VCC via the load resistor _R2 , and the emitter is connected to the base of the next stage NPN transistor _Q3 . Base of transistor Q ₃ and input terminal IN
A Schottky barrier diode _D1 for discharging base charges is connected between them with its anode facing the base side. The collector of the transistor _Q3 is connected to the power supply line _VCC via a load resistor _R3 , and the emitter is grounded via an emitter resistor _R4 . The collector of transistor Q ₃ is also
It is also connected to the first output terminal OUT ₁ , and its emitter is also connected to the base of the NPN transistor _Q4 . The emitter of transistor _Q4 is grounded, and the collector is connected to the second output terminal _OUT2 . The collector of transistor Q ₂ is also connected to the base of NPN transistor Q ₅ , the collector of transistor Q ₅ is connected to the power supply line V _CC , and the emitter is connected to the anode of diode D ₂ . The cathode of diode D ₂ is connected to the collector of transistor Q ₄ .

By adopting a PNP transistor in the input stage, firstly, the input has a low level voltage (e.g.
0.4V) is applied, the current _IIL flowing from the input terminal is only (1-α) times the current I _R1 flowing through the resistor R (here α represents the current amplification factor).
The input characteristics are significantly improved, and secondly, Q ₁
The withstand voltage between base and collector and base and emitter is still more than 20V, so it has the advantage of high input withstand voltage.

However, even in the circuit of FIG.
Similar to the circuit shown in the figure, this circuit has the disadvantage that the input threshold voltage deviates from the standard value. That is, the input threshold voltage V _TH that turns on transistor Q ₄ is V _TH = V _FE (Q ₄ ) + V _FE (Q ₃ ) + V _FE (Q ₂ )−V _FE (Q ₁ ). Here, V _FE (Q ₄ ), V _FE (Q ₃ ), V _FE (Q ₂ )
are the base-to-emitter forward voltages of transistors Q ₄ , Q ₃ , and Q _{2 ,} respectively, and are approximately 0.8 V, respectively.
V _FE (Q ₁ ) is the forward voltage between the emitter and base of the PNP transistor, which is approximately 0.6V. PNP transistor emitter-base forward voltage V _FE (Q ₁ )
is approximately 0.2V lower than the base-emitter voltage of an NPN transistor, so V _TH is 1.8V, higher than the standard value of 1.6V. For this reason, the conventional circuit shown in FIG. 4 has the disadvantages that the switching timing is shifted and the margin for the amplitude of the input voltage is reduced for the same reasons as the conventional circuit shown in FIG. 2.

FIG. 5 is a circuit diagram showing an embodiment of the present invention that solves the drawbacks of FIG. 4. The difference between FIG. 5 and FIG. 4 is that a resistor R ₀ for input threshold voltage correction is inserted between the emitter of PNP transistor Q ₁ and its emitter resistor R ₁ . Since it is similar to FIG. 4, the same reference numerals are given. The value of the resistor R ₀ is set so that when a current flows through R ₀ , the voltage drop across R ₀ is approximately 0.2V. As a result, the third
As in the figure, the input threshold voltage is the standard value.
Almost matches 1.6V. That is, V _TH = V _FE (Q ₄ ) + V _FE (Q ₃ ) + V _FE (Q ₂ ) − V (R ₀ ) − V _FE (Q ₁ ) = 0.8 + 0.8 + 0.8 − 0.2 − 0.6 = 1.6V The resistor R ₀ is also accompanied by a parasitic capacitance C ₀ during the manufacturing process of a semiconductor integrated circuit for the same reason as the example shown in FIG. 3, but according to the circuit configuration shown in FIG _.
The switching speed will not be slowed down by this effect. The resistance value of the resistor R ₀ used in the present invention is, for example, several hundred ohms, whereas the resistance R is, for example, several tens of kilohms. The reason for this will be described below while explaining the operation of the circuit shown in FIG.

When the input terminal IN is at L level (for example, 0.4V),
PNP transistor Q ₁ is on, NPN transistor
Since the base potential of Q ₂ is low, it is off, so Q ₃ is also off, and Q ₄ is also off, and Q ₅ is on because its base potential is high, and both the output terminals OUT ₁ and OUT ₂ are at H level. Input terminal IN is at H level (e.g.
2.4V), Q ₁ is off, so Q ₂ is on, Q ₃
is on, Q ₄ is on, Q ₅ is off, OUT ₁ , OUT ₂
are both at L level. The voltage of input terminal IN is L
level (e.g. 0.4V) to H level (e.g.
2.4V), as soon as the input threshold voltage (e.g. 1.6V) is exceeded, Q ₁ turns off and as a result, even if C ₀ has charge stored, the capacitance C ₀ remains in a floating state. Because I'm getting used to it,
No current flows through resistor R ₁ , and the base potential of Q ₂ immediately reaches the V _CC level. Therefore, Q ₂ is immediately turned on without being affected by capacitance C ₀ .

Also, when the voltage at the input terminal IN transitions from H level to L level, _Q1 turns on when it becomes below the input threshold voltage, and the charge accumulated at the base of _Q2 is removed from the emitter by the transistor operation of _Q1 . Since it is actively drawn out to the collector, the base charge of _Q2 can be drawn out almost unaffected by the parasitic capacitance _C0 , so the output terminal OUT,
or rise propagation time t at OUT _{2 PLH} is the capacitance
Almost unaffected by C ₀ . In this way, Q ₂ can be turned on and off almost unaffected by the parasitic capacitance C ₀ . Therefore, the falling propagation time t _PHL at the output terminal OUT ₁ or OUT ₂
is not affected by the capacitance C ₀ at all. Furthermore, the voltage at the input terminal IN changes from H level (for example, 2.4V) to L level.
level (e.g. 0.4V), below the threshold voltage (e.g. 1.6V) transistor Q ₃ is turned off and the Schottky diode D ₁
discharges the charge accumulated in the base of transistor _Q3 to the input terminal IN side, so _Q3 immediately turns off without being affected by the parasitic capacitance _C0 , and therefore _Q4 also turns off. Therefore, from this point as well, the rise propagation time of output terminal OUT ₁ or OUT _2
tPLH is hardly affected by parasitic capacitance _C0 .

As is clear from the above explanation, the input stage
In a TTL circuit with improved input characteristics and withstand voltage characteristics using a PNP transistor, by placing the resistor R ₀ in the position shown in Figure 5, this resistance
The input threshold voltage can be corrected to the standard value at low cost without affecting the switching speed of the next stage transistors Q ₂ to _{Q 5} due to the influence of the parasitic capacitance C ₀ on R ₀ and without impairing the withstand voltage. This improves the reliability of TTL circuit operation.

Note that the present invention is not limited to the embodiment shown in FIG. 5, but can be applied to all TTL circuits using PNP transistors in the input stage. For example, in FIG. 5, a threshold voltage correction resistor may be further inserted between the transistor Q ₂ and the emitter resistor R ₁ . Again, the transistor
Since the base charge of transistor Q ₂ is extracted by Q ₁ , the switching speed of transistor Q ₂ due to the parasitic capacitance of the compensation resistor is hardly affected.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a well-known basic TTL circuit, and Fig. 2 is a circuit diagram showing an example of a well-known DTL circuit using a Schottky diode D in the input stage.
Figure 3 is a circuit diagram showing an example of a conventional TTL circuit in which an input threshold voltage correction means is added to the circuit in Figure 2, and Figure 4 is an example of a conventional TTL circuit using a PNP transistor in the input stage. FIG. 5 is a circuit diagram showing an embodiment of the present invention which solves the drawbacks of FIG. 4. Q ₁ ... Input stage PNP transistor, D ₁ ... Schottky diode for base charge release, R ₀ ...
Input threshold voltage correction resistor, _R1 ...Emitter resistor.

Claims (1)

[Claims] 1. The collector is grounded, and the emitter is the first
and an input stage which is connected to the power supply via second resistors R ₀ and R ₁ and whose base is connected to the input terminal.
A PNP transistor _Q1 , with its collector connected to the output end,
the first whose emitter is grounded to ground potential;
NPN transistor Q ₃ has a base connected to the connection point of the first and second resistors, a collector connected to the power supply via the fourth resistor R ₂ , and an emitter of the first NPN transistor Q ₃ . a second NPN transistor Q 2 connected to the base; and a second NPN transistor Q ₂ whose cathode is connected to the base of the input stage PNP transistor and whose anode is connected to the base of the first NPN transistor.
and a Schottky diode _D1 for discharging base charge of an NPN transistor, and by setting the first resistance value to a predetermined value, the threshold voltage at the input terminal is set to a specified value. A TTL circuit featuring