JPH0410657B2 - - Google Patents

Description

Claim 1: A bus failure detection device, comprising: a bus; a plurality of devices each having a terminal connected to the bus; first and second power supply terminals; and an impedance control terminal; a first power source of the plurality of devices; means for interconnecting supply terminals; means for interconnecting second power supply terminals of the plurality of devices; energizing means for energizing the plurality of devices; generating a fault signal in response to a fault condition on the bus; means for transmitting a signal to an impedance control terminal of each of the plurality of devices in response to the fault signal to place each of the plurality of devices in a high impedance state; means for separately transmitting first and second signal levels on a bus; a first sensing current flowing between the energizing means and a first interconnected power supply terminal of the plurality of devices; current detection means; first error signal generation means for generating a first error signal when the current detected by the first current detection means exceeds a first predetermined magnitude; and the energization. second current sensing means for sensing a current flowing between the means and interconnected second power supply terminals of the plurality of devices; a second error signal generating means for generating a second error signal when the predetermined magnitude of the error signal exceeds a predetermined magnitude, and the first and second predetermined magnitudes can be made equal. Bus failure detection device.

2. The bus fault detection device according to claim 1, further comprising: generating a composite error signal when the first error signal generating means generates the error signal; A bus fault detection device comprising: means for generating the composite error signal when the generating means generates the second error signal.

3. The bus failure detection device according to claim 2, further comprising means for storing the composite error signal.

4. The bus failure detection device according to claim 1, wherein the first current detection means is connected between the biasing means and the interconnected first power supply terminals of the plurality of devices. a first resistive means connected between the biasing means and a second interconnected power supply terminal of the plurality of devices; and the bus failure detection device further includes: means connected in parallel with the first resistance means and shorting the first resistance means; and means connected in parallel with the second resistance means and shorting the first resistance means. and means for short-circuiting the means.

5. The bus failure detection device according to claim 1, wherein each of the plurality of devices is a three-state device.

Technical Field This invention is directed to detection of transmission line or bus failure points,
More specifically, the present invention relates to a bus failure point detection method and apparatus used when a bus connecting a plurality of devices is locked in a certain logical state.

BACKGROUND OF THE INVENTION Computer systems typically include many circuit packs connected directly to a shared bus. Each circuit pack interfaces with this bus through one or more devices, which may be transmitters, receivers, or transceivers, depending on the function performed by the circuit pack. for example,
When one of these devices fails due to a short circuit in the semiconductor junction, the bus or part of it becomes a logic zero due to the low impedance path to the voltage source used to energize the circuit pack. Or it is locked to logic 1. Detecting this type of bus failure is relatively straightforward. However, it is more difficult to localize this fault to a particular circuit pack, and this is often done manually by replacing one circuit pack at a time. The present invention provides a method and apparatus for automatically detecting the source of this bus fault.

SUMMARY OF THE INVENTION The bus fault detection apparatus of this invention includes a bus, a number of devices connected to the bus, and a power supply for energizing the device. A signal is sent to place a particular device in a high impedance state, and a predetermined signal level is sent to this bus. The current between the particular device and the power supply is sensed and an error signal is generated when the sensed current exceeds a predetermined magnitude.

[Brief explanation of drawings]

1 is a block diagram of a system according to the invention; FIGS. 2 and 3 show detailed views of the circuit packs included in the system of FIG. 1 when arranged according to FIG. 5; and FIG. 4 is a diagram showing details of the bus diagnostic device included in the system of FIG. 1.

General Description FIG. 1 shows a system 10 implementing an exemplary embodiment of a bus fault detection apparatus according to the principles of the present invention.
FIG. In the system 10, a plurality of circuit packs 100-0, 100-1...100
-N provides internal communication via a shared four conductor bus. Each circuit pack 100-0,100-
1...100-N are energized by power supply 200 and include four transmitters and four receivers connected directly to bus 500. For example, circuit pack 100-0 (FIGS. 2 and 3 arranged according to FIG. 5) includes transmitters 101-1, 101-2, 10
1-3 and 101-4 and receiver 102-1,
102-2, 102-3, and 102-4. In this example, the transmitter and receiver are Complementary MOS (CMOS) integrated circuit three-state devices. In FIG. 3, the power supply terminals of each three-state device are designated V and G, and the input and output terminals are designated I and O, respectively. The terminal denoted C here represents an impedance control terminal. When a three-state device is placed in a high impedance state by a logic 1 signal being sent to terminal C,
The device cannot prevent other devices from transmitting data on bus 500. In order to sense the current between power supply 200 and the three-state devices on a particular circuit pack, the power supply terminals of each three-state device on the pack are connected to a pair of terminals BVCC and
Internally connected via BGND (Figure 3). Resistor 184 (FIG. 2) and relay contact 182 in the normally closed position connect the BVCC terminal to power source 200.
Connected in parallel with VCC pin. Similarly,
Resistor 183 and relay contact 18 in normally closed position
1 is connected in parallel between the BGND terminal and the GND terminal of the power supply source 200. Both relay contacts 182 and 181 are controlled by a single relay input circuit 180. Resistors 184 and 183 operate when voltage is applied to relay input circuit 180, thereby opening relay contacts 181 and 182.
Current between BVCC and VCC and BGND, respectively
used to sense the current between GND and GND.

In this example, the data is transferred to bus 500 (first
(FIG.) in four bit units (nibbles) each containing one parity bit carried on one of the conductors of bus 500. Central control device 40
0 monitors all data transmitted on bus 500 to detect parity bit errors.
When central controller 400 determines that a fault condition exists on bus 500 based on the detected parity error, it transmits a signal, referred to as a fault signal, to conductor 401.
is transmitted to the bus diagnostic device 300 via. In response, bus diagnostic device 300 detects circuit pack 100.
-0,100-1...100-N input terminal CB0,
Send a logic 0 signal to CB1...CBN to place each transmitter and receiver in circuit packs 100-0, 100-1...100-N into a high impedance state. The source of the bus fault condition may be one or more conductors of bus 500 and terminals BVCC and C of circuit pack 100-0 (FIGS. 2 and 3 arranged according to FIG. 5).
A logic 1 signal is sent to pack 100-0 input terminal CA0 to determine if there is a low impedance path to one of the
Sent to 0. Thus, relay contacts 181 and 182 open. Bus diagnostic device 300 then sends first a logic 1 signal and then a logic 0 signal on all four conductors of bus 500. When a low impedance path exists between the bus 500 and the BGND of the pack 100-0, the bus diagnostic device 300
(FIG. 1) sends a logic one signal on bus 500, a current greater than a predetermined magnitude is sensed by resistor 183. Similarly, bus 500 and park 1
When a low impedance exists between 00-0 BVCC, a current greater than a predetermined magnitude is sensed by resistor 184 when bus diagnostic device 300 sends a logic 0 signal on bus 500. When either condition exists, pack 100-0 outputs a logic 1 signal via relay bus 250 to terminal
It is sent from RA0 to the bus diagnostic device 300. To improve reliability, a logic 0 signal is also transmitted via relay bus 250 from output terminal RB0 to bus diagnostic device 300. In response to these signals, bus diagnostic equipment 300 determines that pack 100-0 is the source of the bus fault, and this information is sent to a technician by equipment not shown here, causing pack 100-0 to be the source of the bus fault.
Perform 00-0 exchange. Alternatively, in the case of a duplex system, this information is sent to the central controller to activate the other side of the duplex pack. This process continues until the source of the bus fault condition is detected.
Repeat from 100-N.

DETAILED DESCRIPTION System 10 operates in three modes, referred to herein as normal, diagnostic, and current sensing test modes. In normal mode, pack 100-0,
100-1...100-N communicate internally via bus 500 to perform system functions. system 1
0 operates in diagnostic mode to detect the source of a fault condition on bus 500 in the manner described above. Finally, system 10 operates in a current sensing test mode to verify the correct operation of the circuitry used in the diagnostic mode in the manner that will now be described. Control circuit 1 in circuit pack 100-0 (FIGS. 2 and 3 arranged according to FIG. 5)
50, impedance control circuits 120 and 12
0' and indicator 195 indicate circuitry added to pack 100-0 to achieve the bus fault detection capability of the present invention. The circuitry that allows circuit pack 100-0 to perform system functions in normal mode is represented by circuit 110, which is connected to conductors 105-1, 105-2, 105-3, and 105-2.
Transmitter 101-1, 101- via 05-4
2, 101-3, and 101-4, and also conductors 106-1, 106-2, 1
Receiver 102 via 06-3 and 106-4
-1, 102-2, 102-3, and 102-4
is connected to the O output terminal of Circuit 110 is, for example, a microcomputer or a terminal of a microcomputer. When the system 10 does not incorporate the bus failure detection device of the present invention, the circuit pack 100-0 includes the circuit 110, the transmitter 101-
1,101-2,101-3, and 101-4 and receiver 102-1,102-2,102-
3, and 102-4, circuit 110 directly controls the impedance state of these transmitters and receivers via conductors 111 and 112. Circuit pack 100- related to the present invention
0, 100-1...100-N are all the same, so only pack 100-0 will be described in detail.

The selection of normal, diagnostic, or current sensing test modes of operation is controlled by a bus diagnostic device 300 (FIG. 4), which is connected to a microprocessor by a microprocessor bus 305. 301 (e.g. Intel 8085),
Includes direct access storage 302, read only storage 303, and parallel input/output ports 304 (eg, Intel 8255). A storage device 303 stores programs that define the operation of the bus diagnostic device 300, and a storage device 302 is a working memory necessary for the operation of the microprocessor 301.
Parallel input/output port 304 connects to central controller 400
A fault signal is received on conductor 401 indicating that detection of a fault condition on bus 500 has been made by. Microprocessor 301 has parallel input/output ports 304, buffer stores 310-0 through 310-N, and 311-3 through 311-N.
Through circuit packs 100-0 to 100
-N related input terminals CA0 to CAN
System operation is controlled by controlling the transmission of control signals from CB0 to CBN. The microprocessor 301 further includes a parallel input/output port 3.
04 to buffer storage devices 308-1, 308-2,
308-3 and 308-4 and relay contacts 307-1, 307-2, 307- in the normally closed position.
3 and 307-4 to the bus 500, this contact is connected to the parallel input/
Relay input circuit 306 via output port 304
The bus diagnostic device 300 is isolated from the bus 500 until the circuit is closed in response to the voltage being applied to the bus diagnostic device 300 .
Parallel input/output port 304 transmits signals indicating the results of fault detection diagnostics to circuit pack 1 via response bus 250 and buffer stores 309-1 and 309-2.
Receive from 00-0 to 100-N. Two pull-up resistors 351 and 352 are connected between the conductors of response bus 250 and the VCC terminal of power supply 200 to enable proper operation of response bus 250 with an open current collector gate.

The bus diagnostic device 300 has a circuit pack input terminal CA.
System operation is maintained in normal mode by sending a logic 0 signal from 0 to CAN and a logic 1 signal from circuit pack input terminal CB0 to CBN. In the circuit pack 100-0 (FIGS. 2 and 3 constructed according to FIG. 5), the terminal
When a logic 0 signal arrives at CA0 and a logic 1 signal arrives at terminal CB0, a logic 0 signal is sent by inverter 151 and OR gate 150 of control circuit 150 to impedance control circuits 120 and 120'. The impedance control circuit 120 includes one inverter 121 and two AND gates 1
22 and 123 and one OR gate 124. Similarly, impedance control circuit 120'
is one inverter 121', two AND gates 122' and 123', and one OR gate 12.
4' included. Inverter 151 and OR gate 1
52, which causes OR gate 124 to output circuit 11 on conductor 112.
A logic signal having the same logic value as the logic signal transmitted from 0 is transmitted. The output terminals of the OR gate 124 are the transmitters 101-1, 101-2, 101-
3, and the C input terminal of 101-4. Therefore, in normal mode, circuit 110
directly controls the impedance state of transmitters 101-1, 101-2, 101-3, and 101-4 based on logic signals transmitted on conductors 112. Similarly, in normal mode, circuit 110
is further transmitted to the receivers 102-1, 102-2, 102- based on the logic signals transmitted on the conductor 111.
3, and 102-4. Furthermore, in normal mode, when a logic 0 signal is received at terminal CA0, relay driver 153
sends a logic zero signal to relay input circuit 180. Therefore, relay contacts 181 and 182, which are in the normally closed position, remain closed.

Bus diagnostic device 300 establishes a diagnostic mode of system operation by transmitting logic 0 signals from circuit pack input terminals CA0 to CAN and from CB0 to CBN. In circuit pack 100-0 (FIGS. 2 and 3 arranged according to FIG. 5), when a logic 0 signal is received at terminals CA0 and CB0, inverter 151 and OR gate 152 of control circuit 150 are Therefore, the impedance control circuit 120
A logic one signal is sent to and 120'. In response to transmission of a logic one signal by impedance 151 and OR gate 152, OR gates 124 and 124' connect circuit 11 on conductors 111 and 112.
transmitting a logic 1 signal regardless of the logic signal transmitted by the 0, resulting in transmitter 101-1,
101-2, 101-3 and 101-4 and receivers 102-1, 102-2, 102-3 and 1
02-4 is placed in a high impedance state.

Bus diagnostic device 300 determines whether circuit pack 100-0 is the source of a bus fault condition.
changes the signal sent to terminal CA0 from a logic 0 to a logic 1, and relay driver 153 responds by sending a logic 1 signal to relay input circuit 180. Then, relay contact 1 in the normally closed position
81 and 182 are opened, and resistors 184 and 1
83 between BVCC and VCC and between BGND and
Enables sensing of current between GND. In addition, in response to the logic one signal at terminal CA0, monostable multivibrator 158 sends a pulse to reset flip-flop 191;
The flip-flop is used to store error signals as described below. Bus diagnostic device 300 then transmits a first logic 0 signal on all four conductors of bus 500 followed by a logic 1 signal. As mentioned above, when a low impedance path exists between the bus 500 of the circuit pack 100-0 and BGND, the bus diagnostic device 300
Sending a logic 1 signal on 0 causes the current through resistor 183 to exceed a predetermined magnitude. Similarly, when a low impedance path exists between bus 500 of circuit pack 100-0 and BVCC, when bus diagnostic device 300 sends a logic 0 signal on bus 500, the current flowing through resistor 184 is Beyond scale. When the current flowing through resistor 183 exceeds a predetermined magnitude, comparator 188 outputs a logic 1 signal, herein referred to as the first error signal, to OR gate 1.
90 to one input terminal. Similarly, when the current flowing through resistor 184 exceeds a predetermined magnitude, comparator 189 sends a logic one signal, herein referred to as a second error signal, to the other input terminal of OR gate 190. In both excess currents, OR gate 190 sends a logic 1 signal, referred to herein as a composite error signal, to set flip-flop 191.

In the high impedance state, eight National Semiconductor MM70C95 (National Semiconductor
MM70C95) The three-state devices together draw up to 15 microamps of current from the power supply 200. Therefore, bus 5 of circuit pack 100-0
When there is no low impedance path between 00 and BGND or BVCC, the current flowing between resistors 180 and 184 will be up to 15 microamps. In this embodiment, the comparison of the current flowing between resistors 184 and 183 with a predetermined magnitude is such that the voltage between these resistors 184 and 183 through which each fixed magnitude of current flows is equal to the voltage between 187 and 185. This is achieved by comparing. In this example, the voltage at VCC and the resistance values of resistors 183, 184, 185, 186, and 187 are such that comparator 188 indicates that the current flowing across resistor 183 is 500 microamps, as shown in Table 1. Similarly, comparator 189 is selected to generate a logic 1 signal when the current flowing across resistor 184 exceeds 500 microamps.

Table 1 VCC = +5 volts Resistor 183 = 5 ohm Resistor 184 = 5 ohm Resistor 185 = 5 ohm Resistor 187 = 5 ohm Resistor 186 = 9990 ohm As mentioned above, the flip-flop 191 is connected to the bus diagnostic device 300. When the signal at terminal CA0 changes from a logic 0 to a logic 1, it is reset by a pulse from monostable multivibrator 158. When set by a logic 1 composite error signal sent from OR gate 190, flip-flop 191 sends a logic 1 signal from its Q terminal to open current collecting OR gate 194 and also sends a logic 0 signal from its Q terminal. It is transmitted to the open current collection OR gate 193. The logic 1 signal appearing at terminal CA0 is inverted by inverter 192;
The resulting logic 0 signal is sent to the other input terminals of OR gates 194 and 193. Therefore, OR gate 194 sends a logic 1 signal on response bus 250 via terminal RA0, and OR gate 193 sends a logic 0 signal on response bus 250 via terminal RB0, which signals are transmitted to bus diagnostic device 300. The source of the bus fault condition is circuit pack 1.
00-0. On the other hand, when there is no low impedance path fault in circuit pack 100-0, flip-flop 191 is not set and logic 0 and logic 1 signals are transmitted by OR gates 194 and 193, respectively, via response bus 250. This indicates to bus diagnostic system 300 that circuit pack 100-0 is not the source of this bus fault condition. This process then continues from circuit pack 100- to circuit pack 100-1 until the source of this bus fault condition is detected.
Repeated until 00-N. Fault indicator circuit 19
When 5 is working properly, terminals RA0 and
The signals sent to RB0 are not the same. Therefore, the presence of identical signals at terminals RA0 and RB0 indicates to bus diagnostic device 300 that fault indicator circuit 195 is not operating properly.

Bus diagnostic device 300 selects system operation for current sensing test mode and sends a logic 1 signal to terminals CA0 and CB0 of pack 100-0 and from terminal CA1 of packs 100-1 through 100-N.
The fault detection circuitry of circuit pack 100-0 can be tested by sending a logic zero signal up to CAN and from CB1 to CBN. A logic zero signal transmitted to circuit packs 100-1 through 100-N places the transmitters and receivers of those packs in a high impedance state. In circuit pack 100-0, when a logic 1 signal is received at terminals CA0 and CB0, inverter 151
A logic 0 signal is transmitted by the gate, and a logic 1 signal is transmitted by the OR gate 152. Therefore, OR gates 124 and 124'
01-1, 101-2, 101-3 and 101-
4 and receivers 102-1, 102-2, 102
A logic 0 signal is sent to the C terminals of -3 and 102-4 to place these devices in a low impedance state. As in the diagnostic mode, when a logic 1 signal appears at terminal CA0, relay contacts 181 and 182 open. Receiver 102-1, 102-
Since resistors 2, 102-3, and 102-4 are in a low impedance state, the current flowing between resistors 183 and 184 exceeds a predetermined magnitude and flip-flop 191 is set. As a result, OR gate 194 sends a logic 1 signal onto response bus 250 via terminal RA0, and OR gate 193 sends a logic 0 signal onto response bus 250 via terminal RB0. Other responses on response bus 250 are sent to bus diagnostic device 300 by circuit packs 100-
0 indicates that the fault detection circuit is not operating correctly. Circuit pack 100-0 to 100-N 1
includes only a transmitter, the bus diagnostic device 300
connects the logic signal sent by circuit 110 and bus 500 by first sending a logic 1 signal and then a logic 0 signal on bus 500.
It is also possible to cause a mismatch with the logic signal above, causing the pack's transmitter to draw a current greater than a predetermined magnitude.