JPH041066B2 - - Google Patents
Info
- Publication number
- JPH041066B2 JPH041066B2 JP12877886A JP12877886A JPH041066B2 JP H041066 B2 JPH041066 B2 JP H041066B2 JP 12877886 A JP12877886 A JP 12877886A JP 12877886 A JP12877886 A JP 12877886A JP H041066 B2 JPH041066 B2 JP H041066B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- sputtering
- etching
- oxide film
- bias voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004544 sputter deposition Methods 0.000 claims description 23
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 45
- 238000005530 etching Methods 0.000 description 22
- 238000003486 chemical etching Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
Description
【発明の詳細な説明】
利用産業分野
この発明は、薄膜磁気ヘツドの絶縁膜や保護膜
に使用されるAl2O3あるいはSiO2等酸化物をスパ
ツタリングにより被着させる方法に係り、特に、
Al2O3またはSiO2被膜をエツチングする際のサイ
ドエツチ部の発生を防止できる酸化物被膜の形成
方法に関する。[Detailed Description of the Invention] Field of Application This invention relates to a method of depositing oxides such as Al 2 O 3 or SiO 2 by sputtering, which are used for insulating films and protective films of thin-film magnetic heads.
The present invention relates to a method for forming an oxide film that can prevent side etching from occurring when etching an Al 2 O 3 or SiO 2 film.
背景技術
今日、磁気ヘツドは、オーデイオ用、VTR用
の各テープレコーダー、データーレコーダー、コ
ンピユーター用デイスク、ドラム等の磁気記憶再
生用として多用されており、さらに今後は、オー
デイオ用、VTR用の磁気記録媒体のメタルテー
プ化やPCM記録方式化、あるいはコンピユータ
ーの高速、高記録密度化が進められている。そこ
で、かかる要求に対処するため、従来の巻線型バ
ルクヘツドにかえて、ICテクノロジーを用い、
容易にマルチトラツク化、狭トラツク化でる薄膜
磁気ヘツドが最適と考えられている。BACKGROUND ART Today, magnetic heads are widely used for magnetic storage reproduction in audio and VTR tape recorders, data recorders, computer disks, drums, etc., and in the future, magnetic heads for audio and VTR use Progress is being made in the use of metal tape and PCM recording media, and in computers with higher speeds and higher recording densities. Therefore, in order to meet these demands, we used IC technology instead of the conventional wire-wound bulkhead.
A thin-film magnetic head that can easily be made into a multi-track or narrow-track head is considered to be optimal.
この薄膜磁気ヘツドの構造に不可欠である絶縁
膜や保護膜は、一般に、セラミツクス等の基板上
に、スパツタリング方法によりAl2O3またはSiO2
被膜（以下酸化物被膜という）を被着形成してい
る。 The insulating film and protective film that are essential to the structure of this thin-film magnetic head are generally made by sputtering Al 2 O 3 or SiO 2 onto a substrate such as ceramics.
A film (hereinafter referred to as oxide film) is deposited.
上記酸化物被膜を形成するための従来を高周波
スパツタリングは、酸化物被膜を形成中スパツタ
リング雰囲気や雰囲気ガス圧力等の作業条件を一
定に維持して行なつており、得られた酸化物被膜
は全方向に均質で、熱酸等でエツチングし、回路
パターンを形成すると、膜厚み方向及び平面方向
共に同じエツチング速度で浸蝕され、パターン形
成のためのマスクと酸化物被膜間に大きなサイド
エツチ部が形成される問題があつた。このサイド
エツチ部が大きくなると酸化物被膜上に形成され
る回路用パターン幅を広げる必要があり、高集積
化を妨げ、さらには、パターン部の被膜と酸化物
被膜との密着性並びに形状精度に悪影響を及ぼす
等の問題があつた。 The conventional high-frequency sputtering method for forming the oxide film described above is performed by maintaining constant working conditions such as the sputtering atmosphere and atmospheric gas pressure while forming the oxide film, and the resulting oxide film is When a circuit pattern is formed by etching with hot acid, etc., the etching is uniform in the direction, and is eroded at the same etching rate in both the film thickness direction and the planar direction, and a large side etched portion is formed between the mask for pattern formation and the oxide film. I had a problem. If this side etching becomes large, it is necessary to widen the width of the circuit pattern formed on the oxide film, which impedes high integration and has a negative impact on the adhesion between the pattern part film and the oxide film as well as shape accuracy. There were problems such as causing problems.
発明の目的
この発明は、セラミツクス等の基板上に、スパ
ツタリングによりAl2O3またはSiO2被膜を被着形
成した後、回路パターン形成のためのAl2O3また
はSiO2被膜のエツチングに際して、サイドエツ
チの発生を防止できる酸化物被膜の形成方法を目
的としている。Purpose of the Invention The present invention involves forming an Al 2 O 3 or SiO 2 film on a substrate such as ceramics by sputtering, and then performing side etching when etching the Al 2 O 3 or SiO 2 film for forming a circuit pattern. The objective is to provide a method for forming an oxide film that can prevent the occurrence of
発明の構成
すなわち、この発明は、スパツタリングにより
基板上にAl2O3またはSiO2被膜を形成する方法に
おいて、基板側に負のバイアス電圧を、スパツタ
リング時間と共に、200Vから0Vへ、連続的に減
少させながら印加することを特徴とする酸化物被
膜の形成方法である。Structure of the Invention That is, the present invention is a method for forming an Al 2 O 3 or SiO 2 film on a substrate by sputtering, in which a negative bias voltage on the substrate side is continuously decreased from 200 V to 0 V with the sputtering time. This is a method for forming an oxide film, characterized in that the voltage is applied while the oxide film is being applied.
発明の図面に基づく開示
第１図は熱酸によるエツチング速度と印加バイ
アス電圧との関係を現したグラフであり、第２図
はAl2O3被膜のパターンにおけるサイドエツチの
発生を示す断面説明図である。Disclosure of the Invention Based on Drawings Figure 1 is a graph showing the relationship between the etching rate by hot acid and the applied bias voltage, and Figure 2 is a cross-sectional explanatory diagram showing the occurrence of side etching in the pattern of the Al 2 O 3 film. be.
この発明は、前述したサイドエツチの発生を防
止するため、酸化物被膜のケミカルエツチング速
度とスパツタリング中に基板側に印加するバイア
ス電圧との関係を種々検討した結果、以下のスパ
ツタリング機構を知見し、完成したものである。 In order to prevent the occurrence of the side etch described above, this invention was developed by various studies on the relationship between the chemical etching rate of the oxide film and the bias voltage applied to the substrate side during sputtering, and the following sputtering mechanism was discovered and completed. This is what I did.
例えば、基板へのスパツタリングに際して、投
入電力5kw、スパツタAr圧２×10-2Torrの条件
にて、基板側に印加する負のバイアス電圧を0V、
50V、100V、150V、200Vに変化させると、50
℃、50％りん酸をエツチング液として用いたケミ
カルエチツチング処理時のエツチング速度は、
各々、100Å／min、150Å／min、200Å／min、
250Å／min、300Å／minに増加することが、第
１図より明らかである。 For example, when sputtering a substrate, the negative bias voltage applied to the substrate side is 0 V, under the conditions of input power of 5 kW and sputtering Ar pressure of 2 × 10 -2 Torr.
When changing to 50V, 100V, 150V, 200V, 50
The etching rate during chemical etching treatment using 50% phosphoric acid as the etching solution at
100Å/min, 150Å/min, 200Å/min, respectively.
It is clear from FIG. 1 that the rate increases to 250 Å/min and 300 Å/min.
この基板側に印加する負のバイアス電圧の違い
によるエツチング速度の変化は、スパツタリング
の際に、負のバイアス電圧を高くすると、スパツ
タリング雰囲気ガスとして導入されるArガスが、
被膜のAl2O3またはSiO2膜中に含まれ、その量が
多くなるため、ケミカルエツチング時の速度が早
くなると考えられ、かつ膜硬度も低下することが
確認されている。 The change in etching speed due to the difference in the negative bias voltage applied to the substrate side is explained by the fact that when the negative bias voltage is increased during sputtering, the Ar gas introduced as the sputtering atmosphere gas increases.
Since it is contained in the Al 2 O 3 or SiO 2 film of the coating, and its amount increases, it is thought that the speed during chemical etching becomes faster, and it has been confirmed that the film hardness also decreases.
ところが、該バイアス電圧を特定範囲におい
て、スパツタリング時間とともに連続的に減少さ
せることにより、形成される酸化物被膜は、その
エツチング時のケミカルツチング速度が、被膜表
面では小さく、膜厚み方向、すなわち、エツチン
グ深さ方向に順次増大する性質を有するため、エ
ツチング時、マスクと酸化物被膜間に進行するサ
イドエツチ部は、従来のスパツタリング法にて形
成された場合に比較して、大きく減少するのであ
る。 However, by continuously decreasing the bias voltage in a specific range with the sputtering time, the chemical etching rate of the formed oxide film during etching is low on the film surface, and the chemical etching rate is low in the film thickness direction, that is, Since the etching depth increases gradually in the direction of the etching depth, the side etching that develops between the mask and the oxide film during etching is greatly reduced compared to when it is formed by the conventional sputtering method.
すなわち、この発明方法によるAl2O3、SiO2の
酸化物被膜は、従来方法に比較して、サイドエツ
チ部相当幅だけ、マスク幅を小さくすることがで
き、回路パターンの高集積化が可能であり、酸化
物被膜のパターン部への被膜の密着性、形状精度
が向上すると共に、酸化被膜表面の結晶状態が完
全状態に近く、耐摩耗性、強度、耐侯性の改善が
著しいという利点がある。 In other words, compared to the conventional method, the Al 2 O 3 and SiO 2 oxide film formed by the method of this invention can reduce the mask width by the width equivalent to the side etched portion, making it possible to increase the integration of circuit patterns. This has the advantage that the adhesion of the oxide film to the pattern part and shape accuracy are improved, and the crystalline state of the oxide film surface is close to perfect, resulting in significant improvements in wear resistance, strength, and weather resistance. .
この発明方法において、基板側に印加する負の
バイアス電圧の連続的な減少範囲を、−200V〜
0Vに限定した理由は、−200V未満になると、被
膜の内部応力が大きくなりすぎ、また、0Vを越
えると、ステツプカバレージが悪くなり、被膜形
成後、薄膜ヘツド内の各素子との硬度、密着性に
おける整合性が悪くなるためである。 In the method of this invention, the range of continuous decrease of the negative bias voltage applied to the substrate side is set from −200V to
The reason for limiting the voltage to 0V is that if it is less than -200V, the internal stress of the film becomes too large, and if it exceeds 0V, the step coverage deteriorates, and after the film is formed, the hardness and adhesion with each element in the thin film head will deteriorate. This is because the consistency in gender deteriorates.
また、この発明において、スパツタリング中に
変化させるバイアス電圧範囲やその減少速度等
は、酸化物被膜に形成する回路用マスク幅や被膜
厚み、エツチング条件、さらにステツプカバレー
ジ、各素子との適合適合性、密着性に応じて適宜
選定すればよい。 In addition, in this invention, the bias voltage range to be changed during sputtering, its rate of decrease, etc. are determined by the width of the circuit mask formed on the oxide film, the film thickness, etching conditions, step coverage, compatibility with each element, etc. What is necessary is just to select suitably according to adhesiveness.
実施例
基板に純度99.5％のAl2O3−TiC系セラミツク
を使用し、ターゲツトとし純度99.9％のAl2O3を
使用し、投入電力5kw、スパツターAr圧力２×
10-2Torr、の条件で3.5時間のスパツタリングを
行なつた。Example The substrate was Al 2 O 3 -TiC ceramic with a purity of 99.5%, the target was Al 2 O 3 with a purity of 99.9%, the input power was 5 kW, and the sputtering Ar pressure was 2×.
Sputtering was performed for 3.5 hours under the condition of 10 -2 Torr.
この時のスパツタリング条件は、負のバイアス
電圧を最初−200Vであり、斬時連続的に0Vまで
減少させた。 The sputtering conditions at this time were that the negative bias voltage was initially -200V and was continuously decreased to 0V.
上記スパツタリング条件により、基板上に10μ
ｍ厚みのAl2O3被膜を形成した。その後、前記
Al2O3被膜上に幅50μｍの回路パターン用のマス
クを配設した。 Under the above sputtering conditions, 10μ
An Al 2 O 3 film with a thickness of m was formed. Then said
A mask for a circuit pattern with a width of 50 μm was placed on the Al 2 O 3 film.
また、比較のため、上記のスパツタリング条件
で、かつ負のバイアス電圧を−150Vの一定に保
持する従来方法で、基板上に10μｍ厚みのAl2O3
被膜を形成し、同様のマスクを配設した。 For comparison, a 10 μm thick Al 2 O 3 film was deposited on the substrate under the above sputtering conditions and using the conventional method of keeping the negative bias voltage constant at −150 V.
A coating was applied and a similar mask was placed.
次に、第２図に示す如く、Al2O3被膜２マスク
３を形成した基板１に、50℃に加熱した50wt％
の燐酸を使用してAl2O3被膜の回路パターンを形
成し、エツチング時に発生したサイドエツチ部４
の幅を測定した。 Next, as shown in FIG .
The circuit pattern of the Al 2 O 3 film was formed using phosphoric acid, and the side etches 4 generated during etching were
The width was measured.
従来方法により形成したAl2O3被膜の場合、発
生したサイドエツチ部の幅（ｗ）は12μｍであつ
たが、この発明の形成方法によるAl2O3被膜の場
合、サイドエツチ部の幅（w′）は7μｍであり、
サイドエツチ部が小さく、Al2O3被膜のパターン
形成に極めて有利なことが分る。 In the case of the Al 2 O 3 film formed by the conventional method, the width (w) of the side etched portion was 12 μm, but in the case of the Al 2 O 3 film formed by the forming method of the present invention, the width (w′) of the side etched portion was 12 μm. ) is 7μm,
It can be seen that the side etches are small, which is extremely advantageous for patterning the Al 2 O 3 film.
第１図は熱酸によるエツチング速度と印加バイ
アス電圧との関係を現したグラフであり、第２図
はAl2O3被膜のパターンにおけるサイドエツチの
発生を示す断面説明図である。
１……基板、２……Al2O3被膜、３……マス
ク、４……サイドエツチ部。
FIG. 1 is a graph showing the relationship between the etching rate by hot acid and the applied bias voltage, and FIG. 2 is a cross-sectional view showing the occurrence of side etching in the pattern of the Al 2 O 3 film. 1... Substrate, 2... Al 2 O 3 coating, 3... Mask, 4... Side etched portion.
Claims (1)
SiO2被膜を形成する方法において、基板側に負
のバイアス電圧を、スパツタリング時間と共に、
200Vから0Vへ、連続的に減少させながら印加す
ることを特徴とする酸化物被膜の形成方法。1 Sputtering Al 2 O 3 or
In the method of forming a SiO 2 film, a negative bias voltage is applied to the substrate side, and the sputtering time is
A method for forming an oxide film, characterized in that the voltage is applied while decreasing continuously from 200V to 0V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12877886A JPS62284067A (en) | 1986-06-02 | 1986-06-02 | Formation of oxide film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12877886A JPS62284067A (en) | 1986-06-02 | 1986-06-02 | Formation of oxide film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62284067A JPS62284067A (en) | 1987-12-09 |
| JPH041066B2 true JPH041066B2 (en) | 1992-01-09 |
Family
ID=14993231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12877886A Granted JPS62284067A (en) | 1986-06-02 | 1986-06-02 | Formation of oxide film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62284067A (en) |
-
1986
- 1986-06-02 JP JP12877886A patent/JPS62284067A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62284067A (en) | 1987-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0827925B2 (en) | Magnetic head slider having protective coating and method of manufacturing the same | |
| JPH07105004B2 (en) | Manufacturing method of thin film magnetic head | |
| US4481071A (en) | Process of lift off of material | |
| US5316617A (en) | Thin film magnetic head and method of manufacturing the same | |
| JPH041066B2 (en) | ||
| EP0493902B1 (en) | Magnetic head slider and method for making same | |
| JPS6329311A (en) | Thin film magnetic head for perpendicular magnetic recording and manufacture | |
| JP2702215B2 (en) | Method for manufacturing thin-film magnetic head | |
| US4752344A (en) | Magnetic layer and method of manufacture | |
| JPS58100212A (en) | Thin-film magnetic head | |
| JP2751696B2 (en) | Method for manufacturing thin-film magnetic head | |
| JP2613876B2 (en) | Method for manufacturing thin-film magnetic head | |
| JPH0422983B2 (en) | ||
| JPH0380410A (en) | Thin-film magnetic head and production thereof | |
| JPH07331429A (en) | Thin film formation method | |
| JP2875445B2 (en) | Magnetoresistive head | |
| JPH0283811A (en) | Manufacturing method of thin film magnetic head | |
| JP2605535B2 (en) | Method for manufacturing thin-film magnetic head | |
| JP2735967B2 (en) | Manufacturing method of floating magnetic head | |
| JPH103613A (en) | Thin film magnetic head and method of manufacturing the same | |
| JPH09138910A (en) | Method of patterning a metal layer | |
| JPH02247808A (en) | Thin film magnetic head and its production | |
| JPH01128215A (en) | Thin film magnetic head and its manufacture | |
| JPH0370848B2 (en) | ||
| JPH066796B2 (en) | Processing method of ferrite single crystal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |