JPH0410744B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor integrated circuit device having a three-dimensional active layer stacked structure, and improves the reliability of device functional tests by adding a redundant circuit. The present invention relates to a semiconductor integrated circuit element having an element structure that can be used.

<Prior art> As we develop semiconductor integrated circuit devices, we conduct functional tests on the devices manufactured. In recent years, semiconductor integrated circuit devices to which a simple functional test circuit has been added have been studied in order to shorten the test time.

<Problem to be solved by the invention> Even if there is no problem with the original function of the element in a functional test, if a defect occurs in the test circuit for testing the function, the element may be untestable. Since it is considered to be defective, it becomes necessary to directly perform a functional test of the element. If the above-mentioned case occurs frequently, the test circuit added to shorten the test time becomes meaningless.

Furthermore, since the area of the element itself is limited, it is impossible to add a test circuit large enough to test all the functions of the element. Therefore, substantial reduction in test time cannot be expected.

<Means for Solving the Problems> In view of the above points, the present invention provides an SOI (Silicon On Insulator) structure in which multiple active layers are formed on a semiconductor integrated circuit two-dimensionally fabricated on a conventional single crystal silicon substrate. A semiconductor integrated circuit device with a realized three-dimensional structure is provided, and a test circuit, a test circuit, and a redundant circuit of the semiconductor integrated circuit device are added to a functional layer on a single crystal silicon substrate or an active layer formed with an SOI structure thereon. As a result, a semiconductor integrated circuit device is provided which has a device testing function using the device's original area without being restricted by the device area. Unlike the conventional method, the added test circuit can be added in an appropriate scale, and since the test circuit has a redundant configuration, it is possible to provide a semiconductor integrated circuit that can perform substantial and highly reliable testing.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram of an embodiment of the present invention, and is a conceptual diagram of a structure realized by a two-layer active layer of an SOI (Silicon On Insulator) structure in a semiconductor integrated circuit element to which a test circuit for an element having a redundant circuit is added. It is.

In Figure 1, each active layer (active layers 1 and 2) has a MOS transistor, that is, PMOS or NMOS.
Alternatively, a CMOS transistor is formed. The active layer 1 is a first active layer formed on a single crystal silicon substrate, and the active layer 2 is a polycrystalline layer formed by beam irradiation on an insulating layer that electrically insulates the first active layer 1. This is a second active layer obtained by melt-growing silicon. The signal line wiring between the active layer 1 and the active layer 2 is connected through a through hole. Here, only the original functional section 3 of the semiconductor integrated circuit element, its input/output section 4, and input/output signal lines from a test circuit for testing the element are arranged in the active layer 1. Further, in the active layer 2, an input/output signal line terminal 5 inherent to the element, a test circuit 6 for the element, an input/output section 7 for the test circuit, and a redundant circuit 8 for the test circuit are arranged.

Since the test circuit is arranged in the active layer 2, there is plenty of space, and it is possible to design it to satisfy not only a simple test of the element but also a test of all functions. Also, since it has redundant circuits, highly reliable tests can be performed.

FIG. 2 is a circuit diagram of another embodiment of the test circuit according to the present invention. The redundant test circuit is implemented using a three-layer active layer SOI structure. This circuit is part of a test circuit that performs capacitance division to measure the cell capacitance of a memory cell of a dynamic semiconductor memory element. ) forms the functional circuit of the dynamic semiconductor memory element.

The active layer 11 is a first active layer formed on a single-crystal silicon substrate, and the active layer 12 is a polycrystalline layer formed on the top of an insulating layer that electrically insulates the first active layer 11 by beam irradiation. The second active layer is obtained by melting and growing silicon, and similarly, the active layer 13 is
This is a third active layer formed on the active layer 12 using an SOI structure. Wiring between the active layer 11 and the active layer 12 or between the active layer 12 and the active layer 13 is connected by a through hole.

The structure of the device of the embodiment shown in FIG. 2 is different from the conceptual diagram of the embodiment shown in FIG. Since the test circuit has not only the test circuit but also the original function of the element, the test circuit that performs this capacitance division is arranged including a redundant circuit in each active layer.

Here, this test circuit consists of a test circuit 1 consisting of three transistors surrounded by broken lines in FIG.
4 are arranged in three rows in each active layer. The test circuit consisting of three transistors shown in FIG. 2 has nine active layers of three layers, and any one of them can serve as the test circuit. In other words, one of the nine sets of test circuits is the original test circuit, and the remaining eight are redundant circuits of the test circuits for realizing a highly reliable test. The redundant circuit is a redundant circuit in which the fuse 1 arranged in the active layer 3 is used in case of a defective transistor in each test circuit or a defective wiring connection due to a through hole.
5, the defective test circuit is separated and repaired. Three sets of test circuits consisting of three transistors are arranged in each active layer. In layer 3, each of the three single crystal regions is divided into three separate regions, that is, three active regions, and test circuits are distributed to ensure reliability.

Here, a case in which it is impossible to repair a defect in a test circuit having a redundant circuit as shown in FIG. 2 will be briefly described.

When all the through holes used for interlayer wiring are disconnected (open).

If even one of the three transistors in all nine test circuits is disconnected (open).

In all 9 sets of test circuits, if even one of the three transistors is short-circuited between the gate and source, between the gate and drain, or between the source and drain.

In the above case, it is impossible to repair the defect, but in other words, it is a case where all the test circuits having nine sets of redundant circuits are defective.

Therefore, as long as the through hole for interlayer coupling does not short-circuit with any wiring layer between the layers, it is possible to repair with a high probability.

<Effects of the Invention> As described above, the semiconductor integrated circuit element of the present invention has the following effects:
A first active layer formed on a single crystal silicon substrate and a second active layer obtained by melting and growing polycrystalline silicon by beam irradiation on an insulating layer that electrically insulates the first active layer. A semiconductor integrated circuit device having a laminated structure of active layers, each active layer comprising a single crystal active element region having an arbitrary width within each layer and an element isolation region insulating this region at an arbitrary interval, It is possible to add a test circuit to the device without increasing the area of the device, and the test circuit can also be added on a reasonable scale, rather than a simple one unlike in the past.Furthermore, it is possible to add a redundant circuit to the test circuit. By having this, it is possible to test highly reliable devices, and in particular, high reliability and a substantial reduction in test time can be achieved for large-capacity, multi-functional semiconductor integrated circuit devices that have a multi-active layer stacked structure. .

[Brief explanation of drawings]

Figure 1 shows an SOI (Silicon On
Fig. 2 is a conceptual diagram of a three-dimensional semiconductor integrated circuit element realized by a two-layer active layer laminated structure using an insulator structure, and shows a part of a test circuit and its redundant circuit in an embodiment of the present invention. It is a circuit diagram. Explanation of symbols, 1, 2: active layer, 3: functional section,
4: Input/output section, 5: Input/output terminal, 6: Test circuit, 7: Test circuit input/output section, 8: Redundant circuit for test circuit, 11, 12, 13: Active layer, 14: Test circuit, 15: Fuse .

Claims (1)

[Claims] 1 A first active layer formed on a single crystal silicon substrate and a first active layer obtained by melting and growing polycrystalline silicon by beam irradiation on top of an insulating layer that electrically insulates the first active layer. The active layer has a laminated structure of two active layers, and each active layer is composed of a single crystal active element region having an arbitrary width within each layer and an element isolation region insulating the region at an arbitrary interval. The element area is PMOS or NMOS or
A three-dimensional active layer laminated structure semiconductor integrated circuit element comprising a CMOSFET and having a through hole vertically connecting the active layers, the first
Alternatively, a semiconductor integrated circuit device characterized in that a test circuit is redundantly built in the second or each of the first and second active layers.