JPH0411077B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a communication path continuity test method for confirming the normality of a digital communication path in a time-division digital exchange or the like.

[Background of the invention]

As a conventional communication line continuity test method for digital communication lines, Japanese Patent Application Laid-open No. 1983-66453 (Japanese Patent Application No. 1983-1983)
164248), a specific test signal pattern and a complement test signal pattern that is a complement function of the test signal pattern are transmitted, received via a digital channel, and the received signal pattern is transmitted. There is a method that determines whether or not the test signal pattern and complement test signal pattern are the same.

However, in such conventional communication path continuity testing methods, synchronization is achieved according to the phase delay in the time switches and spatial switches that make up the digital communication path, and then the transmitted test signal pattern (complement test signal pattern) and It is necessary to match the received signal pattern. Therefore, there was a drawback in that the phase delay had to be calculated depending on how the bus for the digital communication path was selected.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to make it possible to determine the normality of a digital communication path by simply inspecting the received signal pattern, without having to consider the phase delay occurring within the digital communication path. The object of the present invention is to provide a possible communication line continuity test method.

[Summary of the invention]

The communication line continuity test method of the present invention alternately generates test signal patterns having a complementary relationship with each other at predetermined intervals, and generates test signal patterns that do not follow the alternating rule at predetermined intervals to test the time-division communication line. The signal of a specific channel is extracted from the outgoing highway of the time-division communication path, and the extracted signal is a test signal pattern that has a complement relationship alternately at each predetermined period, and which has an alternating rule at each predetermined period. By detecting the existence of a test signal pattern that does not comply with the test signal pattern and further detecting that the test signal pattern at a specific position is a predetermined test signal pattern,
It is characterized by determining the normality of the time-division communication path.

[Embodiments of the invention]

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a diagram showing an example of a digital communication path whose normality is tested according to the present invention, in which a test signal pattern generation circuit 1 and a test signal pattern inspection circuit 2 are provided in a digital communication path 3.

FIG. 2 is a diagram showing an embodiment of the test signal pattern generation circuit. As shown in the figure, there is a counter circuit 101 that counts clock pulses 111 with a frequency of 8 MHz and outputs a test signal pattern 5 of "01010101" and its control signal, and a test signal pattern of "10101010" that has a complementary relationship with the test signal pattern described above. A pattern alternating generation circuit 102 generates test signal pattern A, outputs test signal pattern 5 and A alternately, and further generates test signal pattern A at the timing when test signal pattern 5 should be generated only once every eight times. ing. FIG. 3 shows the test signal pattern output from the pattern alternation generating circuit 102. Third
As shown in the figure, the pattern alternate generation circuit 102 is
Except for the first frame, test signal patterns A and 5, which are complementary to each other, are alternately output.

FIG. 4 is a diagram showing an embodiment of the test signal pattern inspection circuit shown in FIG. 1. In the same figure,
Test pattern signals A and 5 shown in FIG. 3 are input as received signal patterns to the received signal input terminal 211 via a digital communication path. The received signal pattern is converted into a parallel signal by a serial-to-parallel conversion circuit 201, and a signal holding circuit 202 and a complement arithmetic coefficient detection circuit 20
3 is input to the pattern detection circuit 204 and the seventh frame content detection circuit 205. The complement relationship detection circuit 203 compares the contents of the signal holding circuit 202 and the output of the serial/parallel conversion circuit, and determines the test signal pattern A, 5.
It detects that are being output alternately, and outputs logic "1" to the frame number detection circuit 206. The pattern detection circuit 204 determines whether the received signal pattern is the test signal pattern A or 5, and its output is input to the frame number detection circuit 206.
The frame number detection circuit 206 receives the output of the complement relationship detection circuit 206 and the output of the pattern detection circuit 204, and detects that the received signal pattern alternates between patterns A and 5 for each frame, and each bit in the frame is set to "0" mutually. , "1", the counter C is counted up and each bit becomes "0",
If the received signal does not alternate in patterns A and 5 for each frame even if it alternates with "1", a value of "2" is loaded into the counter C.

As shown in Figure 3, test patterns A and 5 do not alternate in the first frame at the start of reception;
When test pattern A of the first frame is received, a value of 2 is loaded into counter C, and counter C is initialized. Subsequently, when the second and third frames are received, the counter C counts up, and the value obtained by subtracting 1 from that value represents the frame number.

In the frame number detection circuit 206, when the detection of the first multi-frame is completed and the count value of the counter C becomes "1" and the th frame is detected, a logic "1" is input to the gate circuit 208. Therefore, the received signal pattern of the first frame is inverted from pattern A to pattern 5 and input. As a result, the received signal becomes a complete alternating signal of test signal patterns A and 5, and by detecting this in the complement relationship detection circuit 203, the normality of the digital communication path can basically be confirmed.

The seventh frame content detection circuit 205 receives a signal indicating the seventh frame reception timing from the frame number detection circuit 206, and determines whether the content of the seventh frame is test signal pattern A or test signal pattern 5 at that timing. This is because even if the received signal is confirmed to be a complete alternation of test patterns A and 5 through the above processing,
It is also possible that the police box is "5A5A...5A" instead of "A5A5...A5". In the latter case, it cannot be determined to be normal, so the seventh frame content detection circuit 205 confirms that the content of the seventh frame is 5.

Therefore, the complement relation detection circuit 203 confirms that each frame is an alternation of test patterns A and 5, and the pattern detection circuit 204 confirms that the content of each frame is a test pattern A or 5. The confirmation is detected as the output of the AND circuit A in the frame number detection circuit 206. Furthermore, by inputting the output of the seventh frame content detection circuit 205 and the output of the AND circuit A to the AND circuit 207 and taking the AND condition of both, the normality of the digital communication path can be confirmed accurately.

〔Effect of the invention〕

According to the present invention, it is possible to determine the normality of a digital communication path by simply inspecting the pattern of the received signal without having to consider the phase delay in the digital communication path.

[Brief explanation of drawings]

Figure 1 is a diagram of the continuity test configuration of a digital communication path.
2 is a diagram showing an example of the test signal pattern generation circuit shown in FIG. 1, FIG. 3 is a diagram showing an example of the test signal pattern, and FIG. 4 is a diagram showing an example of the test signal pattern inspection circuit. It is a diagram. DESCRIPTION OF SYMBOLS 1...Test signal pattern generation circuit, 2...Test signal pattern inspection circuit, 3...Digital communication path, 201...Serial to parallel conversion circuit, 202...Signal holding circuit, 203...Complement relationship detection circuit, 204
... pattern detection circuit, 205 ... seventh frame content detection circuit, 206 ... frame number detection circuit.

Claims (1)

[Claims] 1. Test signal patterns that are mutually complementary are generated alternately at predetermined intervals, and test signal patterns that do not follow the alternating rule are generated at predetermined intervals, and are inserted into the incoming highway of the time-division communication path, and the time-division communication The signal of a specific channel is extracted from the outgoing highway of the communication path, and the extracted signal is a test signal pattern that has a complementary relationship alternately at each predetermined period, and there is a test signal pattern that does not follow the alternating rule at each predetermined period. 1. A communication path continuity test method, characterized in that the normality of a time-division communication path is determined by detecting that the test signal pattern at a specific position is a predetermined test signal pattern.