JPH0412645B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level shift circuit composed of FETs.

In a linear circuit composed of MOSFETs,
Level shifting circuits are often required to move the DC potential of the input signal into the input voltage range in which the circuit will operate. A typical example is when a common source circuit is used. In general, the input voltage range in which a common source circuit operates is extremely narrow, and the DC potential of the signal to be input is often not within that range. In this case, it is often done that the input signal is once passed through a level shift circuit, its DC potential is moved to a range where the source grounded circuit operates, and then applied to the source grounded circuit.
Such a level shift circuit is required to have a sufficiently small output resistance in order to minimize deterioration of frequency characteristics due to its placement.

Conventionally, source follower circuits have been widely used as level shift circuits. An example is shown in FIG.

In FIG. 1, the drain electrode of MOSFET 1 is connected to the first power supply 5, and the gate electrode is connected to the input terminal 3.
The source electrode is connected to the output terminal 4. Further, the drain electrode of the MOSFET 2 is connected to the output terminal 4, the gate electrode is connected to a power source 7 that provides a bias potential, and the source electrode is connected to a second power source 6. The signal applied to input terminal 3 is the gain coefficient of MOSFETs 1 and 2 and the MOSFET
The potential is shifted by an amount approximately determined by the bias potential of the gate electrode 2 and appears at the output terminal 4.

The transconductance of MOSFET1 is gm1
Then, the output resistance of the level shift circuit shown in FIG. 1 is approximately 1/gm1. However, transconductance gm1 is determined by the magnitude of potential shift and current consumption.

Therefore, when trying to use the conventional circuit shown in Figure 1 as a particularly wide-band circuit, the circuit bandwidth is inversely proportional to the output resistance, so the conventional level shift circuit, which cannot reduce the output resistance sufficiently, will In practice, it is often the case that bandwidth is not available.

In view of this point, the present invention aims to provide a level shift circuit whose output resistance is much smaller than that of conventional circuits.

The level shift circuit according to the present invention includes a first circuit having a drain electrode connected to a first power supply, a gate electrode connected to an input terminal, and a source electrode connected to a connection point.
EFT, the drain electrode is connected to the connection point, the source electrode is connected to the second power source, and the gate electrode is connected to the third power source.
a second FET connected to a power source, and a third FET whose drain electrode is connected to the first power source, whose gate electrode is connected to a fourth power source, and whose source electrode is connected to the output terminal.
and a fourth EFT whose drain electrode is connected to the output terminal and whose source electrode is connected to the second power supply.
The fourth EFT is configured to include an EFT and a circuit that adds the potential change at the connection point and the potential change at the output terminal and applies the sum to the gate electrode of the fourth EFT.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention. A drain electrode of the MOSFET 11 is connected to a first power supply 19 , a gate electrode is connected to an input terminal 16 , and a source electrode is connected to a connection point 18 . The drain electrode of MOSFET 12 is the connection point 18
The gate electrode is connected to a power supply 21 that provides a bias potential, and the source electrode is connected to a second power supply 21.
Connected to 0. A drain electrode of the MOSFET 13 is connected to a first power source 19, a gate electrode is connected to a power source 22 that provides a bias potential, and a source electrode is connected to an output terminal 17.
The drain electrode of the MOSFET 14 is connected to the output terminal 17, and the source electrode is connected to the second power supply 20. Reference numeral 15 denotes an analog addition circuit that adds the potential changes at the output terminal 17 and the connection point 18 and applies the result to the gate electrode of the MOSFET 14. All FETs used in Figure 2 are of the same conductivity type.

Next, the operation of the circuit shown in FIG. 2 will be explained.
MOSFETs 11 and 12 constitute a source follower circuit similar to the circuit shown in FIG. The signal applied to input terminal 16 undergoes a potential shift by an amount determined by the gain coefficients of MOSFETs 11 and 12 and the bias potential of the gate electrode of MOSFET 12, and appears at connection point 18. On the other hand, MOSFETs 13 and 14 constitute an inverter circuit, and the gain is
It is approximately determined by the ratio of the transconductances of 13 and 14. When this gain is sufficiently large and the gain of the analog adder circuit 15 is near or above 1, the MOSFET 1 is connected to the output terminal 17.
Due to negative feedback to the gate electrode of MOSFET 1
Changes in the potential of the gate electrode No. 4 are always kept small. Therefore, the sum of the potential change at the connection point 18 and the potential change at the output terminal 17 becomes approximately zero. As a result, a potential change appears at the output terminal 17 which is approximately the same magnitude as the potential change at the connection point 18 and whose transfer is opposite. That is, since the output terminal 17 obtains a potential change that is approximately the same magnitude and opposite in phase to the signal applied to the input terminal 16, this circuit operates as a level shift circuit. The magnitude of the potential shift in this circuit is determined by the current flowing through MOSFETs 11 and 12.
MOSFET13 gate-source voltage (VGS)
It is also determined by the bias potential of the power supply 22.

Next, the output resistance of the circuit shown in FIG. 2 will be considered in comparison with the circuit shown in FIG. Output resistance is the ratio of the change in potential applied to the output terminal when the input signal is set to zero and the amount of change in output current caused by the change. In Figure 1, the change in current that occurs when a potential change is applied to output terminal 4 is mostly due to the change in the current flowing through MOSFET 1, and therefore the output resistance is approximately 1/gm1 as described above. Become. On the other hand, in the circuit shown in FIG. 2, when a potential change is applied to the output terminal, in addition to the change in the current flowing through the MOSFET 13, the current changes through the analog adder circuit 15.
There is a change in the current flowing through MOSFET 14 due to a change in the gate potential of MOSFET 14, and the latter is usually much larger. Therefore, the second
The output resistance of the circuit shown in the figure is approximately 1/(A·gm14). However, A is the gain of the feedback circuit 15,
gm14 is the transconductance of MOSFET14. Now, it is well known that the transconductance gm of a MOSFET in the saturation region is approximately expressed by the following equation.

gm=2×IDS/(VGS−VT) ………(1) Here, IDS, VGS, and VT are the drain and
These are source current, gate-source voltage, and threshold voltage. In Figure 1, once the magnitude of the potential shift and current consumption are determined, the gate-source voltage VGS and drain-source current IDS of MOSFET1 are determined, so gm1 is also determined. can be seen from equation (1). On the other hand, the second
In the circuit shown in the figure, the magnitude of the potential shift is
Since it does not depend on the MOSFET14 gate-source voltage (VGS), the MOSFET14 drain and
Even under the condition that the source-to-source current IDS is constant,
By bringing the potential of the gate electrode of the MOSFET 14 closer to the second power supply, the gate-source voltage VGS of the MOSFET 14 can be brought closer to the threshold voltage VT as much as possible without changing the magnitude of potential shift. Therefore, according to formula (1), in principle
It turns out that gm14 can be made as large as desired.

Therefore, once the magnitude of the potential shift and the current consumption are determined, A·gm14 can generally be made much larger than gm1, and the circuit of FIG. 2 is much larger than the circuit of FIG. Small output resistance can be obtained.

FIG. 3 shows an embodiment in which the circuit shown in FIG. 2 is further embodied.

The depletion type MOSFETs 30 and 31 are selected to have the same electrical characteristics, and the operating point potentials of the output terminal 17 and the connection point 18 are set to be equal. Since the sum of the currents flowing through MOSFETs 30 and 31 does not change in response to an opposite potential change that occurs at the output terminal 17 and the connection point 18, the MOSFET
The potential of the gate electrode 37 of No. 14 does not change. For potential changes in the same direction that occur at the output terminal 17 and the connection point 18, MOSFETs 30 and 31
Together with the MOSFET 32, it functions as a source follower circuit, and transmits potential changes to the gate electrode 37 of the MOSFET 14 with a gain of approximately 1. Therefore MOSFET3
The circuit consisting of 0, 31, and 32 realizes the analog adder circuit 15 of FIG.

The depletion type MOSFET 33 and the enhancement type MOSFET 34 are the MOSFET 12 and the enhancement type MOSFET 34.
A bias potential is applied to the gate electrode of MOSFET 32. Similarly, depletion type MOSFET3
5 and enhancement type MOSFET36 are
It functions as a power supply that applies a bias potential to the gate electrode of MOSFET 13. As described above, the circuit shown in FIG. 3 is an example of the circuit shown in FIG. 2.

As described above, according to the present invention, it is possible to obtain a level shift circuit with a much smaller output resistance than the conventional one. Therefore, the present invention
It can greatly contribute to widening the bandwidth of linear circuits in MOSFET integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional level shift circuit (source follower circuit), FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an embodiment that further embodies FIG. 2. It is a diagram. 1, 2, 11, 12, 13, 14, 30, 3
1, 32, 33, 34, 35, 36...
MOSFET, 3, 16...Input terminal, 4, 17...
...Output terminal, 5, 6, 19, 20...Power supply, 7,
21, 22...power supply that provides bias potential, 15
...Analog addition circuit, 18...Connection point.

Claims (1)

[Claims] 1 A first FET with a drain electrode connected to a first power source, a gate electrode connected to an input terminal, and a source electrode connected to a connection point, and a first FET with a drain electrode connected to the connection point and a source electrode connected to a second power source. a second FET with a gate electrode connected to a third power source; and a third FET with a drain electrode connected to the first power source, a gate electrode connected to a fourth power source, and a source electrode connected to an output terminal. FET, a fourth FET whose drain electrode is connected to the output terminal and whose source electrode is connected to the second power supply, and the fourth FET which combines the potential change at the connection point and the potential change at the output terminal
A level shift circuit comprising: a circuit for applying voltage to the gate electrode of the FET;