JPH0412672B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a horizontal synchronization pulse generation circuit for extracting horizontal synchronization pulses from a composite synchronization signal containing equivalent pulses, for example in a video tape recorder.

[Technical background of the invention]

Traditionally, composite sync signals (horizontal, vertical sync pulses,
When separating and extracting horizontal synchronizing pulses from (including equivalent pulses), a circuit in which two mono-multivibrators are connected in series is used. When the time constant of the first mono-multivibrator is set to approximately 3/4H (H; horizontal scanning period), when the composite synchronization signal shown in Fig. 1a is input, the capacitor terminal as shown in Fig. 1b A voltage can be generated and an output as shown in FIG. 1e can be obtained. In other words, the period is 1H
A wide pulse synchronized with the rise of the composite synchronization signal is obtained. By inputting this to a second mono-multivibrator with a small time constant, it is possible to obtain a horizontal synchronizing pulse from which the equivalent pulse has been removed, as shown in FIG. 1d.

[Problems with background technology]

However, according to the above-mentioned conventional horizontal synchronization pulse generation circuit, two mono-multivibrators are used, but a capacitor and a resistor are used to determine the time constants of each. Therefore, if such a horizontal synchronizing pulse generation circuit is to be integrated into an integrated circuit, the capacitor and resistor become external elements, and therefore two pins are required.
When implementing an integrated circuit into an IC, it is desired that the number of pins be small, and a reduction in the number of pins is also desired for the horizontal synchronization pulse generation circuit.

[Purpose of the invention]

This invention was made in view of the above circumstances, and is effective in reducing the number of pins by eliminating equivalent pulses by using only a time constant circuit of one resistor and capacitor.Moreover, the pulse width is also accurate. It is an object of the present invention to provide a horizontal synchronization pulse generation circuit that can determine horizontal synchronization pulses.

[Summary of the invention]

In this invention, as shown in FIG. 2, a flip-flop circuit 1 is used to generate a mask pulse for an AND circuit 13 to which a horizontal synchronizing signal is applied.
2, oscillator 14, frequency divider 15, 16, logic circuit 1
The above object is achieved by forming 7 loops and setting the mask period by a digital count value.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which reference numeral 11 denotes a composite synchronizing signal input terminal, which is connected to the clock input terminal of the D-type flip-flop circuit 12 and to the first input terminal of the AND circuit 13. It is connected. High level data D1 is applied to the data input terminal D of the D type flip-flop circuit 12. The output terminal Q ₀ of the D-type flip-flop circuit 12 is applied to a control terminal 141 for controlling the operation and stop of the oscillator 14, and the inverted output terminal ₀ is applied to the first and second flip-flop circuits. It is connected to the set input terminals 15 and 16. The oscillator 14 is connected to the control terminal 14
When the control signal applied to 1 is high level, the oscillation operation is performed, and when the control signal is low level, the oscillation operation is stopped. Further, the flip-flop circuit 15,
16 is the D type flip-flop circuit 12.
When the inverted output ₀ is at a high level, it is set, and when it is at a low level, it is unset and operates as a frequency divider.

The oscillator 14 can obtain two types of output signals, and from the first output terminal 142,
A mask pulse is output, and this is applied to the AND circuit 1.
In addition to the second input terminal of No. 3, an oscillation output is obtained from the second output terminal 143, which is applied to the frequency dividing input terminal of the flip-flop circuit 15 and also to the third input terminal of the NOR circuit 17. Added. NOR circuit 17 is D type flip-flop circuit 1
2, and the divided outputs of the flip-flop circuits 16 and 15 are input to its first and second input terminals.

The synchronous pulse generation circuit of the present invention is configured as described above, and the time constant circuit of the resistor R ₁ and the capacitor C ₁ is only one time constant circuit connected to the oscillator 14 .

Here, to explain the oscillator 14 in more detail,
It is constructed as shown in FIG. 141 is
It is a control signal input terminal, and is connected to the base of the transistor _Tr1 via an inverter 144. The transistor Tr ₁ has an emitter connected to the reference ground terminal, a collector connected to the power supply terminal via the resistor R ₁ , and also connected to the collector of the transistor Tr ₂ and the input terminal 21 of the operational amplifier 146, and further, Input terminal 23 of operational amplifier 147
It is connected to the. The resistor _R1 is a capacitor
Together with _C1 , it forms a time constant circuit. The transistor Tr ₂ has a bias power supply E ₁ at its base.
is supplied, and its emitter is connected to a constant current source 145 together with the emitter of the transistor _Tr3 . The collector of the transistor Tr ₃ is connected to the power supply terminal, and the base is connected to the operational amplifier 14.
7 output ends are connected. Operational amplifier 146
A reference bias power supply _E2 is supplied to the input terminal 22 of the operational amplifier 147, and a reference bias power supply _E3 is supplied to the input terminal of the operational amplifier 147 via a resistor _R2 , and the output voltage is fed back via a resistor _R3 . has been done.

The oscillator 14 described above has a control signal input terminal 141
When the control signal applied to is low level, transistor _Tr1 turns on and stops oscillation. The potential at point C in the figure is approximately zero potential. Therefore, the outputs D and E of the operational amplifiers 146 and 147 are at high level. In addition, + of the operational amplifier 147
A reference voltage V _r1 is applied to the side input terminal 24 . A reference voltage V r1 can be applied to this + side input terminal 24 when the output E is at a high level, and a reference voltage V _r2 can be applied when the output E _is at a low level. Further, when the output E is at a high level, the transistor Tr ₃ is turned on and the transistor Tr ₂ is turned off. Furthermore, when the output E is at a low level, the transistor Tr ₃ can be turned off and the transistor Tr ₂ can be turned on.

Next, when the control signal B is at a high level, the transistor _Tr1 is turned off. For this reason, the capacitor
Charging of C ₁ with the power supply voltage is started via resistor R ₁ . If the terminal voltage of capacitor C ₁ at the start of charging is V _c = 0, the potential V _c at point C after time t is V _c = V _cc {1-exp(-t/R ₁ C ₁ )}... …It is expressed as (1). V _c rises and operational amplifier 14
7, the output E of the operational _amplifier 147 switches from high level to low level. By this,
The reference voltage of the + side input terminal 24 becomes V _r2 , and the transistor Tr ₃ is turned off and the transistor Tr ₂ is turned on. When this transistor Tr ₂ is turned on, the charge in the capacitor C ₁ starts discharging. At this time, the potential V _c at point C after t hours from the start of discharge is V _c = (V _cc - R ₁ I ₁ ) + (V _r1 - V _cc + R ₁ I ₁ ) exp (-t/R ₁ C ₁ )...(2) I ₁ ; Represented by the current flowing through the constant current source 145. This V _c decreases, and the reference voltage V _r2
When the voltage becomes approximately equal to , the output E becomes high level again and charging is performed. The potential at point C at this time is the same as equation (1). However, V _r2 ＜V _c ＜V _r1
The range satisfies the following. By repeating this, the oscillation continues and when the control signal B becomes low level again,
Oscillation stops and returns to the initial state. Further, the reference voltage V _r3 applied to the + side input terminal 22 of the operational amplifier 146 is set lower than the previous reference voltage V _r2 , and in the range where V _c is higher than the reference voltage V _r3 ,
An output D having a low level is obtained.

That is, the operating waveforms of the oscillator 14 described above are expressed as shown in FIG. 4c, d, and e.

The operation of the oscillator 14 described above as well as the operation of the circuit shown in FIG. 2 will be explained with reference to the operating waveforms of FIG. 4. FIG. 4a is a composite synchronization signal A,
It is input to a D type flip-flop circuit 17.
H _p is the horizontal synchronization signal and E _p is the equivalent pulse. Since the D type flip-flop circuit 17 outputs high level data D1 at the rise of the synchronization signal, its output, that is, the control signal B becomes high level. As a result, the oscillator 14 starts oscillating, and the output terminal ₀ of the D-type flip-flop 12 becomes low level, so that the flip-flop circuit 15, which constitutes the frequency divider,
16 is released. Then, the oscillation output E is halved by the flip-flop circuit 15.
The frequency is divided, but this inversion is performed by the rising edge of the input pulse, and the frequency divided output F is shown in FIG.
can be obtained. This frequency-divided output F is further frequency-divided by the flip-flop circuit 16, resulting in a frequency-divided output G shown in FIG. 4g. Since the outputs E, F, and G are logically calculated by the NOR circuit 17, an output H (high level) as shown in FIG. 4h is obtained from the NOR circuit 17. This output H is applied to the clear end of the D-type flip-flop circuit 12. Therefore, when the output H of the NOR circuit 17 becomes high level, the D type flip-flop circuit 12 is cleared and its output B becomes low level as shown in FIG. 4b. Also, at this time, the flip-flop circuits 15 and 16 are in the set state. Furthermore, as a result, the oscillator 14
oscillation operation stops, point C is discharged to zero potential,
Output E becomes high level. Then, when the next synchronization signal is input, the same operation can be repeated again.

In other words, in the circuit shown in Fig. 2, when a synchronizing signal is input (H _p in Fig. 4 a), the oscillator 14 starts oscillating, and the frequency divider counts the oscillation pulses, and this count number is N. When this happens, the oscillation is stopped. It then waits for the next synchronization signal to be input. Therefore, between the synchronization signal and the charging period of the capacitor _C1 of the oscillator 14, from zero potential to V _r3
The horizontal synchronizing pulse I as shown in FIG. 4i can be obtained by logically ANDing the periods up to this point using the AND circuit 13.

Here, in the waveform of Fig. 4c, the time from the start of rising (zero potential) to reaching the voltage V _r1
From equation (1), T ₀ is expressed as T ₀ = R ₁ C ₁ ln {V _cc /V _cc −V _r1 ...(3), and the time T ₁ required to fall from V _r1 to V _r2 is From equation (2), it is expressed as T ₁ =R ₁ C ₁ ln {(V _r1 −V _cc +R ₁ I ₁ )/V _r2 −V _cc +R ₁ I ₁ )} (4). Next, the time T ₂ from V _r2 to V _r1 is calculated from equation (1) as follows: T ₂ = R ₁ C ₁ ln {V _cc − V _r2 )/(V _cc − V _r1 )} ……(5) becomes.

Next, the Nth (in the example, N=
4) When the fall starts, output E becomes low level, output H becomes high level, and output B becomes low level. At this time, the transistor
Tr ₁ turns on and the potential of capacitor C ₁ drops rapidly to 0V, so this fall time is very short and can be ignored. Therefore, the pulse width T _D (mask width) of the D-type flip-flop circuit 12 can be approximated by T _D =T ₀ +(N-1)(T ₁ +T ₂ ) (6). This pulse width T _D is the equivalent pulse
It is set to about 3/4H for E _p removal.

Next, the time T ₁ in equation (4) is calculated as follows:
It depends on the constant current source current I ₁ inside the IC, but R ₁ × I ₁
If is chosen to be larger than V _cc −V _r1 , T ₁ becomes T ₂ ,
Since it is sufficiently smaller than T ₀ , the influence of variations in I ₁ is extremely small, and since the reference voltages V _r1 and V _r2 within the IC have good accuracy, variations in time T _D are small.

Next, when the pulse width T _HD of the horizontal synchronization pulse I is shorter than the pulse width of the composite synchronization signal, T _HD = R ₁ C ₁ ln {(V _cc / (V _cc − V _r3 )) from equation (1). } ...(7) If you want to make this T _HD considerably smaller, you have to make the time constant R ₁ × C ₁ smaller, but in this case, increase the number of division stages and increase N. Moreover, there is no need to increase the variation in T _D by increasing V _r1 .

(If V _cc −V _r1 is small, the effect of variation in V _r1 increases.) In the previous explanation, we considered the removal of equivalent pulses, but in the vertical retrace period of the composite synchronization signal, the vertical synchronization signal with a wide pulse width is It is included. In this case, since the D-type flip-flop circuit is an edge trigger, it operates only on the rising edge and has no relation to the pulse width, so the circuit operation in FIG. 2 is exactly the same as above. Furthermore, the configuration of the oscillator 14 is not limited to the embodiment shown in FIG. 3, as long as the waveform shown in FIG. 4c can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the time constant circuit can be realized with one piece, the number of pins of the IC can be reduced. Further, as shown in equations (1) to (7), the pulse width of each part can be determined with high accuracy, and the output pulse width can also be a very stable and accurate pulse.

[Brief explanation of drawings]

Figures 1a to d are operating signal waveform diagrams of a conventional horizontal synchronizing pulse generation circuit, Figure 2 is a circuit diagram showing an embodiment of the present invention, and Figure 3 is an example of an oscillator in the circuit of Figure 2. The circuit diagrams shown in Fig. 4 a to i are the circuit diagrams shown in Fig. 2,
4 is a signal waveform diagram of each part of the circuit of FIG. 3. FIG. R ₁ ...Resistor, C ₁ ...Capacitor, 12...D
Type flip-flop circuit, 13...AND circuit, 14...oscillator, 15, 16...flip-flop circuit, 17...NOR circuit.

Claims (1)

[Claims] 1. A capacitor is charged to the highest first level by being given a control signal for starting oscillation, and a second level lower than the first level and the first level are charged. The oscillation operation is performed to charge and discharge the capacitor in between, and when a control signal for stopping oscillation is given, the capacitor is discharged to below a third level, which is lower than the second level, and then the capacitor is stopped. An oscillator, a frequency divider that counts the oscillation output of the oscillator in response to a reset release control signal, and a logic circuit that generates a clear pulse when the count of the frequency divider reaches a predetermined value. and the control signal for starting oscillation and the control signal for canceling the reset are generated by inputting the composite synchronization signal, and the control signal for stopping the oscillation and the control signal for canceling the reset are generated by the clear pulse. a flip-flop circuit that outputs a reset control signal;
The composite synchronization signal is applied to one input terminal, an output that detects that the voltage of the capacitor of the oscillator is below the third level is applied to the other input terminal, and the logical product of both inputs is output. and a logic circuit that uses this as a horizontal synchronization pulse.