JPH0413787B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a PCM signal device, in particular, for example, among control signals for recording data and playback data of a PCM audio signal, the control signal is parallel to the currently defined control signal. Equipped with a recording LSI and an LSI control LSI that have a circuit configuration that allows the undefined control signal to be used even in the event that the undefined control signal is input to the system and is defined and used in the future. It concerns PCM signal equipment.

For example, when using video tape as a recording medium in PCM audio equipment, the PCM audio format signal is recorded on the video tape in a format compliant with television signals, including horizontal synchronization signals, vertical synchronization signals, etc. be done. As shown in Figure 1, the format signal of one horizontal synchronization section of the PCM signal consists of a 13-bit horizontal synchronization signal block, a 4-bit and data synchronization signal block, a 128-bit data block, a 4-bit white reference signal block, etc. One horizontal synchronization period consists of 168 bits. In the control signal block, as shown in FIG. 2, the 128-bit data block includes a 56-bit cue signal word, a 14-bit content identification signal word, a 28-bit address signal word, and a 14-bit control signal. A word and a 16-bit error detection signal word (CRC) are arranged to form a data control signal for one horizontal synchronization period. The control signal word consists of 14 bits, currently #1 to #10 are undefined and therefore not used, #11 is the dubbing prohibition code, #12 is the P correction identification code, and #13 is the dubbing prohibition code. Four types of bit Q correction identification code and #14 bit pre-emphasis identification code are defined and used as needed.

When designing and manufacturing a new recording LSI and LSI control LSI used in PCM audio equipment such as PCM audio adapters and PCM audio decks, the control signal consisting of 14 bits as shown in Figure 2 is used. The following two methods can be considered for processing each control signal within a block.

The first type is the serial input/output format shown in Figure 3A, in which each control signal data input in parallel to an external control signal block input circuit 1 during recording The signal is parallel-to-serial converted by the signal block input circuit 1 and then input to the recording LSI 2. During playback, control signal data input serially from the LSI control LSI 3 to an externally provided control signal block/latch circuit 4 is decoded by the control signal block/latch circuit 4 and output as parallel signals. It is something that
That is, control signal data in the form of a serial bit string is inputted to the recording LSI 2, and control signal data in the form of a serial bit string is outputted to the LSI control LSI 3.

The second is the parallel input/output format shown in FIG. 3B, in which each control signal data is input in parallel to the recording LSI 5; Parallel-to-serial conversion is performed within the recording LSI 5 to generate a serial bit string control signal. During reproduction, the control signal block/latch circuit provided in the LSI control LSI 6 decodes the serial bit string control signal and outputs each control signal data in parallel. i.e. for recording
Control signal data is input in parallel to the LSI 5, and control signal data is output in parallel to the LSI control LSI 6.

The former serial input/output type has the disadvantage of requiring external circuits for serial-to-parallel conversion and parallel-to-serial conversion. In the latter parallel input/output format, if you try to output all of the control signals in the control signal block,
Internal circuitry of LSI 5 for recording and LSI 6 for LSI control,
The disadvantage is that the number of input or output pins increases.
Also, if only the currently defined and used control signals of the 14-bit control signals are input/output, the amount of internal circuitry and the number of bins, which are the drawbacks mentioned above, will be reduced, but control signals other than
For example, when the currently undefined #1 bit control signal is defined and used, the PCM using the recording LSI 5 and LSI control LSI 6
In audio equipment, the control corresponding to the #1 bit control signal is not performed on recorded data or playback data, resulting in a problem of lack of versatility.

The present invention aims to solve the above problems. For example, when creating an LSI used in PCM audio equipment, control signals that are currently undefined and unused will be defined and used in the future. Considering the situation, add a series input/output circuit to avoid the above-mentioned situation of lack of versatility by adding an external circuit, and add an external circuit to the control signals currently defined and used. The circuit configuration is equipped with a parallel input/output circuit so that processing can be performed for the time being without any unnecessary processing, and it has the versatility to cope with the future use of control signals that are currently undefined and unused.
The purpose is to provide PCM signal equipment.
This will be explained below with reference to FIG. 4 and subsequent figures.

FIG. 4 shows the configuration of an embodiment for explaining the positioning of the present invention, FIG. 5 shows the circuit configuration of an embodiment of the control signal block output circuit used in FIG. 4, and FIG. An example circuit configuration of the control signal block input circuit used,
Figure 7 is an operation time chart of the control signal block output circuit, Figure 8 is an operation time chart when parallel control signals are input to the control signal block input circuit, and Figure 9 is an operation time chart of the control signal block input circuit. Each shows an operation time chart when a serial control signal is input.

In FIG. 4, reference numeral 7 represents a recording LSI, 8 a control signal block input circuit, 9 an LSI control LSI, 10 a control signal block output circuit, 11 a reproduction LSI, and 12 a memory.

Control signal block input circuit 8 is for recording
The control signal block output circuit 10 is installed inside the LSI 7, and the control signal block output circuit 10 is installed inside the LSI 9 for LSI control.
installed inside. And for controlling the LSI
The LSI 9 controls the recording LSI 7, the reproduction LSI 11, and the memory 12, and also has a part of a data reproduction function for reproducing data from a reproduction PCM signal reproduced from a recording medium.

The recording data of the PCM audio signal is input to the recording LSI 7, further temporarily stored in the memory 12, and then sequentially transferred to the recording LSI 7. The recording data transferred to the recording LSI 7 is added with other control signals, such as a horizontal periodic signal, a data synchronization signal, etc., and forms the format of one horizontal synchronization section consisting of 168 bits as shown in Figure 1.
It is output from the recording LSI 7 as a PCM signal.
At this time, if the recording data of the PCM audio signal is not pre-emphasized, for example, the control signal data with the pre-emphasis identification code "1" set indicating such a state is the control signal of the recording LSI 7. The corresponding bit is input to the block input circuit 8. In addition, the control signal data of the other control signals, such as the dubbing prohibition code, the P correction identification code, and the Q correction identification code, is inputted into the control signal block together with the control signal data of the pre-emphasis identification code by setting the content code to each control content. It is input to circuit 8. The above control signal data to the control signal block input circuit 8 are input directly without going through an external circuit when input in parallel, and after being converted into a serial bit string by an external circuit when input in series.

The reproduced PCM signal reproduced from the recording medium is a signal conforming to a television signal that includes control signals such as a horizontal synchronization signal and a data synchronization signal in addition to reproduction data, and is input to the LSI control LSI 9. concerned
The LSI control LSI 9 separates control signals such as the horizontal synchronization signal and data synchronization signal from the reproduction PCM signal, extracts reproduction data, and transfers the extracted reproduction data to the reproduction LSI 11. The playback data transferred to the playback LSI 11 is stored in the memory 12 and sequentially read out to the playback LSI 11, and becomes the playback data of the PCM audio signal and is used for the playback.
Output from LSI11. Each control signal that controls the reproduced data of the PCM audio signal is taken out as parallel output or serial output from the control signal block output circuit 10 of the LSI control LSI 9. The parallel output control signal taken out from the control signal block output circuit 10 becomes a direct control signal for the reproduction data output from the reproduction LSI 11, whereas the serial output control signal is decoded by an external circuit and output in parallel. The signal is converted into a control signal for the reproduction data.

In one embodiment of the control signal block output circuit shown in FIG. 5, reference numeral 10 corresponds to that in FIG. 4, and 13 is a control signal block/latch circuit which receives control signal data input in series. 14 is a clock generator, 15 is a 4-bit shift register, 16 to 18 are latch circuits, and 19 is a data processing circuit, which is included in the LSI control LSI 9 in FIG. 4. , 20 is an input terminal into which a reproduced PCM signal is input, 21 to 23
are serial output terminals, and 21 is a control signal data latch (CDLT), 22 is a control signal data clock (PBCS), 23 is a data (DATA) signal, and 24 is a terminal for serial output. 26 to 26 are parallel output terminals, 24 is an emphasis code (PBEM),
Reference numeral 25 represents a control signal for a Q correction code (QCOT), and reference numeral 26 represents a control signal for a dubbing prohibition code (DBIH) to output the decoded data contents.

The operation of the control signal block output circuit shown in FIG. 5 will be explained using the operation time chart of the control signal block output circuit shown in FIG. A reproduced PCM signal of one horizontal synchronization section carrying the control signal block shown in FIG.
In the data processing circuit 19, the horizontal synchronization signal 101 and the data synchronization signal 102 in the control signal block are separated and the data (DATA) shown in FIG. 7 is output.

A control signal data clock (PBCS) synchronized with the above data is generated from the clock generator 14 as shown in FIG. 7, and the control signal data latch (CDLT) is pulsed at the 112th clock of the control signal data clock. Generate a signal.

By the way, each of the data control signal data clock and control signal data latch signals are connected to the serial output terminals 23, 22, 21 and the 4-bit shift register 15 of the control signal block latch circuit 13 and the latch circuit 1.
6 to 18, respectively. Therefore, the data from the data processing circuit 19 input to the 4-bit shift register 15 is output from the 4-bit shift register 15 every time the control signal data clock generated by the clock generator 14 is input. As shown in Fig. 7, the terminals Q _A , Q _B , and Q _D have a cue signal (56 bits) 103, a content identification signal (14 bits) 104, an address signal (28 bits) 105, and a control signal (14 bits) 1.
06 are output in sequence. These output terminals
Since Q _A , Q _B , and Q _D are input to latch circuits 16, 17, and 18, respectively, the 112th control signal data clock is a 4-bit shift clock.
When input to the register 15, data representing the control contents of the pre-emphasis identification code 111 is input to the latch circuit 16, data representing the control contents of the Q correction identification code 110 is input to the latch circuit 17, and data representing the control contents of the Q correction identification code 110 is input to the latch circuit 17. Data representing the control contents of the dubbing prohibition code 109 is inputted to the field. As explained above, along with the generation of the 112th control signal data clock, the control signal data and
Since a latch pulse signal is output, each of the latch circuits 16 to 18 latches its respective input data. That is, parallel output terminals 24, 25, 2
6 has a pre-emphasis identification code 111, a Q correction identification code 110, and a dubbing prohibition code 109.
Control signal data representing the control content of each is output.

On the other hand, control signal data, latch, control signal data, and the like that output the 112th pulse signal to the serial output terminals 21, 22, and
Since the clock and data signals are output, the control signal block can be used as an external circuit.
By receiving the same latch circuit 13,
As explained above, each control signal data can be extracted in parallel from the reproduced PCM signal. At this time, the control signal block
4-bit shift register 1 of latch circuit 13
By using a 14-bit shift register instead of 5, it is possible to cope with the case where #1 to #10 bit control signals, which are currently undefined and unused, are newly defined and used.

In FIG. 7, reference numeral 107 represents a CRC signal (16 bits), and 108 represents a white reference signal (4 bits).

In one embodiment of the configuration of the control signal block input circuit of FIG. 6, reference numeral 8 corresponds to that of FIG. 27 is a clock generator, 28 to 3
3 is a NAND gate, 34 and 35 are data processing circuits which are included in the recording LSI shown in Figure 4, and 36 is a recording data input terminal.
37 and 38 are serial input terminals into which PCM audio signal data is input, a control signal (CSIG) is input to 37, and a shift clock (COTS) is output to 38. 39 and 40 are parallel input terminals, and 39 is an emphasis code (EMPH).
data is input, 40 is input with dubbing prohibition code (DBTH) data, 41
is an output terminal to which a recording PCM signal is output, 42 is a cue signal (GD) line, 43 is a control signal (CSIGR) control line, 44 is an emphasis code (EMPH) control line, 45
46 represents a dubbing inhibition code (DBIH) control line, 46 represents a control signal (CGATE) control line, 47 represents a control signal (CSIGM) line, and 48 represents a data (Data) line.

Currently, there are usually two types of control signals required during recording: a pre-emphasis identification code and a dubbing prohibition code. Control signal data representing the contents of these codes is sent to parallel input terminals 39 and 4.
0 in parallel, the control signal data of the pre-emphasis identification code and the dubbing prohibition code are generated at a predetermined position of the control signal block placed at the beginning of the data section of each field. This will be explained using an operation time chart when control signals are input in parallel to the control signal block input circuit shown in the figure.

In the case of parallel input, the control signal at terminal 37 for serial input is set to logic "0". The emphasis code control line 44 is output from the clock generator 27 at a predetermined timing as shown in FIG.
and generates a pulse signal on the dubbing prohibition code control line 45. As a result, the control signal data representing the control contents of the emphasis code and the dubbing prohibition code inputted to the parallel input terminals 39 and 40 are transmitted to the NAND gates 29 and 3.
0 respectively, and become control signals for the pre-emphasis identification code 111 and the dubbing prohibition code 109. These control signals are the cue signal 10 generated by the clock generator 27.
3 and NAND gate 31 and converted into a serial bit string. The serial bit string is passed through the NAND gate 32 by a logic "1" on the control signal control line 46 that is input to the NAND gate 32. Since the NAND gate 32 is open only during one horizontal synchronization period of the control signal block generated by the clock generator 27, the serial bit string exists only during the control signal block period. The data output from the data processing circuit 34 and the serial bit string are combined by a NAND gate 33, and the output thereof is input to the data processing circuit 35. In the data processing circuit 35, a horizontal synchronizing signal 101, a data synchronizing signal 102, and a white reference signal 108 are added to the serial bit string to make the signal in a format compliant with the television signal, and
After data processing including the CRC signal 107 is performed, a control signal block for one horizontal synchronization period is generated. In this way, the pre-emphasis identification code 111 and the dubbing prohibition code 10 are placed at predetermined positions.
Each signal of the control signal block including control signals 9 and 9 is outputted from the output terminal 41 as a recording PCM signal.

On the other hand, when the control signal data of the pre-emphasis identification code and the dubbing prohibition code are converted into serial signals converted from parallel to serial by an external circuit and input to the serial input terminal 37, the control signal data is the beginning of the data section of each field. The operation generated at a predetermined position of the control signal block placed in the control signal block will be explained using an operation time chart when a serial control signal is input to the control signal block input circuit shown in FIG.

In the case of serial input, the parallel input terminals 39 and 40 are set to logic "0". As shown in FIG. 9, when the clock generator 27 finishes outputting a predetermined cue signal 103, a predetermined number of shift clocks are output from the serial input terminal 38. Note that although the shift clock is output from the serial input terminal 38 as explained above, it is referred to as "for input" because the control signal that is a serial signal is input to the serial input terminal 38. This term is based on the meaning of a terminal for causing a control signal block to generate a control signal such as a pre-emphasis identification code or a dubbing prohibition code at a predetermined position from the serial input terminal 37.

The series input terminal 37 is connected in parallel by an external circuit.
A control signal in the form of a serial bit string of a content identification number, an address signal, and a control signal that has been serially converted is input, and in synchronization with the shift clock, the control signal of the serial bit string is sequentially NANDed. gate 28
is input. At this time, as shown in FIG.
Since the control signal control line 46 is at logic "1", the control signal of the serial bit string input to the NAND gate 28 is a NAND gate.
It passes through gates 28, 31, and 32, is combined with data from data processing circuit 34 at NAND gate 33, and is input to data processing circuit 35. In the data processing circuit 35, various signals are added to predetermined positions as described above, and a control signal block for one horizontal synchronization period is generated.

Since the control signals for the pre-emphasis identification code 111 and the dubbing prohibition code 109 are placed at predetermined positions in the serial bit string generated by an external circuit and input to the serial input terminal 37, they are output from the data processing circuit 35. It is also placed at a predetermined position within the control signal block. Each signal of the control signal block obtained in this way is output to the output terminal 4 as a recording PCM signal.
Output from 1.

As explained above, the currently established and used control signals can be encoded and decoded without adding an external circuit for the time being.
Furthermore, even if an undefined control signal is defined and used in the future, it is possible to encode and decode it by adding an external circuit, thereby providing versatility.

Then, it encodes and decodes the control signals that will be used for the time being, for example for recording.
Since a parallel-serial conversion circuit and a serial-parallel conversion circuit are provided for each LSI and LSI control LSI, the amount of internal circuitry and the number of input/output pins provided in each LSI can be reduced.

[Brief explanation of drawings]

Figure 1 shows the format signal configuration of one horizontal synchronization section of the PCM signal, Figure 2 shows the control signal block configuration, Figures 3A and B are explanatory diagrams for explaining the recording/playback input/output format of the PCM signal, and Figure 4 The figure shows the configuration of one embodiment for explaining the positioning of the present invention, FIG. 5 shows the circuit configuration of one embodiment of the control signal block output circuit used in FIG. 4, and FIG.
The circuit configuration of one embodiment of the control signal block input circuit used in the figure, Figure 7 is an operation time chart of the control signal block output circuit, and Figure 8 shows the control signal input circuit in which parallel control signals are input to the control signal block input circuit. FIG. 9 shows an operation time chart when a serial control signal is input to the control signal block input circuit. In the figure, 1 and 8 are control signal block input circuits, 2, 5, and 7 are recording LSIs, and 3, 6, and 9 are control signal block input circuits.
LSI control LSI, 4 is a control signal block/latch circuit, 10 is a control signal block output circuit, 11 is a playback LSI, 12 is a memory,
13 is a control signal block/latch circuit;
14 is a clock generator, 15 is a 4-bit shift register, 16 to 18 are latch circuits, 1
9 is a data processing circuit, 20 is an input terminal, 21 to 23 are serial output terminals, 24 to 26 are parallel output terminals, 27 is a clock generator, 28 to 33 are NAND gates, 34 and 35 are data processing circuits , 36 are recording data input terminals, 37 and 38 are serial input terminals, 39 and 40 are parallel input terminals,
41 each represents an output terminal.

Claims (1)

[Claims] 1 A first circuit equipped with a circuit that generates a predetermined PCM signal format including PCM data and a control signal for the data.
The first LSI includes an LSI and a second LSI that obtains reproduction data of the PCM signal.
and an LSI control LSI that controls a second LSI, which inputs a reproduced PCM signal to the LSI control LSI and extracts a control signal corresponding to the reproduced data of the PCM signal reproduced by the second LSI. In a PCM signal device equipped with a control LSI, the first LSI has an input circuit into which each control signal for the above data is converted into a serial bit string by an external circuit and then inputted. A control signal block input circuit is provided, which includes an input circuit in which each control signal is input in parallel and converted into a series, and then generates a serial bit string of the control signal.
The LSI control LSI has an output circuit that outputs a serial bit string control signal that each control signal corresponding to the playback data is decoded by an external circuit, and a predetermined control signal of the serial bit string that is converted into parallel signals. a control signal block circuit that includes a control signal block/latch circuit that outputs a control signal after being decoded and decoded;
It is characterized by a circuit configuration in which control signals for PCM signal data and playback data are input and output in either serial or parallel mode.
PCM signal equipment.