JPH0416762B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a focus detection method for cameras used in still cameras, cine cameras, microphotography devices, and the like.

Recently, cameras that detect focus, such as automatic focus cameras, have been proposed.As one method of detecting focus, for example, a part of the subject image is received by a row of light receiving elements each having a large number of light receiving elements. There is a method of converting an output analog image signal of a light receiving element into a digital signal and obtaining a focus detection signal from the sum of absolute values of differences between digital signals corresponding to adjacent light receiving elements. However, in this case, variations in the output due to the sensitivity of each of the many light-receiving elements, variations in the electrical characteristics of the peripheral circuits corresponding to each light-receiving element, non-uniformity of the optical system, etc. are superimposed on the image information of the subject image. Therefore, there is a drawback that accurate focus detection cannot be performed, especially for subjects with low contrast.

In order to eliminate this drawback, it is necessary to correct the signal level for each light receiving element. Below is the first part of the most common correction method that has been used.
This will be explained with reference to the figures. In Figure 1, the horizontal axis is the illuminance E.
( _X ), and the vertical axis represents the output V(v) of each light receiving element. First, measure the dark output A _o of each light receiving element in the dark state, and calculate the minimum value A _p
Find A _o −A _p −a _o as . Next, with all light-receiving elements uniformly illuminated with light of sufficient brightness (illuminance E _H ), the output B _o of each light-receiving element is measured, and the maximum value thereof is set as B _p . Find yon from the actual value y o at a given brightness (illuminance E _o ), with A _p and B _p as a straight line A as the ideal sensitivity straight line, and straight line B connecting A _o and _{B o} as the actual value straight line. . For this purpose, first, the actual measured value straight line B is translated downward by _ao to create a straight line C shown by a two-dot chain line. Letting the intersection of this straight line C and the illuminance E _o be y _o ′, yon＝B _p ／E _H E _o …(1) y _o ′＝B _o ′−a _o ／E _H E _o ＝y _o −a _o …(2) Eliminating E _o /E _H and y _o ′ from equations (1) and (2) above, yon＝B _p /B _o −a _o y _o −a _o B _p /B _o − a _o ...(3), and if we measure A _o = B _p / B _o - a _o and B _o = a _o B _p / B _o - a _o as the correction coefficient of each light receiving element, then yon = A _o y Correction using the general form of first-order correction _o −B _o becomes possible.

However, since the above correction method requires measurement in both dark and dark conditions, it is difficult to perform correction during actual photographing, especially in cameras and the like. In addition, since primary correction always includes multiplication by A _o y _o , the arithmetic circuit becomes large and expensive.
Even when using a microcomputer, low-end models have the drawback of being time consuming.

It is an object of the present invention to eliminate the various drawbacks mentioned above, to effectively correct variations in the characteristics of each light-receiving element with a simple and inexpensive configuration, and to always achieve highly accurate imaging even for objects with low contrast. It is an object of the present invention to provide a focus detection method for a camera that enables rapid focus detection.

The present invention projects a small common portion of an image of an object formed by an optical system onto an array of light-receiving elements, obtains image information corresponding to the light intensity distribution of the object image from each light-receiving element, and determines this image information. In the camera focus detection method of detecting the in-focus state of an object image by calculating based on a calculated evaluation function, the light-receiving element array is uniformly illuminated from in front of the light-receiving element array to determine the output of each light-receiving element. It is characterized in that the image information of each light receiving element corresponding to the light intensity distribution of the object image is corrected based on the stored values.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an example of a focus detection device that performs the camera focus detection method according to the present invention. A light emitting diode is provided between the photographing optical system 2 and the light receiving element array 3 in the photographing optical path in which a part of the image of the subject 1 is projected through the photographing optical system 2 onto the light receiving element array 3 having a large number of integral type light receiving elements. etc. luminous body 4
selectively intervene. In this example, prior to projecting the image of the subject 1 by the light emitter 4, the light receiving element array 3
is uniformly illuminated, and the outputs of all the light receiving elements are supplied to an analog-to-digital (A/D) conversion circuit 5 to be converted into a digital signal, which is then taken into the central processing unit 6 as a correction value. Next, the light emitter 4 is removed from the photographing optical path, a part of the image of the subject 1 is projected onto the light receiving element array 3, and the outputs of all the light receiving elements at that time are measured by the A/D converter in the same way as described above. The signal is supplied to a conversion circuit 5, converted into a digital signal, and taken into the central processing unit 6 as image information. The central processing unit 6 includes a correction value reading unit 7, an image information reading unit 8, a correction calculation unit 9, a focus detection unit 10, and a controller unit 11. By subtracting the correction value for the light-receiving element taken into the correction value reading unit 7 from the image information for the element, variations in characteristics of each light-receiving element are corrected, and based on this corrected image information, focusing is performed. In the detection unit 10, for example, the absolute value of the difference between adjacent light receiving elements is calculated, and the in-focus state is determined using the sum of these absolute values or the sum of the absolute values from the largest absolute value to a predetermined number as an evaluation function. A focus detection signal is obtained, which is supplied to the display device 12 via the controller unit 11 to notify the photographer of the focused state, and the photographic optical system 2 is controlled by an arrow through the optical system drive circuit 13 and optical system drive device 14. Focus adjustment is performed by displacement in the optical axis direction as shown. The controller unit 11 not only controls the central processing unit 6 but also controls the driving of the light receiving element array 3, the light emitter 4, and the A/D conversion circuit 5. Further, in a simple type device, the photographing optical system 2 may be driven manually by the photographer according to instructions on the display device 12, and the optical system drive circuit 13 and the optical system drive device 14 may be omitted. good.

Focus detection can be performed by arranging one light-receiving element array on a plane optically equivalent to the intended focal plane of the photographic optical system 2, or at equal distances before and after the position optically equivalent to the intended focal plane. It is also possible to perform focus detection by arranging one on each plane. For example, when applying the focus detection device of the present invention to a single-lens reflex camera, two light receiving element arrays are connected to the photographing optical system 2.
When disposing the mirror at equal distances before and after the planned focal plane of 23,
The photographing light flux reflected by the half mirror 23 is guided to an observation optical system comprising a focusing plate 24, a pentaprism 25, etc., and the light flux transmitted through the half mirror 23 is guided to a reflection mirror 26 provided on the back surface of the quick return mirror 22. The light beam guided downward is transmitted through the half mirror 27 and incident on one of the light receiving element rows 3A, and the light beam reflected by the half mirror 27 is transmitted through the reflecting mirror 28 to the other light receiving element. The configuration is such that the light is incident on column 3B. As described above, the light receiving element arrays 3A and 3B are arranged at equal positions before and behind a plane that is optically conjugate with the film 21.

Further, in this case, the light emitter 4 is a shutter 30 that is selectively interposed in the distance measuring optical path between the reflecting mirror 26 and the half mirror 27 by driving the motor 29.
can be provided on the lower surface of the shutter 30.

The conversion process in the A/D conversion circuit 5 described above includes, for example, sequentially extracting output analog image information from a large number of light-receiving elements provided in a row of light-receiving elements,
Although it is possible to convert this into digital values successively, if such a successive conversion method is adopted, it takes time to convert all the necessary data into digital values, which is disadvantageous.

For this reason, this embodiment uses a parallel A/D conversion circuit that can convert a large number of analog quantities into digital values almost simultaneously. Hereinafter, an embodiment using such a parallel A/D conversion circuit will be described in further detail.

FIG. 4 shows in detail the light receiving element array, A/D conversion circuit 5, and central processing unit 6 when performing such parallel analog-to-digital conversion. In this embodiment, as explained in FIG. 3, the two light-receiving element arrays 3A and 3B are arranged at equal positions before and after a plane that is engineeringly conjugate to the intended focal plane of the photographing optical system, and the light emitter 4 is attached to the lower surface of the shutter 30, and under the control of the central processing unit 6, the driving circuit 31 and motor 29 are driven to interpose it in the distance measuring optical path and at the same time drive it to emit light.

The light receiving element arrays 3A and 3B are configured to be driven and controlled by commands from the central processing unit 6. Each light receiving element of these light receiving element rows 3A and 3B is connected to a sample hold circuit 38 provided corresponding to each light receiving element row.
A ₁ to 38A _o and 38B ₁ to 38B _o , respectively, and these sample and hold circuits 38
A ₁ to 38A _o , 38B ₁ to 38B _o have a sample hold signal line a and a sample hold circuit 38.
Any of A ₁ to 38A _o and 38B ₁ to 38B _o ,
That is, selection signal lines b and c from the central processing unit 6 for selecting one of the light receiving element arrays 3A and 3B are connected in parallel, respectively. Sample hold circuit 38A ₁ ~ 38A _o , 38B ₁ ~
Each output terminal of 38B _o is connected to one input terminal of comparator circuits 39 ₁ to 39 _o commonly used for light receiving element arrays 3A and 3B. That is, the sample and hold circuits 38A ₁ and 38B ₁ are used as the comparator circuit 39 ₁ , the sample and hold circuits 38A ₂ and 38B ₂ are used as the comparator circuit 39 ₂ , and the sample and hold circuit 38A _o
and 38B _o are connected to the comparator circuit 39 _o . The other input terminals of these comparator circuits 39 ₁ to 39 _o are connected in parallel to the D/A converter 40,
This D/A converter 40 receives predetermined digital signals of different numerical values from a counter 41 with a pulse generator controlled by the central processing unit 6 and one after another representing numerical values within a predetermined range. Provides the generated digital signal. In this example, this digital signal is formed with 4 bits. The output terminals of the comparator circuits 39 ₁ to 39 _o are connected to corresponding digital memories 42 ₁ to 42 _o , respectively, and are also connected in parallel to an AND circuit 43 and an OR circuit 44, respectively. The output terminals of the AND circuit 43 and the OR circuit 44 are respectively connected to the central processing unit 6, and the output terminal of the OR circuit 44 is further connected to one input terminal of a flip-flop 45.
The other input terminal of the flip-flop 45 is connected to the central processing unit 6, and the output analog image information from all the light-receiving elements of the light-receiving element rows 3A and 3B is sent to the corresponding sample through a sample-hold signal line a based on the output of the flip-flop 45. Hold circuits 38A ₁ to 38A _o and 38B ₁ to 38B _o
Configure to hold the sample. Further, the output of the counter 41 is supplied in parallel to the digital memories 42 ₁ to 42 _o , and these output terminals are connected in parallel to the central processing unit 6, so that the digital signals stored in the required memories are sent to the address bus 46. The address decoder 47 is controlled through the address decoder 47 and the data is input into the central processing unit 6.

FIG. 5 shows the light receiving elements 3A, 3B and sample and hold circuits 38A ₁ to 38A _o , 38 shown in FIG. 4.
It is a more detailed circuit configuration diagram of the part B ₁ to 38B _o , where 3A ₁ to 3A _o indicate each light receiving element part of the light receiving element row 3A, and 3B ₁ to 3B _o indicate each light receiving element of the light receiving element row 3B. Each light receiving element section is constructed by connecting a light receiving element and a capacitor in parallel. Here, the light receiving elements are denoted by symbols 3'A ₁ to 3'A _o ,
3′B ₁ ~3′B _o , and the capacitors are designated 3″A ₁ ~
3″A _o , 3″B ₁ to 3″B _o . One end of all of these light receiving elements is connected in parallel to the power supply of power supply voltage V _c , and the other end is connected to the central processing unit 6. ON-OFF controlled switch 50A ₁ ~ 50
A _o , 50B ₁ to 50B _o are connected to the ground plate. Sample hold circuit 38A ₁ ~
38A _o and 38B ₁ to 38B _o each include two buffers 51A ₁ , 52A ₁ to 51A _o , 52A _o and 51B ₁ , 52B ₁ to 51B _o , 52B _o , and two gates 53A ₁ , 54A ₁ 53A _o , 54A _o and 53B ₁ , 54B ₁ -53B _o , 54B _o and one capacitor 55A ₁ -55A _o and 55B ₁ -55B _o , gates 53A ₁ -53A _o and 53B ₁ -
53B _o is controlled by the output of flip-flop 45 via sample and hold signal line a, and gates 54A ₁ to 54A _o are controlled by the output of flip-flop 45 via select signal line b.
Furthermore, the gates 54B ₁ to 54B _o are connected to the selection signal line c.
and are respectively controlled by the central processing unit 6.

FIG. 6 shows a specific circuit configuration of peripheral circuits such as a sample and hold circuit corresponding to one light receiving element section. In this example, the switch 50A ₁ and the gate 54A ₁ are configured with semiconductor switches using field effect transistors, and the buffer 51A ₁
and _52A1 are each constructed by connecting a resistor to the source-drain path of a field effect transistor. The peripheral circuits corresponding to other light-receiving elements are also connected to the sixth
Configure as shown in the figure.

7A to 7D are waveform diagrams for explaining the operation of the focus detection device of this embodiment, and FIG. 7A shows signals from the central processing unit 6 to switches 50A ₁ to 50A _o , 50
7B shows the output potentials of the buffers 51A ₁ to 51A _o and _{51B 1} to 51B _o , and FIG _. 7C shows the sampling signal from the flip-flop 45. D is Batsuhua 52
The output potentials of A ₁ to 52A _o and 52B ₁ to 52B _o are shown, respectively.

The operation of the focus detection device of this embodiment will be explained below.

In this example, first, the motor 29 is driven via the drive circuit 31 under the control of the central processing unit 6, and the shutter 30 is interposed in the distance measuring optical path between the reflecting mirror 26 and the half mirror 27 in FIG. , the light emitter 4 emits light and the light receiving element arrays 3A, 3B
is uniformly illuminated, and sample and hold circuits 38A ₁ to 38A _o , _{3 output analog illuminance information of the respective light receiving element sections 3A 1 to 3A o, 3B 1 to 3B o} at that time.
After holding samples at the same time from 8B ₁ to 38B _o ,
These are converted into digital signals and taken into the central processing unit 6 as correction values, and then the motor 29 is driven again to move the shutter 30 out of the distance measuring optical path, erase the light emitter 4, and receive the subject image. Projected onto the element arrays 3A and 3B and integrated, the output analog image information for focus detection is sent to the sample and hold circuits 38A ₁ to 38A _o and 38B ₁ to 3 in the same manner as above.
8B _o at the same time, convert it into a digital signal, and input it into the central processing unit 6.

Before the start of integration, switches 50A ₁ to 50A _o and 50B ₁ to 50B _o are open (OFF), and the voltage between the terminals of capacitors 3″A ₁ to 3″A _o and 3″B ₁ to 3″B _o is It is "0". Therefore, Batsuhua 51A ₁
The input potential to ~51A _o and 51B ₁ ~51B _o is V _c
and buffers 51A ₁ to 51A _o , 51B ₁ to 5
The output of 1B _o is at a corresponding predetermined potential V (7th
Figure B).

The gates 53A ₁ to 53A _o and 53B ₁ to 53B _o are open (ON), and this potential is applied to the capacitor 55A ₁
~55A _o and 55B ₁ ~55B _o are applied, and these capacitors are charged to the potential V. One of the gates 54A ₁ to 54A _o and 54B ₁ to 54B _o is open and the other _is closed;
~54A _o is open (ON), 54B ₁ ~54B _o
It is assumed that is closed (OFF).

In this state, the capacitor 55A ₁ ~ 55A _o , 5
The terminal voltage V of 5B ₁ to 55B _o is a buffer 52A ₁ to 52A _o , 52
Input to B ₁ ~ 52B _o and the corresponding potential
V' (Fig. 7D) is output.

To perform integration, first, the switches 50A ₁ to 50A _o , 50B ₁ to 5 are activated by a command from the central processing unit 6.
Close 0B _o (ON). Then, capacitor 3″A ₁
V _c is applied to ~3″A _o , 3″B ₁ ~3″B _o , and these capacitors are charged to V _c .In addition, along with this, buffers 51A ₁ ~51A _o , 51B ₁ ~51
Since the input potential to B _o becomes "0", the outputs of these buffers also become "0" or a small value close to this, and the capacitors 55A ₁ to 55
A _o , 55B ₁ to 55B _o and gates 53A ₁ to 53A _o ,
53B ₁ to 53B _o and buffer 51A ₁ to 51
A _o , 51B ₁ to 51B _o are discharged. As a result, buffers 52A ₁ to 52A _o , 52B ₁ to 52B _o
Since the input to the circuit decreases, its output also becomes "0" or a small value close to this.

After a predetermined time (capacitor 3″A ₁ ~ 3″A _o ,
After 3″B ₁ to 3″B _o are sufficiently charged), the switch 50A ₁ to 50 is activated by a command from the central processing unit 6.
Open A _o , 50B ₁ to 50B _o (OFF). Then,
The charges stored in the capacitors 3''A ₁ to 3''A _o , 3''B ₁ to 3''B _o are transferred to the light receiving elements 3'A ₁ to 3'A _o , 3'B ₁ to
A photocurrent with an intensity corresponding to the light incident on 3'B _o is discharged through each light receiving element, and buffers 51A ₁ to 51A _o , 51B ₁ to 51
The input potential to B _o rises, and its output also gradually increases (Figure 7B). Accordingly, the capacitors 55A ₁ to 55A _o and 55B ₁ to 55B _o are charged via the buffers 51A ₁ to 51A _o and 51B ₁ to 51B _o and the gates 53A ₁ to 53A _{o and} 53B ₁ to 53B _o. From, Batsuhua 52A ₁ ~ 52A _o , 52
The input potential and output potential of B ₁ to 52B _o also gradually increase.

This buffer 52A ₁ ~ 52A _o or 52B ₁ ~
The output potential of 52B _o passes through the gates 54A ₁ to 54A _o or 54B ₁ to 54B _o to the comparator circuit 3.
It is supplied to one input terminal of 9 ₁ to 39 _o .

On the other hand, in this example, first, the light receiving element portions 3A ₁ to 3A _o ,
In order to detect the correction value for the output variation in 3B ₁ to 3B _o , the counter 41 is activated at the same time as the integration starts.
, a digital signal having an analog value converted into an analog value by the D/A converter 40 and having a value corresponding to the luminous intensity of the light emitting body 4 or a constant value close to this, for example "0111", is sent to the D/A converter 40. Then, an analog reference signal of a constant value corresponding to this digital signal is sent from the D/A converter 40 to the comparator circuits 39 ₁ -
39 _o in parallel to the other input terminal. Comparator circuits 39 ₁ to 39 _o combine this constant value analog reference signal with the sample hold circuit 38A ₁
- 38A _o are compared in parallel, and at least one of the outputs is inverted, that is, a large number of analog information from the light receiving element array 3A supplied via the sample and hold circuits 38A ₁ to 38A _o . The OR circuit 44 detects that at least one of the signals exceeds the analog reference signal of a certain value supplied from the D/A converter 40, and thereby operates the flip-flop 45 to output the sample and hold signal line a. Sample and hold circuit 38
The gates 53A ₁ to 53A _o and 53B ₁ to 53B _o of A ₁ to 38A _o and 38B ₁ to 38B _o are closed (see FIG. 7C), and the light receiving element arrays 3A and 3 are closed.
Sample and hold circuit capacitors 55A ₁ to 5 each correspond to all output analog information of B.
5A _o and 55B ₁ to 55B _o at the same time (see FIG. 7D).

The solid line A shown in FIG. 8 indicates the correction value level at each light receiving element section of one of the light receiving element rows 3A that was sampled and held at this time.The vertical axis represents the sample hold level (potential), and the horizontal axis represents each light receiving element. It represents the department. Further, straight line B represents an ideal state, and if there is no variation in the characteristics of each light receiving element in the light receiving element array 3A, all outputs will have equal values as shown by straight line B.

Note that the solid line A also applies to the other light-receiving element row 3B.
Outputs with such variations are sampled and held.

Next, the central processing unit 6 controls the counter 41 to output a digital signal from the counter 41 within a predetermined range, for example, from "0000" to "1111", the value of which changes sequentially from larger to smaller. /A
Converter 40 is supplied. The D/A converter 40 successively converts this digital signal into an analog signal and supplies it to one input terminal of each of the comparator circuits 39 ₁ to 39 _o . Note that this analog signal gradually decreases as the digital signal output from the counter 41 sequentially changes from a larger value to a smaller value. The other input terminal of each of the comparator circuits 39 ₁ to 39 _o is connected to the light receiving element array 3 held in the sample and hold circuits 38A ₁ to 38A _o .
Output analog information from each of the light receiving element sections 3A ₁ to 3A _o of A is supplied. Comparator circuit 39
Each of ₁ to 39 _o is connected to the corresponding digital memory 42 by an inverted signal generated when the magnitude relationship of both inputs is reversed, that is, when the sampled and held analog information exceeds the analog signal from the D/A converter 40. ₁ to 42 _o , and write the digital signal that the counter 41 is outputting at that time into the digital memory. Comparator circuit 39
When all the outputs of ₁ to 39 _o are inverted, that is, all the digital memories 42 ₁ to 42 _o produce digital signals corresponding to the variations in the outputs of the light receiving element array 3A sampled and held in the sample and hold circuits 38A ₁ to 38A _o . When the (correction value) is written and the A/D conversion is completed, the AND circuit 43 operates at that point, so the central processing unit 6 controls the counter 41 based on the output of the AND circuit 43. Stop sending digital signals from the That is, if the A/D conversion of the analog information of the light receiving element sections 3A ₁ to 3A _o is completed at the time when "0100" is sent out, the digital signals from "0011" to "0000" are not sent out. In this way, since the digital signals to be sent range from "1111" to "0100", the predetermined time for A/D conversion can be shortened to the minimum.

Thereafter, the central processing unit 6 controls the address decoder 47 via the address bus 46 to take in the correction values written in the digital memories 42 ₁ to 42 _o .
It is stored in a predetermined memory within the central processing unit 6.

Next, the central processing unit 6 closes the gates 54A ₁ to 54A _o via selection signal lines b and c, and at the same time opens the gates 54B ₁ to 54B _o to open the sample and hold circuits 38B ₁ to 38B _o , that is, the light receiving element array 3B. The light receiving element sections 3B ₁ to 3 of the light receiving element row 3B are selected and sampled and held in each of these sample and hold circuits 38B ₁ to 38B _o .
The output analog information of B _o is A/D converted by the same operation as above and stored in a predetermined memory in the central processing unit 6.

With the above steps, A/D conversion of the output analog information of all the light receiving element sections (including peripheral circuits) when uniform light is irradiated onto the light receiving element rows 3A and 3B is completed, and the correction value of each element section is completed. is obtained.

Next, the motor 29 is driven to move the shutter 30 out of the distance measuring optical path, erase the light emitter 4, and integrate the subject image to obtain a signal for focus detection. A digital signal of a constant value, for example "1111" corresponding to the largest value of the analog values converted into analog values by the A converter 40 or a value close to this, is sent to the D/A converter 40, and the digital signal corresponding to this digital signal is sent to the D/A converter 40. An analog reference signal of a constant value is supplied in parallel from the D/A converter 40 to the other input terminals of the comparator circuits 39 ₁ to 39 _o . In this way, for example, if the light receiving element row 3A is selected, at least one output of the output analog image information from the sample and hold circuits _38A1 to _38Ao exceeds the above-mentioned constant value of the analog reference signal. , the inverted signal of the comparator circuit is detected by the OR circuit 44 and the flip-flop 4
5, the analog image information output from all the light receiving element sections of the light receiving element rows 3A and 3B is simultaneously held in the corresponding sample and hold circuits. After that, sample and hold circuits 38A ₁ to 38A _o and 38
The analog image information of the light-receiving element arrays 3A and 3B sampled and held in _B1 to 38B _o , respectively, is A/D converted by the same A/D conversion operation when obtaining the above-mentioned correction value, and then converted into the light-receiving element array. Each time, the data is taken into a predetermined memory in the central processing unit 6. In this case, the A/D conversion is performed by sending out from the counter 41 a digital signal whose value successively changes from larger to smaller in the range of "1111" to "0000" in this example. If you do this,
If the digital signal when the AND circuit 43 operates is "0111", there is no need to send out the digital signals from "0110" to "0000", so the analog Information can be A/D converted.

Here, when uniform light is irradiated by _the light emitter 4 shown by _the solid line A in FIG. 8, the output analog illuminance information (corrected The value) is obtained by adding a potential corresponding to the light intensity of the light emitter 4 to each dark level as shown by the solid line C in FIG. 8, and the solid line A and the solid line C are similar. This also applies to the light receiving element array 3B. The level of each element shown by solid line A is bn, the minimum value is bn min, and the level at which the dark level of each element is superimposed when the subject image is integrated is
If yn is the true analog image information yon according to the light intensity of the subject image with dark level corrected,
yon−yn− (bn−bu min). Therefore,
By calculating yon in each element portion and using these signals for focus detection, highly accurate focus detection can be quickly performed in accordance with the light intensity distribution of the subject image. Note that when using the sum of the absolute values of differences in the outputs of adjacent light-receiving element sections as an evaluation function for focus detection, the true analog image information yom of the m-th light-receiving element section is yom = ym −(bm
-bn min), the true analog image information yom+1 of the m+1th light receiving element section is yom+1=ym+1-
(bm+1-bn min), and the absolute value D of these differences is D=|ym-(bm-bn min)-{ym+1-(bm
+1−bn min)}｜=|ym−bm−(ym+1−bm
+1) | and bn min is eliminated. Therefore,
In this case, the light intensity distribution of the subject image is corrected for variations in characteristics by a simple calculation that subtracts the potential (correction value) corresponding to the dark level shown by the solid line A from the image information for focus detection of each element part. Since it is possible to obtain a signal according to the following, highly accurate focus detection can be performed more quickly with a simple circuit configuration.

In this embodiment, the correction value is subtracted from the focus detection signal for each element described above in the central processing unit 6 which A/D converts and imports each signal. Both digital values corresponding to the light intensity distribution are transmitted to the light receiving element array 3A.
For each of 3B and 3B, arithmetic processing is performed based on a predetermined evaluation function to obtain an evaluation value for each, and a focus detection signal indicating a focused state is obtained based on the comparison result of the evaluation values of both, and this is displayed. The signal is supplied to the device 12 to notify the photographer of the state of focus, and as explained in FIG. 2, the focus of the photographing optical system 2 is adjusted via the optical system drive circuit 13 and the optical system drive device 14.

The circuit configuration of the central processing unit 6 and its arithmetic operation will now be described with reference to FIG. 9 when the evaluation function S shown below is used.

S= _N 〓 ^k=1 D _k , where D _k is the absolute value of the difference between the outputs of adjacent light receiving elements among the corrected light receiving element outputs, and is the kth value counting from the largest one, N is a positive integer represented by 1≦N≦n−2, where n is the number of light receiving elements (for example, in the light receiving element row 3A).
The central processing unit 6 includes correction value memories _61A 1 to 61A o and _{61B 1} that receive digital signals x _1,1 to x _o,1 corresponding to the dark levels of the n light receiving elements of the light receiving element arrays 3A and 3B, respectively. ~61B _o , and n digital signals for focus detection obtained by integrating the subject image for each light receiving element row 3A and 3B _x1,2 ~x _o,2
memories 62A ₁ to 62A _o and 62B ₁ to 62B _o , respectively, and a digital signal x _n,2 (1≦m≦n) for each element for focus detection corresponding to the dark level _. Operation x _n to subtract ₁
-x _n , ₂ , -x _n,1 correction calculation unit 63
and the absolute value D _k ′ of the difference between the digital signals of the adjacent light receiving elements for each light receiving element and the x memory 64 that receives the result x _n (however, ₁ ≦≦
n-1), a D _k ' memory 66 that takes in the result, a comparison unit 67 that compares successive D _k ' values, and a D _k ' calculation unit 65 that calculates the D _k ' values. Absolute value memory 68 that sequentially stores up to N
₁ to 68 _N , and an addition unit 69 that calculates evaluation values S _A and S _B by adding the values of D ₁ ' to D _N ' for each light receiving element row, and compares these evaluation values to determine the in-focus state. a unit selector 71 that selects the correction calculation unit 63, the _Dk ' calculation unit 65, the comparison unit 67, the addition unit 69 and the focus detection unit 70, and these units 63, 65. , 67, 69 and 70
an instruction decoder 72 that provides operation instructions to the
and the above various memories 61A ₁ to 61A _o , 61B ₁
~61B _o , 62A ₁ ~62A _o , 62B ₁ ~62B _o ,
64, 66 and 68 ₁ to 68 _N , and also the unit selector 71 and instruction decoder 72.
and a controller 73 for controlling the controller. In addition,
Digital memory 42 configuring the A/D conversion circuit 5
₁ to _42o are controlled by a controller 73 via an address bus 46 and an address decoder 47. Further, D _k ' for calculating the evaluation value S is obtained by digital processing, and this value corresponds to D _k of the above-mentioned evaluation function.

Correction value memory 61A ₁ ~ 61A _o , 61B ₁ ~ 61
B _o and memory 62A ₁ to 62A _o , 62B ₁ to 62
Since the loading of data into B _o is clear from the above explanation, the focus detection operation after required data is loaded into these memories will be explained in order below. In addition, various units 63, 65, 6
7, 69, and 70 operate in response to signals from both the unit selector 71 and the instruction decoder 72, and thereby take in data on the data bus and perform a predetermined operation, and transfer the results to the data bus. Send upward.

The focus detection signal _x2,1 is sent from the memory _62A1 to the data bus and taken into the correction calculation unit 63.

A digital signal _x1,1 corresponding to the dark level is sent from the correction value memory _61A1 to the data bus and taken into the correction calculation unit 63.

In the correction calculation unit 63, x ₁ = x _1,2 −
Calculate x _1,1 and send the result to the data bus.

x ₁ is stored in the x memory 64.

Repeat the steps ~ above to transfer x ₂ (=
x _2,2 −x _2,1 ). However, the signals x _2,2 and x _2,1 to obtain x ₂ are stored in the correction value memory 61.
A ₂ and memory 62A ₂ respectively.

D _k 'Calculation unit 65 is activated to take in x ₂ .

Access x memory 64 and send x ₁ to data bus
Send out.

D _k 'x ₁ is taken into the calculation unit 65.

x ₂ is stored in the x memory 64.

D _k ′ Activates calculation unit 67 and calculates D ₁ ′=|
Calculate x ₂ −x ₁ | and send the result to the data bus.

D ₁ ′ is stored in D _k ′ memory 66.

D ₁ ′ is stored in the absolute value memory 68 ₁ .

Repeat ~ above to get D ₂ ′=｜x ₃ −x ₂ ｜
D _k 'Stored in memory 66. At this point, D ₁ ' is stored in the absolute value memory 68 ₁ .

D _k ′ to comparison unit 67 D ₂ ′ from memory 66
and transfer the absolute value memory 68 ₁ to D ₁ ′
are transferred, their sizes are compared, and the results are sent to the controller 73.

When D ₂ ′>D ₁ ′, it is stored in the absolute value memory 8 ₁ under the control of the controller 73.
Transfer (shift) D ₁ ' to the absolute value memory 68 ₂ ,
D ₂ ' stored in the D _k ' memory 66 is transferred to the absolute value memory 68 ₁ . Further, when D ₂ ′≦D ₁ ′, D ₂ ′ stored in the D _k ′ memory 66 is stored in the absolute value memory 68 ₂ .

Repeat ~ above to get D ₃ ′=｜x ₄ −x ₃ |
D _k 'Stored in memory 66.

Compare D ₃ ′ with D ₁ ′ and D ₂ ′ stored in absolute value memories 68 ₁ and 68 ₂ , and if D ₃ ′>[contents of absolute value memory 68 ₁ ], controller 7
The contents of the absolute value memories 68 ₁ and 68 ₂ are transferred to the absolute value memories 68 ₂ and 68 ₃ via _the
Store D ₃ ′. When D ₃ ′≦[contents of absolute value memory 68 ₁ ], next D ₃ ′ and [contents of absolute value memory 68
If D _{3 ′} > [contents of absolute value memory 68 _{2], shift the contents of absolute value memory 68 2} to 68 ₃ , store D _{3 ′} in 68 ₂ , and D ₃ ′
When ≦[contents of absolute value memory 68 ₂ ], D ₃ ' is stored in absolute value memory 68 ₃ .

By repeating the above operations, the correction value memories 61A ₁ to 61A _o and the memories 62A ₁ to 62A _o
Process all the captured data. At the end of this data processing, D _k ′ (1≦k≦n
-2) are stored in the absolute value memories 68 ₁ to 68 _N in descending order of value.

Next, the data from the absolute value memories 68 ₁ to 68 _N are transferred to the addition unit 69 and added to the light receiving element array 3.
The evaluation value S _A - _N 〓 ^k=1 D _k ' at A is calculated and the result is transferred to the focus detection unit 70.

The data stored in the correction value memories 61B ₁ to 61B _o and the memories 62B ₁ to 62B _o are
The light receiving element array 3 is processed by the same operation as above.
The evaluation value S _B at B is calculated and the result is transferred to the focus detection unit 70.

〓〓 The focus detection unit 70 calculates S _A - S _B ,
The result is supplied to the controller 73. In this example, the in-focus state is reached when S _A −S _B =o, and S _A −S B =o.
When S _B >o, the front pin is in the front pin state, and when S _A −S _B <o, the rear pin state is achieved.

In the above example, as a method of evaluation calculation, when signals from adjacent light receiving elements are corrected, the absolute value of the difference is calculated, and the Nth value from the larger one is selected, the absolute value memory 68 is used. ₁ to 6
Although the values stored in _8N are compared with the values stored in the _Dk ' memory 66 in ascending order, the comparison may be made in reverse order starting from the smallest.
In this case, the above calculation method may be changed as described below.

D ₃ ′ is compared with D ₁ ′ and D ₂ ′ stored in the absolute value memories 68 ₁ and 68 ₂ , and when D ₃ ′>[contents of the absolute value memory 68 ₂ ], D ₃ ′ and the absolute The contents of the value memory 68 ₁ are compared, and when D ₃ ′ > [content of the absolute value memory 68 ₁ ], the contents of the absolute value memories 68 ₁ and 68 ₂ are transferred to the absolute value memories 68 ₂ and 68 ₃ via the controller 73, Absolute value memory 68 ₁
Store D ₃ ′ in . D ₃ ′≦ [Absolute value memory 68 ₁
], the contents of the absolute value memory 68 ₂ are transferred to the absolute value memory 68 ₃ via the controller 73, and D ₃ ' is stored in the absolute value memory 68 ₂ . When D ₃ ′≦[contents of absolute value memory 68 ₂ ], D ₃ ′ is stored in absolute value memory 68 ₃ .

In this way, when the absolute value memories 68 ₁ to 68 _N contain values, the value of D _k ' and the absolute value memory 68
8 _N and D _k ′＞[Absolute value memory 68 _N
], D _k ′ is the absolute value memory 68 _N-1 , ..., where the values are stored in order from the smallest value to the largest value.
68 Compare with the absolute value of ₁ , D _k ′≦ [Absolute value memory 6
8 ₊₁ , where 0≦≦N-2], the absolute value memory 68 is stored via the controller 73.
₁ ~ 68 The contents of _N-1 are stored in absolute value memory 68 _-1 ~ 68
The value of D _k ' is stored in _{the absolute value memory 68 l .} This calculation method of comparing in order from the smallest one has the advantage of being able to calculate quickly when the number of light receiving elements is large compared to N.

According to the embodiment described above, the output analog information of all the light receiving elements of the light receiving element rows 3A and 3B is simultaneously sampled and held based on the signal from which the OR circuit 44 is activated. Highly accurate focus detection can be performed even when the lens 3B moves relative to the lens 3B. Also, AND
Since the output of the digital signal that changes sequentially within a predetermined range is stopped by the signal activated by the circuit 43, the sampled and held analog information can be A/D converted in a short time.

Note that the present invention is not limited to the above-mentioned examples, and can be modified or modified in many ways.
For example, the digital signal sent from the counter 41 is not limited to 4 bits, but may be greater than this to further improve the accuracy of A/D conversion. Further, the counter 41 can be built into the central processing unit 6 as hardware, and configured to send a required digital signal from the central processing unit 6 to the D/A converter 40. Furthermore, in the example described above, the two light receiving element rows 3A and 3B are arranged before and after the position optically equivalent to the intended focal plane of the photographic optical system 2, but the two light receiving element rows 3A and 3B are arranged before and after the position optically equivalent to the intended focal plane of the photographic optical system 2. It is also possible to detect a focused point by arranging two or more light-receiving element arrays each consisting of one or more light-receiving elements arranged sparsely and densely thereon. Further, the timing for sampling and holding the output analog information from all the light receiving elements of the light receiving element rows 3A and 3B is determined by using the OR circuit 44 without using the flip-flop 45.
Alternatively, instead of using the OR circuit 44 and the flip-flop 45, another counter controlled by the central processing unit 6 may be provided, and this counter can be used to calculate the predetermined time. It can also be configured to hold the sample after the elapsed time. The same applies to sample and hold of correction values. Furthermore, in the above example, the sending of digital signals from the counter 41 is stopped when the AND circuit 43 is activated, but this AND circuit 43 is omitted and all digital signals within a predetermined range are sent out. Good too. In this way, the circuit configuration can be further simplified. In addition, the range of digital signals for the output analog image information for focus detection from all light receiving elements is determined, and within this determined range, a digital signal that changes sequentially within a predetermined range is sent out to generate the analog image. It is also possible to configure the information to be A/D converted. That is, for example
The OR circuit 44 samples and holds all the analog image information at the same time by making the digital signal of a constant value sent out when timing the sample and hold correspond to the maximum value of the analog image information, and then outputs the AND signal to the D/A converter 40. Until the circuit 43 is activated, digital signals of different predetermined numerical values are sequentially sent out to determine the digital signal corresponding to the minimum value of all sampled and held analog image information, and then a predetermined value within this determined range is determined. A number in the range, "1111" to "0000" in the example above
is sequentially changed from larger to smaller or from smaller to larger, and sent to the D/A converter 40 to A/D convert all the sampled and held analog image information. In this way, the A/D conversion range of the maximum value and minimum value of all sample-held analog image information is determined, and the digital signal within a predetermined range is sequentially changed within this determined range to perform A/D conversion. By performing D conversion, the in-focus point can be detected with even higher accuracy even for subjects with weak contrast. Furthermore, AND circuit 43 and OR circuit 4
4 can be constructed from various logic circuits using comparators and adder circuits. Further, the AND circuit 43 can be configured to detect that the outputs of the comparators up to a predetermined number are inverted.
In this way, for example, the A/D converter for analog image information up to the predetermined number N can be evaluated using the evaluation function S= _N 〓 ^k=1
a _k (however, a _k is the A/D conversion value of the k-th analog image information from the maximum value), when calculating by substituting the analog image information smaller than a _N
Processing speed is further increased because only necessary analog image information is A/D converted without being A/D converted outside the conversion range. Furthermore, although not shown in the drawings, the large number of light receiving elements constituting each light receiving device can be arranged in various arrangements, such as vertically and horizontally arranged in a grid pattern or arranged in concentric circles.
Furthermore, in the above example, all the analog image information of the two light receiving element arrays is simultaneously sampled and held,
This same instantaneous image information is A/D converted in parallel for each light receiving element row, but the two light receiving element rows 3A and 3B are sequentially selected by a signal from the central processing unit 6. The n output analog information of the light receiving element array is held in a sample hold circuit commonly used for the light receiving element arrays 3A and 3B and A/D converted, and then the n output analog information of the other light receiving element array is
It is also possible to detect the in-focus state by holding the output analog information in a sample and hold circuit and converting it from analog to digital. In this case, the sample and hold of the correction value in each light receiving element column and the sample and hold of the image information for focus detection may be performed sequentially, or the correction values of each light receiving element column may be sampled and held in sequence. After A/D conversion, image information for focus detection of each light receiving element array may be sequentially sampled and held and A/D converted. In addition, in FIG. 9, n digital signals for focus detection of each light receiving element row are stored in n memories 62A ₁ to 62A _o , 62B ₁ to 62B _o.
However, these memories are omitted and the data written in the digital memories 42 ₁ to 42 _o is also stored in the correction value memories 61A 1 to 61A _{1 to 42} o in synchronization with the correction values of the corresponding light receiving elements. 61A _o or 61B ₁ to 61B _o to the data bus, and these values can be taken into the correction calculation unit 63 to perform focus detection. Furthermore, the evaluation value for the correction value and the evaluation value for the image information for focus detection may be determined independently, and the true evaluation value corrected for characteristic variations may be determined from the difference between the two to perform focus detection. can. Furthermore, it is not necessary to measure the correction value (dark level) every time a focus detection operation is performed, and the correction value memory 6
The correction values stored in 1A ₁ to 61A _o and 61B ₁ to 61B _o are repeatedly used for an arbitrary or predetermined number of focus detections, and the correction values are measured and updated every arbitrary or predetermined number of focus detections. You can do it like this. Moreover, if there is a sample hold circuit or the like corresponding to the light receiving element, it may be necessary to perform the process only once.

Furthermore, in the above-mentioned example, the shutter 30 with the light emitter 4 attached was selectively interposed in the distance measuring optical path by driving the motor 29, but the mechanism shown in FIGS. It can also be configured so that it is selectively interposed therein.

In FIGS. 10A and 10B, the shutter 30 with the light emitter 4 attached is connected to the camera base 7 on one side.
The string 77 is rotatably connected to a pair of fixing members 76A, 76B provided in the fixing members 76A, 76B.
It is connected to a sliding plate 79 via a string holder 78 installed between them. 10A and 10B show a state in which the shutter 30 is located in the distance measuring optical path, the light emitter 4 emits light, and the correction value of each light receiving element is measured;
0 is rotated clockwise in the figure by the action of a scissor spring 80 provided between the pivot 30A and the fixing member 76B, and the side facing the pivot 30A abuts a stopper 81 provided on the camera base 75. ing. Further, the sliding plate 79 is urged rightward in the figure by the force of a spring 83 disposed between the sliding plate 79 and the fixed member 82, and is brought into contact with the regulating plate 84. When the sliding plate 79 is moved in the direction of the arrow in the figure via the knob 79A against the force of the spring 83, for example in conjunction with the film winding operation, the shutter 30 is moved by the string 7.
7 until it comes into contact with a shutter stopper 85 provided on the fixing member 76A, it rotates approximately 90° counterclockwise in the figure against the force of the scissor spring 80, and
The shutter 30 moves out of the distance measuring optical path. This state is a state in which a focus detection signal of a subject image is obtained, and for example, a configuration can be made in which focus detection is started in conjunction with a shutter release operation. Further, the operation of positioning the shutter 30 in the distance measuring optical path of the balance and causing the light emitter 4 to emit light can also be configured to be performed in conjunction with the shutter release operation.

In FIG. 10, the shutter 30 is held rotatably and selectively interposed in the distance measuring optical path, but the shutter 30 is held slidably and selectively interposed in the distance measuring optical path. It can also be configured as follows.

FIG. 11 shows the configuration of an example of a moving mechanism in which the shutter 30 is slidably held and selectively interposed in the distance measuring optical path as described above, and FIG. 11A shows a plan view. , Figure 11B is the first
FIG. 1 shows a cross-sectional view taken along the - line in FIG. 1A, respectively. A permanent magnet 9 is attached to one side of the shutter 30 that holds the light emitter 4.
1 will be provided. Cut grooves 92A and 92B are formed on opposing sides of the shutter 30, respectively, extending in the sliding direction, and a pair of cut grooves are provided on the camera base 75, extending in the sliding direction via supports 93A and 93B. The shutter 30 is held slidably by being engaged with the guide rods 94A and 94B, respectively. FIG. 11 shows a focus detection state in which the shutter 30 has moved out of the distance measuring optical path and the subject image is projected onto the light receiving element arrays 3A and 3B.
The shutter 30 is biased rightward in FIG. 11A by a tension spring 96 installed between
It is in contact with B. On the other hand, in FIG. 11A,
On the left side of the distance measuring optical path, a magnetic body 99 with a coil 98 wound thereon is provided on the camera base 75 so as to face the permanent magnet 91. By supplying current, the permanent magnet 91 and therefore the shutter 30 are pulled by the spring 96.
Shutter 3 by sliding it to the left against the force of
0 is interposed in the distance measuring optical path to cause the light emitter 4 to emit light.

As explained in detail above, in the present invention,
The light receiving element array is uniformly illuminated from the front of the light receiving element array, the output of each light receiving element is stored, and image information of each light receiving element corresponding to the light intensity distribution of the object image is generated based on the stored value. Since it is a correction, the circuit configuration can be made simple and inexpensive, and
Variations in characteristics of individual light receiving elements can be effectively corrected. Therefore, even when the contrast of the object image is low, the focus can always be quickly detected with high accuracy without causing erroneous detection of focus, and the object of the present invention can be effectively achieved.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the conventional method of correcting variations in characteristics of light-receiving elements;
The figure is a block diagram showing the configuration of an example of a focus detection device that performs the camera focus detection method according to the present invention, and FIG. 3 is a light receiving element array when the device shown in FIG. 2 is applied to a single-lens reflex camera. A line diagram showing an example of the arrangement of
FIG. 4 is a block diagram showing a detailed circuit configuration of one row of the light-receiving element row, A/D conversion circuit, and central processing unit shown in FIG. 2, and FIG. 5 is a block diagram showing the light-receiving element row shown in FIG. FIG. 6 is a circuit diagram showing a detailed configuration of an example of the sample and hold circuit portion; FIG. 6 is a circuit diagram showing a specific configuration of a peripheral circuit corresponding to one light-receiving element section shown in FIG. 5; FIGS. 7A to D 5 is a waveform diagram for explaining the operation of FIG. 5, FIG. 8 is a diagram showing the relationship between the dark level and the output analog information of each light-receiving element sampled and held in the embodiment shown in FIG. 4, and FIG. The figure is a block diagram showing a more detailed circuit configuration of the central processing unit shown in FIG. FIG. 7 is a diagram showing the configurations of two other examples of the configuration. 1...Subject, 2...Photographing optical system, 3, 3A,
3B...Light receiving element array, 3A ₁ to 3A _o , 3B ₁ to 3B _o
... Light receiving element section, 4 ... Light emitter, 5 ... A/D conversion circuit, 6 ... Central processing unit, 7 ... Correction value reading unit, 8 ... Image information reading unit, 9 ...
Correction calculation unit, 10... Focus detection unit,
11...Controller, 12...Display device, 13
...Optical system drive circuit, 14...Optical system drive device,
21... Film, 22... Quick return mirror, 23, 27... Half mirror, 24... Focusing plate, 25... Pentaprism, 26, 28...
... Reflection mirror, 29 ... Motor, 30 ... Shutter, 31 ... Drive circuit, 38A ₁ to 38A _o , 38
B ₁ ~38B _o ... Sample hold circuit, 39 ₁ ~
39 _o ...Comparator circuit, 40...D/A converter, 41...Counter, 42 ₁ to 42 _o ...Digital memory, 43...AND circuit, 44...OR circuit, 45...Flip-flop, 46... ...Address bus, 47...Address decoder, 50A ₁ ~
50A _o , 50B ₁ ~ 50B _o ... Switch, 51A ₁
~51A _o , _51B1 ~51B _o , _52A1 ~52A _o ,
52B ₁ ~52B _o ...Batsuhua, 53A ₁ ~53
A _o , 53B ₁ ~ 53B _o , 54A ₁ ~ 54A _o , 54
B ₁ ~ 54B _o ... gate, 55A ₁ ~ 55A _o , 55
B ₁ ~55B _o ... Capacitor.

Claims (1)

[Scope of Claims] 1. Projecting at least a common portion of an image of an object formed by an optical system onto an array of light-receiving elements to obtain image information corresponding to the light intensity distribution of the object image from each light-receiving element,
In a camera focus detection method that calculates the image information based on a predetermined evaluation function to detect a focused state of an object image, the light receiving element array is uniformly illuminated from in front of the light receiving element array and each What is claimed is: 1. A focus detection method for a camera, comprising: storing the outputs of each of the light receiving elements, and correcting image information of each of the light receiving elements corresponding to the light intensity distribution of an object based on the stored values.