JPH0416995B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a television signal receiving device subjected to band compression processing, and in particular, it reduces the signal bandwidth by interframe sub-Nyquist sampling, and This invention relates to a television signal receiving device in which a synchronized horizontal synchronizing signal and a synchronizing signal for synchronizing frames equivalent to two horizontal scanning periods within a vertical retrace period once per frame are transmitted together with an image signal. It is something.

Conventional technology When transmitting wideband image signals such as high-definition television signals, a method for reducing the signal bandwidth by sub-Nyquist sampling was proposed by the Japan Broadcasting Corporation in ``Television Society Technical Report TEBS95-2''. (Multiple Sub-Nyquist Sampling Encoding Multiple
It was proposed as a Sub-Nyquist Sampling Encoding method. This method is called a motion-compensated multiple sub-Nyquist sampling transmission method, and in detail, the sampling phase is offset between fields and frames, and processing is performed such that the sampling phase goes around in four fields. It transmits signals in analog form.
In addition, in this method, it is necessary to sample and digitize the input analog signal and supply a sampling clock signal (hereinafter abbreviated as clock signal) for digitally processing the video signal inside the receiver. This clock signal must be phase-locked to the input synchronization signal.
Therefore, it is necessary to reproduce this clock signal inside the receiver. As mentioned above, the MUSE system is an analog sample value transmission system, so if the resample clock phase on the receiver side shifts, waveform distortion occurs, resulting in ringing that appears on the screen and causes image quality deterioration. In order to minimize the above image quality deterioration, it is necessary to quickly return the phase-drifted resample clock to its normal phase.

Conventional examples related to the present invention will be described below with reference to the drawings. Figure 2 shows the conventional
This figure shows a clock signal regeneration circuit in the MUSE system.

A synchronization signal for synchronizing the frame with the horizontal synchronization signal (this is defined as a frame pulse, and is referred to below as
A television composite video signal containing FP (abbreviated as FP) is input from an input terminal 1 and supplied to a frame pulse point detection circuit 2 and a phase error detection circuit 3. The frame pulse point detection circuit 2 detects the FP in the input composite video signal, and also detects the frame pulse point (hereinafter abbreviated as FPP) synchronized with the clock signal transmitted via the signal line 4, and compares the phase. At the same time, a signal with a horizontal scanning period synchronized with the FPP is sent to the phase error detection circuit 3. Note that the circuit of this conventional example is entirely composed of digital circuits, so it includes a frame pulse point detection circuit 2 that operates at the sampling clock cycle, a phase error detection circuit 3, an N _-1 counter 5,
Phase comparison circuit 6, digital low-pass filter 9
are all voltage controlled oscillators (hereinafter abbreviated as VCO)
It is clear that the output clock signal generated at 8 is supplied via signal line 4.

As described in Japanese Patent Application Laid-open No. 59-221091, the phase error detection circuit 3 detects a value twice the signal level of the current sample point of the input composite video signal, two sample points before the current one, and two sample points after the current one. The difference from the value obtained by adding the signal levels is constantly calculated, and the signal sent from the frame pulse point detection circuit 2 corresponds to each horizontal scanning period at a fixed position in the horizontal synchronization signal period of the composite video signal. The phase error signal is extracted. The phase error signal is integrated by a digital low-pass filter 9 and fed back to the VCO 8.

On the other hand, the frame pulse point detection circuit 2 detects the FPP signal (hereinafter referred to as the detected FPP signal) in the FP included in the input composite video signal, and the _N
By frequency-downgrading the oscillation output clock signal having the standard clock period of VCO8, a signal whose frequency is equivalent to the detected FPP signal (hereinafter referred to as internal
(referred to as FPP signal). Phase comparison circuit 6
The phase difference between the detected FPP signal and the internal FPP signal is determined, and the up/down counter 7 is operated in the direction of zeroing the phase difference between the two signals in a frame period using the output signal of the phase comparator circuit 6. The output signal is converted into a voltage value, which controls the VCO 8 to control the phase of the clock signal.

The former loop composed of the phase error detection circuit 3, digital low-pass filter 9, and VCO 8 is a so-called phase lock loop (hereinafter abbreviated as PLL).
The latter circuit constitutes an offset phase adjustment circuit. Using a crystal controlled VCO
In the clock regeneration method that constitutes the PLL, a residual phase offset constantly occurs in the regenerated clock signal. If the loop gain is increased to such an extent that the residual offset can be ignored, the loop control system will become unstable, so in this case, first operate the offset phase adjustment circuit until the PLL is within the range where synchronization can be pulled in, and then adjust the pull-in range. Processing is performed to bring the large phase shift outside the synchronization range back within the range, and PLL control is performed within the synchronization pull-in range.

Problems to be Solved by the Invention The conventional clock signal regeneration circuit controls the clock frequency in the horizontal scanning period using the horizontal synchronization signal included in the composite video signal, and also controls the FP transmitted once per frame. This is used to control the clock phase. Since the FP is sent only once per frame, phase control can only be performed at intervals of the frame period. Therefore, the phase control can be performed only at intervals of the frame period from a state where the clock signal frequency is significantly deviated to a state where the clock signal returns to the locked state. The problem was that it required a considerable amount of time to be controlled.

Means for Solving the Problems In order to solve the above problems, the present invention includes a phase error detection circuit that detects a phase error of a synchronization signal included in an input video signal, a low-pass filter that integrates this phase error, A phase lock loop is formed from an oscillator that generates a clock signal whose phase is controlled according to the phase error, and
a frame pulse point detection circuit that detects a frame pulse point from a synchronization signal included in an input video signal;
first and second signal generation means for counting clock signals to generate a signal of a predetermined period; a phase comparison circuit for comparing the phase of the frame pulse point with the phase of the output signal of the first signal generation means; and a clock frequency and a switch for selecting either the output signal of the second signal generating means or the output signal of the phase comparator circuit based on the detection signal.

Effect If the phase of the clock signal is significantly shifted compared to the input synchronization signal and the clock frequency is outside the specified range centered on the phase lock state, the output clock phase must be adjusted within the range where synchronization by the PLL is possible. This method uses a method that uses a combination of precise control of the offset phase of the clock signal and frequency control using a PLL, resulting in an even shorter synchronization pull-in period than the conventional example. This makes it possible to obtain a clock signal whose phase is synchronized with the input synchronization signal.

Examples Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a clock signal reproducing device according to the present invention.

A television composite video signal containing a horizontal synchronizing signal and FP is input from an input terminal 1 and supplied to a frame pulse point detection circuit 2 and a phase error detection circuit 3. The frame pulse point detection circuit 2 detects the FP in the input composite video signal, and also detects the FPP in synchronization with the clock signal input via the signal line 4.
is detected and sent to the phase comparator circuit 6, and
A signal with a horizontal scanning period synchronized with the FPP signal is sent to the phase error detection circuit 3. This signal is a gate signal for extracting a phase error signal at a fixed position corresponding to each horizontal scanning period while the phase error detection circuit 3 constantly obtains a phase error for each sampling clock. It should be noted that the circuit of this embodiment is entirely composed of digital circuits like the circuit of the conventional example, so it includes a frame pulse point detection circuit 2, a phase error detection circuit 3, and an N _-1 counter 5 that operate around the sampling clock. , phase comparator circuit 6,
The digital low-pass filter 9, the N _binary counter 11, and the frequency detection circuit 12 are all supplied with an output clock signal generated by the VCO 8 via the signal line 4.

The phase error detection circuit 3 calculates the difference between a value twice the signal level of the current sample point of the input composite video signal and a value obtained by adding the signal levels of two sample points before and two sample points after the current one. Only the phase error signal at a predetermined position is extracted based on the signal supplied from the frame pulse point detection circuit 2.

On the other hand, an internal FPP signal whose frequency is equivalent to the detected FPP signal obtained by the frame pulse point detection circuit 2 is generated by the N1 _- ary counter 5, and the phase difference between the detected FPP signal and the internal FPP signal is determined by the phase comparison circuit 6. In addition, independent of the above circuit, N _binary counter 1 is output from the clock signal supplied from VCO8.
1 counting cycle shorter than the frame period,
For example, a signal having a field period is created.

Here, as shown in FIG. 3, f _CK + α, f _CK is located outside the PLL pull-in range with the desired reproduction clock frequency f _CK as the center, and has an offset α of positive and negative values.
The frequency −α is defined as a boundary, and the outside of the boundary is defined as a first frequency range, and the inside of the boundary is defined as a second frequency range with _fCK as the center. A frequency detection circuit 12 determines whether the oscillation clock frequency output from the VCO 8 is included in the first frequency range or the second frequency range.
Detect with.

Detection detected by frame pulse point detection circuit 2
FPP signal and N Internal FPP generated in _hexadecimal counter 5
If the phase difference with the signal is large and the frequency detection circuit 12 determines that the oscillation clock frequency at that time is within the first frequency range, the switch 13 is switched to select the signal on the a side, and the frame The up/down counter 7 is operated at high speed using the output of the N _binary counter 11, which has a counting cycle shorter than the period, as a trigger, and the oscillation clock frequency is set to the second one by applying a phase error voltage to the VCO 8.
Control works in the direction of convergence within the frequency range. When the oscillation clock frequency falls within the second frequency range, the frequency detection circuit 12 causes the switch 13 to select the b side signal, and as in the conventional example, the output of the phase comparator circuit 6 is used as a trigger to detect the signal at the frame period. The up/down counter 7 is operated. Specifically, the up/down counter 7 works to decrease the count value when the frequency of the output clock signal is higher than the desired frequency, and to increase the count value when it is lower than the desired frequency. to work. The output signal of the up/down counter 7 is converted into a voltage value and applied to the VCO 8 as a phase error voltage to control the phase of the clock signal.

By the procedure described above, an output clock signal whose phase is completely synchronized with the input synchronization signal is obtained from the output terminal 10. In the conventional method, when adjusting the residual offset phase of the oscillation clock signal, the phase comparison result of the FPP signal is used regardless of the degree of phase drift, so phase control using an up/down counter can only be done in the frame period. However, in the present invention, if a phase drift of the oscillation clock signal occurs and the frequency deviates significantly from the desired value, the frequency will first be lower than the frame period until it falls within the predefined boundary value. By operating the up/down counter with a short period signal, it is brought into the pull-in range at high speed, and after the clock frequency falls within the boundary value, the detection FPP is activated.
By performing precise phase control of the oscillation clock signal based on the phase comparison results between the oscillation clock signal and the internal FPP, and frequency control using the PLL, it is expected that the offset phase adjustment of the oscillation clock signal will be faster.

Effects of the Invention As is clear from the above explanation, according to the present invention, in the system clock regeneration control method on the receiver side of the analog sample value transmission method,
The oscillation frequency of the output clock signal generated by the VCO is monitored, and as a quick recovery method when the phase of the oscillation clock signal deviates significantly from the desired value, the frequency range is divided by a predetermined boundary value, and the clock frequency is By controlling the VCO using a high-speed phase control method until the phase falls within a predetermined boundary value, the speed of offset phase adjustment can be improved, which has a great practical effect.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a clock signal reproducing device according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional clock signal reproducing device, and Fig. 3 shows the reproduction frequency of an oscillating clock signal, and the division of the frequency and frequency range. FIG. 3 is a diagram showing a relationship with a threshold value for 1...Input terminal, 2...Frame pulse point detection circuit, 3...Phase error detection circuit, 5...N _binary counter, 6...Phase comparison circuit, 7...Up/down counter, 8...Voltage controlled oscillator (VCO),
9...Digital low-pass filter, 10...Output terminal, 11...N _binary counter, 12...Frequency detection circuit, 13...Switch.

Claims (1)

[Claims] 1. A clock signal reproducing device that generates a basic clock for a signal processing circuit by synchronizing the output signal of an oscillator that oscillates at a clock period with a synchronization signal included in a transmitted television video signal, and which generates a basic clock for a signal processing circuit, and A phase lock loop is constructed from a phase error detection circuit that detects a phase error of a synchronization signal included in the clock, a low-pass filter that integrates this phase error, and an oscillator that generates a clock signal whose phase is controlled according to the phase error. In addition, a frame pulse point detection circuit detects a frame pulse point from a synchronization signal included in an input video signal, first and second signal generation means for counting clock signals to generate a signal of a predetermined period, and a frame pulse point detection circuit. a phase comparison circuit that compares the phase of the output signal of the first signal generation means with the phase of the output signal of the first signal generation means, a frequency detection circuit that detects the clock frequency, and an output signal of the second signal generation means according to the output of the frequency detection circuit. and a switch for selecting one of the output signal of the phase comparator and the output signal of the phase comparison circuit, and the oscillator is controlled by the phase lock loop according to the signal selected by the switch.