JPH0535958B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a MUSE type television receiver.

[Conventional technology]

Research and development of high-definition television is nearing the stage of practical use. MUSE (Multiple Sub-Nyquist
The Sampling Encoding method is a method developed by the Japan Broadcasting Corporation, which encodes high-definition television signals with a baseband bandwidth of approximately 30 MHz to approximately 8M
Bandwidth compression to Hz bandwidth. In the MUSE method, one screen is completed with four fields due to the above-mentioned subsampling. On the receiver side, 1 from the sent signal
A frame memory is required to create a screen, and interpolation is performed by writing every other sample to the frame memory using a subsample control code sent superimposed on the vertical blanking period. .

[Problem that the invention seeks to solve]

When writing to the frame memory above,
PLL that regenerates the receiver's system clock
If the circuit goes out of lock state due to a disturbance, an error in extracting the subsample control code will occur, and the subsample pattern in the frame memory will remain, resulting in a double screen and significantly deteriorating the subjective evaluation. Conventionally, there was no special processing to deal with the unlocked state of the PLL circuit.

In view of the above-mentioned circumstances, an object of the present invention is to obtain high-definition image quality as a high-definition television.
Even if the PLL circuit becomes unlocked,
An object of the present invention is to provide a MUSE type television receiver having means for preventing deterioration of image quality.

[Means for solving problems]

In MUSE television receivers, the PLL circuit that generates the system clock (transmission sampling rate 16.2MHz) uses the horizontal synchronization signal detected from the HD (horizontal drive) waveform by the horizontal synchronization detection circuit of the timing signal regeneration system. Forms a phase-locked loop for input.

The receiver of the present invention includes the horizontal synchronization detection circuit and
The unlocked state of the PLL circuit is
Means for detecting a phase mismatch between the horizontal synchronization signal and a window signal generated from a frequency-divided signal of the system clock, and means for generating an unlock signal in the case of the mismatch, are provided, and a motion adaptive type of data signal system is provided. The still area/moving area interpolation mixing circuit is provided with means for controlling mixing using the unlock signal. When the unlock signal is active, all of the mixing circuits are subjected to dynamic region interpolation processing.

[Effect]

The deterioration of the screen when the PLL circuit is in the unlocked state is mainly due to image duplication, so to prevent duplication, frame interpolation can be stopped and processing within the field can be performed.
In the MUSE method, the signal data is interpolated into a static region and a moving region, and the ratio is controlled by a mixing circuit using motion detection. Therefore, if the mixing circuit is controlled so that when the PLL circuit enters the unlocked state, the processing is forced into the dynamic region within the field, the double pattern will not occur. Although some deterioration in image quality cannot be avoided, the ease of viewing is significantly improved.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. The circuit block diagram of FIG. 1 shows a timing signal reproduction system and a data signal system. The data signal system is divided into a motion system interpolation filter 21 and a stationary system interpolation filter 22 for data processing.

The outputs of the interpolation filters 21 and 22 are input to a motion adaptive static area/moving area interpolation mixing circuit 27 (hereinafter referred to as mixing circuit), and the mixing ratio is determined using the ROM 24 based on the output of the motion detection circuit 26. control. In this embodiment, the ROM 24 further stores an unlock signal 20 that becomes an antique low when the PLL circuit 20 (described later) enters an unlock state.
1. That is, the unlock signal 20
1, only the dynamic area interpolation signal is outputted by the mixing circuit 26. Mixing circuit 2
The output of 6 passes through the interfield interpolation circuit 28,
Output as TCI signal.

The timing signal regeneration system consists of a horizontal synchronization detection circuit 12 that detects a horizontal synchronization signal from the HD waveform, and a PLL circuit 20 that generates a system clock 202 (16.2MHz) in phase synchronization with the detected horizontal synchronization signal. . In the following, all horizontal synchronization will be abbreviated as HD. In this embodiment, the HD detection circuit 1
2. The PLL circuit 20 includes unlock detection means,
An unlock signal generating means is provided. This will be explained below.

The frame pulse 11a detected by the frame pulse detection circuit 11 and the data signal 10a are input to the HD detection circuit 12 from the digital data signal 10a which is the output of the A/D converter 10, and the HD signal is detected from the HD waveform. do. If the phase of this HD signal matches that of a window setting circuit 17a which is an output of an HD window setting circuit 17 (described later), the HD detection circuit 12 generates an HD detection pulse 12a and inputs it to the PLL circuit 20. The PLL controller 13 is a controller that manages the phase of the phase locked loop, and manages the phase relationship between the clock frequency division signal 16a and the input signal 12a. The D/A converter 14 converts the output signal of the PLL controller 13 into an analog signal, and this signal is sent to the voltage controlled oscillator 15.
It controls the frequency of the system clock 202 and sends out the system clock 202. The signal of the voltage controlled oscillator 15 is passed through the frequency divider 16
Divide the frequency by , and divide the frequency to a frequency where the phase can be controlled. This frequency-divided signal 16a is further input to an HD window setting circuit 17, which outputs a window signal 17a of the scheduled phase for HD waveform phase detection, and inputs the window signal 17a to the HD detection circuit 12.

The HD detection circuit 12 detects the digital signal 10a.
When the HD signal extracted from the HD waveform and the window signal 17a match, the signal 12a is output as described above, but the signal 12a also triggers the retrigger mono multivibrator 18 to release the unlock signal 201. is set to “H”. At this time, the ROM 24 is not affected by the signal 201 at all. Note that the pulse signal generated by the retrigger monomultivibrator 18 is made slightly longer than the horizontal synchronization scanning period, and this state is maintained until the next detection operation of the HD detection circuit 12. Now, when the PLL circuit 20 is out of phase synchronization due to some disturbance,
The phase of the window signal 17a generated by the HD window setting circuit 17 no longer matches the phase of the detection synchronization signal of the HD detection circuit 12, and the signal 12
a is not output. Therefore, the output of the retrigger mono-multivibrator 18 does not continue and changes to "L". Therefore, the unlock indicator 19 including the photodiode is lit, the unlock signal 201 goes low, the ROM 24 is controlled, and the mixing circuit 27 is all operated so that the interpolation filter is converted into the dynamic domain. In this way, the PLL circuit 20
When the interpolation filter becomes unlocked, all the interpolation filters operate as a moving region, thereby preventing the image from being duplicated.

〔Effect of the invention〕

As explained above, the PLL circuit that reproduces the system clock is phase-synchronized with the HD signal detected from the HD waveform included in the data signal. When the detected HD signal matches the phase of the window signal set by the frequency division signal of the system clock of the PLL circuit, the HD detection circuit detects the HD pulse.
Input to PLL circuit. When the PLL circuit is unlocked, it will not generate a pulse at the generation phase. Since the HD pulse is also input as a trigger for the retrigger mono multivibrator, the output of the retrigger mono multivibrator is “L” at this time.
Therefore, all the outputs of the mixing circuit are changed to the outputs of the motion interpolation filter. Additionally, the unlock indicator lights up to indicate the unlocked state. In this way, when the PLL circuit loses synchronization with the HD signal due to disturbance, the motion-adaptive static area/moving area interpolation mixing circuit all performs moving area interpolation processing, causing the image to become a double image. can be prevented from happening. The image quality will deteriorate somewhat, but the screen will remain easy to view.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention. 10...A/D converter, 11...Frame pulse detection circuit, 12...HD detection circuit, 13...
PLL controller, 14...D/A converter, 1
5... Voltage controlled oscillator, 16... Frequency dividing circuit, 17
... HD window setting circuit, 18 ... Retrigger mono multivibrator, 19 ... Unlock display, 20 ... PLL circuit, 21 ... Motion system interpolation filter, 22 ... Stationary system interpolation filter, 24 ...
...ROM, 26...Motion detection circuit, 27...Mixing circuit (motion adaptive static area/moving area interpolation mixing circuit).

Claims (1)

[Claims] 1. In a MUSE television receiver, a horizontal synchronization detection circuit for a timing signal reproduction system;
A PLL circuit that generates a system clock in phase synchronization with the detected horizontal synchronization signal determines the unlocked state of the PLL circuit by detecting a phase mismatch between the horizontal synchronization signal and a window signal generated from the divided signal of the system clock. and a means for generating an unlock signal in the case of the mismatch, and a means for controlling mixing using the unlock signal in a motion adaptive static area/moving area interpolation mixing circuit of the data signal system. A MUSE television receiver, characterized in that when the unlock signal is active, all of the mixing circuits perform dynamic area interpolation processing.