JPH0418632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input signal correction circuit. The present invention relates to a signal correction circuit that accurately and quickly detects a downhill position.

[Prior art]

An example of a conventional detection circuit for detecting the rising and falling positions of an input signal is to output a high level when the input signal, which is a supersaturated signal, reaches a predetermined threshold level and use this as the rising position. There are known circuits that stop the high level when the input signal falls below the threshold level and detect this as a falling position, or circuits that make certain corrections to these detected values. However, for example, when the input signal of the supersaturation signal is a width signal for measuring the width of a steel plate during hot rolling, the supersaturation signal will vary in magnitude, that is, its rising angle and falling angle, depending on the temperature of the steel plate, etc. Change. Therefore, even if the supersaturation signal rises from the same position, the position at which it is triggered at a predetermined threshold level changes depending on the temperature of the steel plate, etc., and this causes a measurement error.

There is also a circuit that automatically corrects rising and falling slopes in an analog manner, but this has the problem of slow response speed.

[Object of the Invention] The present invention has been made in view of the above-mentioned problems of the conventional detection circuit for detecting the rising and falling positions of an input signal. It is an object of the present invention to provide a signal correction circuit that corrects the rising and falling positions of an input signal and can accurately and quickly detect the input signal.

[Structure of the invention]

The present invention has the following structural features to achieve the above object. That is, the present invention includes a first threshold circuit that shapes the waveform of an input signal at a first threshold level V _T1 , and a second threshold circuit that shapes the waveform of an input signal at a second threshold level V _T2 higher than the first threshold level V _T1 . a second threshold circuit; a gate circuit that outputs the difference between the output of the first threshold circuit and the output of the second threshold circuit; a first clock pulse generator that generates a first clock pulse with a period _T1 ; and a first clock pulse generator with a period _T2 . a second clock pulse generator for generating a second clock pulse; a first AND circuit for ANDing the output of the gate circuit and the first clock pulse; and the output of the second threshold circuit and the second clock pulse. a second AND circuit for ANDing the output pulses of the first AND circuit;
It has an OR circuit that ORs the output pulses of the AND circuit, and a counting section that counts the output pulses of the OR circuit, and the periods T ₁ and _T2 are T ₂ =V _T2 −V _T1 / It is configured to have a relationship of V _T2 T ₁ . Therefore, even if the rising angle of the input signal changes, by measuring the time between triggers at two different threshold levels using a clock pulse with a different period from other parts, the correct rising position can always be determined. The falling position can be detected using a similar method.

〔Example〕

As shown in FIG. 1, the first and second embodiments of the present invention are employed in a steel plate width detection device 2, etc. for measuring the width _L1 of a strip steel plate 1 moving in a direction perpendicular to the drawing. It is something. Steel plate width detection device 2
The measurement optical axis 4 is swung in the direction of the arrow in FIG. 1 to scan the steel plate 1. Then, the width L ₁ of the steel plate 1 is calculated by detecting the front end 6 and the rear end 8 and counting the clock pulses output within the scanning time from the front end 6 to the rear end 8. .

The first embodiment is an example in which only the tip is detected, and as shown in the block diagram of FIG. 2 and the waveform diagram of FIG. The saturated signal b is input to the first threshold circuit 102 and the second threshold circuit 104. The first threshold circuit 102 is triggered when the oversaturation signal b reaches a predetermined threshold level V _T1 and outputs an output signal c. 2nd threshold circuit 1
04 means that the supersaturation signal b is at the above threshold level.
V Threshold level higher than _T1
When V _T2 is reached, it is triggered and outputs the output signal d.

The first flip-flop 10 receives the output signal c of the first threshold circuit 102 and the synchronization signal e.
6 outputs a square wave gate signal f to the third flip-flop 110, which is set by the rising edge of the output signal c and held until reset by the synchronizing signal e. Second threshold circuit 10
The second flip-flop 108, to which the output signal d of No. 4 and the synchronization signal e are input, outputs the square wave gate signal g, which is set by the rising edge of the output signal d and held until reset by the synchronization signal e, to the third flip-flop 108.
Output to flip-flop 110.

The third flip-flop 110 is set by the rising edge of the gate signal and outputs the corrected gate signal h until it is reset by the rising edge of the gate signal. The first gate 112 has a correction gate signal h
and clock signal i are inputted to obtain a correction pulse signal j. The period _T1 of the clock signal i will be described later. A gate signal g and a clock signal k are input to the second gate 114 to obtain an output pulse signal l. The period _T2 of the clock signal k will be described later. The correction pulse signal j and the output pulse signal l are input to the OR gate 116 and added, and the added output pulse signal m is sent to the counting circuit 11.
8 and is counted.

Next, the relationship between the periods T ₁ and T ₂ of the clock signals i and k will be explained. In Fig. 4, time t is plotted on the horizontal axis, voltage V is plotted on the vertical axis, and oversaturation signals A,
A' and threshold levels V _T1 and V _T2 are shown. The supersaturation signals A and A' are detection signals of the tip of the same steel plate, and the magnitude of the supersaturation signal, that is, the rising angle, differs depending on the temperature difference of the steel plate, etc., but their estimated rising point is O is constant, and the present invention detects this estimated rising point O as the end of the steel plate or the like.

The time it takes for the supersaturated signals A and A' to reach the threshold level V _T1 from the estimated rising point O is t ₀ ,
t ₀ ', and the time to reach V _T2 from threshold level V _T1 is t ₁ , t ₁ ', for oversaturation signal A, V _T2 - V _T1 /t ₁ = V _T2 /t ₀ +t ₁ t ₀ +t ₁ =V _T2 /V _T2 −V _T1・t ₁ . Further, regarding the oversaturated signal A', V _T2 -V _T1 /t ₁ '=V _T2 /t ₀ '+t ₁ 't ₀ '+t ₁ '=V _T2 /V _T2 -V _T1 ·t ₁ '. In other words, the time from the estimated rise point O to the threshold level V _T2 is a constant determined by only the two threshold levels [V _T2 / (V _T2 − V _T1 )], regardless of the rise angle. ,
Time t ₁ to reach threshold level V _T2 from threshold level V _T1
It can be found as the product of

Therefore, when the period of the clock signal k input to the second gate 114 is T2, the first gate 1
Let the period _T1 of the clock signal i input to the circuit 12 be _T1 =V _T2 -V _T1 /V _{T2 T2} . Then, the estimated rising point O can be obtained by counting the corrected pulse signal j and the output pulse signal l, and performing arithmetic processing on this counted value as a clock pulse with a period _T1 . Although the above explanation relates to the rising edge, the falling edge can also be considered in the same way.

The second embodiment is an example in which the leading end and the trailing end are detected, and as shown in the block diagram of FIG. 5 and the waveform diagram of FIG. 6, the input signal a is input to an amplifier circuit 200 and amplified. The oversaturated signal b is then inputted to the first threshold circuit 202 and the second threshold circuit 204. The first threshold circuit 202 is triggered when the oversaturation signal b reaches a predetermined threshold level V _T1 and outputs an output signal c. The second threshold circuit 204 is triggered and outputs an output signal d when the oversaturation signal b reaches a threshold level V _T2 higher than the threshold level V _T1 .

Output signals c and d are input to a first flip-flop 206 and a second flip-flop 208, respectively. The first flip-flop 206 generates a gate signal e that is set on the rising edge of the output signal c and reset on the rising edge of the output signal d, while the second
Flip-flop 208 generates a gate signal f which is set at the falling edge of output signal c and reset at the falling edge of output signal d.

The first AND gate 210 has gate signals e, f.
and clock signal g are input, and a correction pulse signal i is output. The second AND gate 212 receives the output signal c and the clock signal h and outputs an output pulse signal j. The corrected pulse signal i and the output pulse signal j are input to the OR gate 212, and the output pulse signal k added here is input to the counting circuit 214.
is counted.

The periods of the clock signals g and h are determined in the same manner as in the first embodiment. Furthermore, the second embodiment has the advantage that the rising and falling positions of the input signal can be accurately detected without generating a synchronizing signal as in the first embodiment.

〔Effect of the invention〕

Since the present invention is configured as explained above,
By triggering the input signal, the supersaturated signal, at two different threshold levels at its rising and falling edges, and counting the time in between using a clock pulse with a period different from that of the other parts, the supersaturated signal can be detected. This has the effect of allowing accurate rise and fall positions to be detected.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a steel plate width detection device incorporating an embodiment of the present invention, FIG. 2 is a block diagram of the first embodiment of the present invention, FIG. 3 is a waveform diagram of the first embodiment, and FIG. FIG. 5 is a block diagram of the second embodiment, and FIG. 6 is a waveform diagram of the second embodiment. 1... Strip steel plate, 2... Steel plate width detection device, 4...
...Measurement optical axis, 100,200...Amplification circuit, 10
2,202...first threshold circuit, 10
4,204...second threshold circuit, 10
6,206...first flip-flop, 108,
208...second flip-flop, 110...third flip-flop, 116,212...OR gate circuit, 118,214...counting circuit.

Claims (1)

[Claims] 1. A first threshold circuit that shapes the waveform of an input signal at a first threshold level V _T1 , and a first threshold circuit that shapes the waveform of an input signal at a second threshold level V _T2 higher than the threshold level V _T1 . a two-threshold circuit; a gate circuit that outputs the difference between the output of the first threshold circuit and the output of the second threshold circuit; and a first gate circuit that generates a first clock pulse with a period _T1 .
a second clock pulse generator that generates a second clock pulse with a period _T2 ; a first AND circuit that performs an AND operation between the output of the gate circuit and the first clock pulse; an output of a second threshold circuit; a second AND circuit that ANDs a second clock pulse; an OR circuit that ORs an output pulse of the first AND circuit and an output pulse of the second AND circuit; and an output of the OR circuit. and a counting section that counts pulses, and a signal characterized in that the period _T1 of the first clock pulse and the period _T2 of the second clock pulse are in the relationship _T2 = V _T2 - V _T1 /V _{T2 T1.} correction circuit.