JPH042022B2 - - Google Patents

Description

[Detailed description of the invention] (a) Technical field The present invention relates to an optical receiving circuit.

The optical receiving circuit converts the optical signal transmitted through the optical fiber into an electrical signal, amplifies it, shapes the waveform, and
This is a circuit that restores a clean digital waveform.

(b) Prior art and its problems Waveform shaping is to convert a dull pulse into a correct rectangular wave, but it compares the voltage signal with a certain threshold, and if it is larger than this, it is set to H. If it is small, set it to L and create a rectangular wave.

Initially, a fixed threshold was used and compared with a DC amplified signal.

However, when direct current is amplified, there are problems such as offset and fluctuations in offset due to temperature. Also,
There is a limit to the strength of the optical signal that enters the photoelectric converter,
The drawback was that the input dynamic range was too narrow.

Since the intensity of the optical signal does not change in a correct rectangular wave and has a rough waveform, when it is binarized using a fixed threshold, the time when it is H and the time when it is L, Th,
There is a problem that Tl varies depending on the light intensity.

Furthermore, weak input signals smaller than a fixed threshold cannot be sensed.

Therefore, the inventors of the present invention solved this problem by first performing differentiation and then changing the state depending on the edge of the differentiated waveform, instead of using DC amplification.

FIG. 4 is a block diagram of such an optical receiving circuit.

The photodiode PD converts the optical signal transmitted through the optical fiber into a current.

A current-voltage conversion circuit converts this into a voltage signal. These are further amplified by an AC amplifier circuit,
It is now differentiated by a differentiating circuit. The differential waveform has an upward pulse and a downward pulse, and the output of the comparator with hysteresis is changed by these short pulses. When the short pulse is upward, the output of the comparator with hysteresis changes from L to H, and when the short pulse is downward, the output changes from H to L.

However, since it is a differential waveform, the voltage will eventually become equal to the intermediate value. At this time, the comparison voltage of the comparator is shifted by several tens of mV above or below the intermediate value so that the output value does not change even if the voltage reaches the intermediate value.

In such a comparator, the reference voltage is not a constant value but changes up and down. The change in reference voltage is
It is called a comparator with hysteresis because it suppresses changes in the output and maintains the previous state.

These structures are, for example, disclosed in Japanese Patent Application Laid-open Nos. 60-85649, 60-93856, and 60-93856, which were invented by the present inventors.
60-100818, etc., for detailed explanations.

It is an excellent optical receiver circuit with a wide input signal dynamic range, no waveform distortion, and no output fluctuation due to temperature.

However, this circuit had the following drawbacks.

One is that the number of elements that make up the circuit is large, making it expensive.

The AC amplification and differentiation circuit is composed of a capacitor C, a resistor R, a transistor, and the like. Therefore, the circuit is complicated.

In addition, a comparator (IC) is used in the waveform shaping circuit.
Therefore, a hysteresis adding circuit is required. Hysteresis is to apply a voltage of ±Δ with a certain voltage as a reference. In order to switch between positive and negative, the direction of the current flowing through the resistor connected to the input of the comparator is switched.

This requires at least three constant current circuits. Since the characteristics of a constant current circuit are determined by the value of the resistance, strict conditions may also be imposed on the accuracy of the resistance value.

Another drawback is that it uses a differential circuit, so it is susceptible to noise.

(c) Purpose It is an object of the present invention to provide an optical receiving circuit that has fewer elements constituting the circuit and can be manufactured more easily.

A second object of the present invention is to provide an optical receiving circuit that can withstand noise without using a differentiating circuit.

(d) Configuration The optical receiving circuit of the present invention is comprised of a photoelectric conversion element, a current-voltage conversion circuit A, an AC amplifier circuit B, a waveform shaping circuit C, an output buffer circuit D, and the like.

There is no differentiation circuit, which makes it resistant to noise.

Furthermore, since there is no need to use a comparator with hysteresis for binarization, a simpler Schmitt trigger is used to binarize the signal.

The AC amplifier circuit has one feature. this is,
The input and output of the inverter are coupled with a resistor. This makes it a simple AC amplifier circuit.

This will be explained using drawings.

FIG. 1 shows a circuit diagram of an optical receiver circuit of the present invention. FIG. 2 shows only the current-voltage conversion circuit.

A photodiode PD is used as the photoelectric conversion element. The anode of the PD is grounded. The cathode and anode are reverse biased and the light is PD
Once inside, a photocurrent ΔI flows from the cathode to the anode.

The current-voltage conversion circuit A converts a change in photocurrent ΔI into a change in voltage. This consists of transistors Q1, Q2, resistors R1, R2, etc.

The base a of transistor Q1 is connected to the cathode of photodiode PD. The collector b of the transistor Q1 is connected to the power supply Vcc via a small protective resistor R3. collector b
Since is grounded by the capacitor C1, it can be considered as the power supply voltage in terms of AC.

The emitter c of Q1 is connected to the base of Q2. The emitter of Q2 is grounded.

Since Q1 and Q1 are connected in Darlington, the current amplification factor is squared.

The collector d of Q2 is connected to R3 by a resistor R2. Collector d is forward connected to base a of Q1 by diode D1. The collector d is parallel to this and connected to the base a of Q1 by a current detection resistor R1.

The voltage at the collector d of Q2 is the current voltage conversion circuit A.
This is the output of This is simply written as d.

The current amplification factors of Q1 and Q2 are assumed to be β. The base current of Q1 is I1, and the base current of Q2 is I2, Q2.
The emitter current is I3, the collector current is I5,
Let I4 be the current flowing through R1.

Regarding the current at point a, I1 + ΔI = I4 (1) Regarding the currents of Q1 and Q2, I2 = (1 + β) I1 (2) I3 = (1 + β) I2 (3) I5 = βI2 (4). When the collector b of Q1 is written as Vcc, the following equation holds true regarding the voltage d at point d: d=Vcc−R2(I4+I5) (5) d=2V _BE +R1I4 (6). Since the potential at point a is always equal to the base-emitter drop of Q1 and Q2, 2V _BE , (6)
The ceremony takes place.

From these equations, the equation d2V _BE R1ΔI (7) is obtained, assuming that the current amplification factor β is larger than 1 and β≫1.

The voltage at the output d is the photocurrent ΔI of the photodiode
appears as a value R1ΔI, which is obtained by multiplying by R1.

This is a current-voltage conversion circuit.

The reverse bias voltage of the photodiode is V _BE (approximately
0.7V), but since it is a constant voltage, the photocurrent characteristics do not change. Therefore, it is possible to obtain a current with good linear saturation relative to the amount of light.

When the optical signal is large, ΔI becomes large, so d
The voltage at the point is too high. Although this will not exceed Vcc, the output waveform will become saturated.
Since the collector current of Q2 decreases, the base current of Q1 also decreases. This is undesirable since I1, I2, and I3 must be approximately constant values. In other words, there is a risk that the simple equation (7) will no longer hold and waveform distortion will occur.

Therefore, by putting the bypass diode D1 in parallel with R1, the voltage applied to R1 can be reduced to approximately
I try to keep it below 0.7V.

The larger the current detection resistor R1 is, the higher the sensitivity becomes. However, if this value is too large, it will not be possible to follow fast input changes.

In this example, since the optical input signal has a speed of 4 Mbps (4 megabits per second), R1 is set to 50 kΩ, for example. R2=2kΩ. Q1,
A single transistor was used for Q2.

Capacitor C to stabilize Vcc AC
1 is, for example, 0.01 μF.

The above configuration is the same as that already described by the inventors in connection with the above-mentioned optical receiving circuit.

Next, coupling capacitor C2 (e.g.
0.01μF) to AC amplifier circuit B.

Here, three amplification stages are shown. The respective input and output are coupled by coupling capacitors C3 and C4.

Since it is an AC amplification, it seems natural to insert a capacitor between them.

However, the AC amplifier circuit used here is different from that normally used. It does not use operational amplifiers, comparators, or tuned amplification. As such a linear amplifier, an inverter, which is a digital circuit element, is used in the present invention instead of a commonly used analog element.

Inverters are the most commonly used elements in digital circuits. Its function is to invert the input. It is well known to connect multiple stages of inverters to form an oscillator.

However, it has not been known until now to use an inverter as a linear amplifier. This is the original work of the inventor.

With reference to FIG. 3, it will be explained that the inverter can be used as a linear amplifier. The curve in FIG. 3 represents the input/output characteristics of the inverter. The horizontal axis is the input voltage
Vin, and the vertical axis is the output voltage Vont.

When the input voltage is low, the output voltage is at H level. This is a constant voltage and will be written as V _DD . In the figure, it is between ST.

When the input voltage becomes high, the output voltage becomes L level. This is almost OV. This is the part marked X in the diagram.

In reality, the value of the input voltage changes (T→X)
Sometimes, the output voltage does not change immediately from H to L level, and there is a short transition region TUV.

If the inverter operates slowly, the output change from H to L or L to H can be considered to occur instantaneously, but if the input signal changes quickly, such an output change may be regarded as a signal change. It will come to the same extent. Therefore, it is possible to draw input/output characteristics like the diagonal line TUV.

Inverters may have element-specific hysteresis. In other words, the threshold when the input changes from bottom to top is higher than the threshold when the input changes from top to bottom. In this case, it seems that two curves corresponding to TUV can be drawn from top to bottom and from bottom to top, but this is not the case.

Once the output reaches H level or L level, hysteresis is applied, but in the middle, that is, TVU
If the output is fluctuating between

Then, by making the input voltage Vin vibrate up and down around the line Y (corresponding to point U), the output voltage Vout can be obtained as an amplified signal between the TVs.

However, it is necessary to set the DC bias of the input voltage to Y. Y can be considered to be the center of the mutation point where Vin changes from H to L and L to H. This is a value that varies depending on the element. Therefore, with the usual method of connecting a resistor in series between the power supply and ground and dividing the voltage to determine the bias, it is difficult to set the bias correctly at the Y point. If you use a variable resistor, you can make the bias variable, so you can set the DC bias to the Y point, but you have to make adjustments.
It's extremely troublesome.

Even if the input bias is temporarily determined correctly, it may shift due to changes in temperature.

The inventor has discovered that a direct current bias can be correctly applied to the Y point using a simpler method.

It is a high resistance connection between the input and output.

Both the input and output of the inverter are blocked from direct current by capacitors.

For example, a case will be described in which the input f and output g of the inverter 1 are connected through a resistor R4.

The direct current is cut off by capacitors C2 and C3. Current flowing into the inverter from the input,
The current flowing out is almost 0. There are currents that flow into and out of the inverter from the output, but
This always passes through R4 and flows to the input. In the end, R
It can be seen that the algebraic sum of the currents flowing from right to left and from left to right is 0.

Then, the average value of input Vin and output Vout will always be equal.

＜Vout＞＝＜Vin＞ (1) It is.

Since equation (1) holds true, the input and output bias points are equal and have a constant voltage.

Prove this.

If this becomes higher than the constant voltage, the average input voltage will go up and the average output voltage will have to go down, since the inverter will produce the opposite signal.

Therefore, the average voltage of input and output are equal,
Moreover, it becomes a constant value. This constant value is naturally the center Y of the input threshold and the center Y of the output threshold.
V _DD /2.

By utilizing the characteristic that the input and output of an inverter are inverted, it is possible to easily set the input bias to the center of the threshold value correctly.

Point U in the figure provides a bias. Of course Y=
V _DD /2.

When an input signal is input here, the output signal becomes an inverted signal, so it becomes a vibration wave centered on the Z axis in FIG.

Then, amplification equal to the aspect ratio of the steeply sloped TUV, which depends on the characteristics of the inverter, will be achieved.

The amplification factor depends on the slope TUV and does not depend on the resistance.
Whatever the value of the resistance, the bias can be set at point U.

However, if the resistance is small, the input impedance will be small and the input signal itself will be small, so it will not be amplified much.

The larger the value of the bias resistor, the better, but if it is too large, it becomes vulnerable to external noise.

Furthermore, if the amplification factor is too large, waveform distortion will occur in the output if the input signal is already large.

In this example, in order to lower the input impedance of the first stage, R4=50 kΩ and the voltage amplification degree is set low. As an inverter,
When using TC74HCUO4P, the amplification degree is approximately 10dB
That's about it. Further, C2 was set to 0.01 μF.

In the second stage, for example, R
5=1MΩ, C3=0.01μF. With the same element,
The amplification degree was about 20 dB.

The third stage is C4 to avoid waveform distortion.
It is preferable to adjust the voltage amplification degree and band using R6. For example, assume that C4=2.2pF and R6=100kΩ. Although the resistance is large, the coupling capacitor C4 is small, so there is little signal transmission, and the voltage amplification obtained here is about 3 dB.

The AC amplifier circuit is thus a three-stage circuit including three inverters 1, 2, and 3, resistors R4, R5, and R6, and capacitors C2, C3, and C4. AC amplification is performed between f and g, between h and i, and between j and k. Since it is blocked by a capacitor, the DC level of each amplifier stage is determined to the value already mentioned.

Although a three-stage amplifier circuit is shown here, it may be an amplifier circuit in which three or more stages, four stages, or five stages of inverters are arranged.

Next, the waveform shaping circuit C will be explained.

In the present invention, a Schmitt trigger circuit is constructed by connecting two inverters in series and connecting the input and output through a resistor.

The output of the AC amplifier circuit appears at point k. This enters the input m of the inverter 4 via the resistor R7 and capacitor C5. The output n of the inverter 4 is directly connected to the input of the inverter 5. The output p of the inverter 5 is connected to the point m two stages before by a resistor R8.

It is safe when point m and point p are at the same potential.
The operation when C5 is excluded will be explained.

Assuming that the voltage at point k rises from OV, the voltage at point p is also OV, so the voltage at point k (simply written as k) is the voltage at point m (simply written as m).
increases while maintaining the relationship m=R8/R7+R8k (2).

Let Vth be the input threshold of the CMOS inverter 4. When voltage m exceeds Vth, the voltage at point p changes to H level.

When the voltage at point k changes from bottom to top, the voltage at point m also rises, and when this reaches Vth, the output p changes to H level (V _DD ). This change point at point k is written as an upward threshold k (↑). This is given by k(↑)=R7+R8/R8Vth (3). When k exceeds the increased value k (↑), the output changes suddenly.

Assume that points m and p are at H level (V _DD ), and the voltage at point k is decreasing. The voltage at point m is m=R8k/R7+R8+R7V _DD /R7+R8 (4). p= _VDD . The downward threshold seen from point k is set as m = Vth, and k (↑) = R7 + R8 / R8Vth - R7 / R8V _DD (5).

In other words, since the downward threshold is lower than the upward threshold, a hysteresis operation occurs.

Furthermore, by connecting inverters 4 and 5 in series,
Since the input and output are connected by the resistor R8, the change in the p point is made in a very fast time depending on the internal elements of the inverter.

This is a Schmitt trigger circuit because the output p changes rapidly with respect to the input k and is binarized.

An example is shown.

R7=60kΩ, R8=200kΩ, _VDD =5V, Vth=
Set to 2.5V. Since a CMOS inverter is used here, the inverter's Vth is 1/2 of _VDD . However, it does not have to be CMOS.

In this example, k(↑)=3.25V K(↓)=1.75V Therefore, there is a 1.5V difference between the upper and lower thresholds.

Even if the input signal is weak, the amplitude will always be 1.5V or higher after three stages of amplification, so it will be correctly binarized by the waveform shaping circuit.

The upper and lower thresholds are separated from each other with V _DD /2 as the center (in this example, V _DD /2 = 2.5V). R7,R
Even if 8 is changed, the property that the sum of k (↑) and c (↓) is V _DD , that is, the average is V _DD /2, is maintained. This is clear from (3) and (5).

Capacitor C5 is inserted to give the input frequency characteristics. For low frequencies, the difference between the upper and lower thresholds is 1.5V, but for high frequency signals, the threshold difference (k(↑)−k(↓)) is a lower voltage.

The sensitivity is increased for high frequency components, the sensitivity is improved for 4Mdps data, and it is made less responsive to low frequency noise. It acts as a kind of good filter.

With the above circuit, the waveform has been shaped, that is, binarized.

Transistors Q1 and Q2 produce a voltage signal that is in phase with the signal. Thereafter, amplification and waveform shaping processing are completed up to point p, but the number of inverters is five counting from point d. Since the number is odd, the phase of the signal is inverted.

Another inverter 6 is installed to restore the output signal to a phase matching the original signal. At point q, an output wave with the correct phase is obtained.

The output buffer circuit here has one inverter.
There are only individuals. As long as it is an odd number,
It could be 3, 5, etc.

If four stages of AC amplification are used, the output of the waveform shaping circuit C will be in phase with the input. In this case, the output buffers are 0, 2, 4, 6
It can be configured with an even number of inverters such as... The inverter may be zero.

Here we have 6 inverters
Since TC74HCUO4P is used, inverters 1 to 6 can be obtained with one IC, which is convenient.

The output wave is taken out from terminal RD.

Power supply V _CC is applied externally. Capacitor C
7, C8, and inductance L1 are commonly used circuits that stabilize the power supply and prevent noise from entering from the power supply line. For example, these are 10μF,
10μF, 1mH.

Describe the difference between power supplies V _CC and V _DD . V _CC is a voltage applied to the element from the outside. here
Although 5V is used as an example, it is arbitrary. V _DD is the H level of the inverter. Sometimes it is close to and coincides with V _CC , sometimes it is not. Therefore,
These were distinguished.

(e) Effects (1) Since the number of circuit elements is small, it can be constructed at a lower cost than conventional optical receiving circuits.

AC amplification, waveform shaping, and output buffer can be created with a single IC that includes 6 inverters.

Even if the entire circuit is a hybrid IC, the circuit can be configured with this IC, two transistors, and a small capacitor resistance.

(2) Even if the gain of the amplifier section is increased, it will not saturate,
There is no delay in response characteristics due to saturation.

This is because a digital IC (inverter) is used for AC amplification.

(3) Small waveform distortion. Fast response characteristics. This is also because it uses a digital IC. Regardless of the magnitude of the amplitude, the midpoint of the signal (half peak to peak) always coincides with the DC bias point U, so the output changes at the same time regardless of the magnitude of the amplitude.

In the case of DC differential amplification, this does not occur, and waveform distortion occurs.

The resistors R7 and R8 of the waveform shaping circuit determine the magnitude of the difference between the upper and lower threshold values, but this value itself does not have to be strictly defined, so the accuracy requirements for R7 and R8 are not strict.

(4) AC is amplified, but not differentiated. Since there is no differentiation circuit, it is resistant to noise.

(5) Does not require a comparator with hysteresis,
A large number of constant current circuits are not required. The accuracy requirements imposed on the resistance value are not strict.

The feedback resistor of the amplification stage does not directly determine the amplification factor, and strict accuracy is not required.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an optical receiving circuit of the present invention. FIG. 2 is a circuit diagram of only the current-voltage conversion circuit portion of FIG. 1. FIG. 3 is an input/output characteristic diagram illustrating AC amplification by an inverter. FIG. 4 is a configuration diagram of a conventional optical receiving circuit. 1-6...Inverter, C1-C8...Capacitor, R1-R8...Resistor.

Claims (1)

[Claims] 1. An optical data link receiving circuit that transmits binary digital signals is composed of a photoelectric conversion element, a current-voltage conversion circuit, an AC amplifier circuit, a waveform shaping circuit, and an output buffer, and the current-voltage conversion circuit uses a Darlington connection. transistors Q1, Q
2, a resistor R1 and a diode D1 connected between the base of the transistor Q1 and the collector of the transistor Q2, and a resistor R2 connected between the collector of the transistor Q1 and the power supply. It is assumed that the emitter of Q2 is connected between the base and ground, and the emitter of Q2 is grounded. The waveform amplification circuit consists of two inverters 4 and 5 connected in series, a resistor R8 that feeds back the output of the inverter 5 to the inverter 4, and a waveform amplification circuit that feeds the amplified output of the AC amplification circuit to the inverter. 4, and a capacitor C5 connected in parallel to the resistor R7, and an output buffer comprising an inverter to match the phases of the output and input signals.