JPH0420299B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a receiving device, and particularly to a receiving device used in a digital communication system using an error correction code.

[Conventional technology]

First, a general configuration of a conventional receiving device used in a digital communication system using an error correction code will be explained.

Such a receiving device includes a carrier wave regenerator that inputs an input signal modulated by a digital signal, regenerates its carrier wave component, and outputs it as a carrier wave signal; a demodulator that demodulates the input signal based on the reference and outputs it as a baseband signal, a discriminator that identifies and reproduces this baseband signal, and a discriminator that detects and corrects code errors in the output reproduced signal and outputs it as an output signal. It is equipped with an error corrector.

Many error correctors generate error pulses that can be easily extracted externally when a code error is detected. In addition, if it is not easy to extract such error pulses, an exclusive OR circuit (hereinafter abbreviated as EX-OR circuit) is installed in the error corrector.
is added, the input signal to the error corrector is branched and inputted to one of the input terminals of the EX-OR circuit through a delay circuit with an appropriate delay time, and the output signal of the error corrector is branched and outputted to the EX-OR circuit. The configuration is such that an error pulse can be obtained as the output of the EX-OR circuit by inputting it to the other input terminal of the OR circuit, and in either case, the error corrector outputs an error pulse every time a code error is detected. can do.

Now, if the phase of the reproduced carrier signal changes, the reference phase of the demodulator will change. If the reference phase fluctuates and deviates from the optimum value, this is equivalent to a decrease in the energy of the input signal, and therefore the bit error rate performance of the receiving device deteriorates. Therefore, it is necessary to maintain the amount of phase shift that the carrier wave component undergoes on the path from the input terminal of the receiving device to the demodulator via the carrier wave regenerator to a constant value. For this reason, conventional receiving devices use electrical components such as transmission lines and carrier wave regenerators that make up the above-mentioned paths that have small temperature changes and changes over time, making them expensive and requiring use over a wide ambient temperature range. In order to achieve this, it is also necessary to perform temperature compensation for the amount of phase shift, but this compensation is extremely difficult, resulting in a disadvantage that the temperature stability of the bit error rate performance is poor.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, or in other words, the purpose of the present invention is to eliminate the above-mentioned drawbacks and to provide a receiving device that is economical and has excellent temperature stability of bit error rate performance.

[Means for solving problems]

The receiving device of the present invention includes carrier wave reproducing means for branching and inputting an input signal modulated with a digital signal including an error correction code, regenerating its carrier wave component, and outputting the carrier wave component as a carrier wave signal, and the carrier wave signal and the control signal. a phase adjusting means that receives the input signal and outputs, as a reference phase signal, a signal having a phase different from the phase of the carrier signal by a phase amount controlled by the control signal; a demodulating means for demodulating the baseband signal and outputting it as a baseband signal; a discriminating means for inputting the baseband signal, identifying and reproducing it, and outputting it as a reproduced signal; and inputting the reproduced signal, detecting and correcting code errors thereof, and outputting the result an error correction means for outputting an error pulse as an error pulse signal each time the code error is detected; and an error correction means for inputting the error pulse signal and counting the number of the error pulses input within a certain period of time, the value being a count value. a counting means for periodically outputting a signal as an error rate signal; control means for outputting, as the control signal, a signal whose value changes in the direction of decreasing the value of the error rate signal by decreasing the control signal if the directions match and increasing the control signal if the directions do not match; Prepared and configured.

〔Example〕

The present invention will be described in detail below with reference to the drawings shown in examples.

FIG. 1 is a block diagram showing an embodiment of the receiving apparatus of the present invention.

The receiving device of this embodiment is configured as follows. In other words, an input signal modulated with a digital signal containing an error correction code (external input terminal 98
(input via) 101 and input it by branching,
A carrier wave regenerator 1 that regenerates the carrier wave component and outputs it as a carrier wave signal 102, and a carrier wave signal 102 and a control signal 109 are input, and the control signal 109 has a phase different from the phase of the carrier wave signal 102 by a controlled phase amount. A phase adjuster 2 that outputs a signal as a reference phase signal 103, a demodulator 3 that receives the input signal 101 and the reference phase signal 103, demodulates the input signal 101, and outputs it as a baseband signal 104, and a baseband signal 104. a discriminator 4 that inputs the reproduced signal 105, detects and corrects code errors in the reproduced signal 105, and outputs it as an output signal 106 to the outside via an output terminal 99. and an error corrector 5 which outputs an error pulse as an error pulse signal 107 every time a code error is detected, and an error pulse signal 1
07 and the control clock signal 110, and the number of pulses of the error pulse signal 107 that occurs during one cycle of the control clock signal 110 (this time is T) is counted, and the value is the error rate signal. 1
Counter 6 outputs as 08 and error rate signal 1
08 and a control clock signal 110 and outputs a control signal 109 that changes every time T, and a clock generator 8 that generates and outputs a control clock signal 110.

The phase adjuster 2 includes a DA converter that converts the control signal 109 and outputs a DC voltage, and a variable phase shifter in which a variable capacitance diode is loaded on the transmission line. Since this DC voltage is applied to the variable capacitance diode to control the phase shift amount of the variable phase shifter in an analog manner, the phase shift amount of the phase adjuster 2 is controlled by the control signal 109.

Note that the control signal 109 is an error rate signal 1 outputted via the demodulator 3, discriminator 4, error corrector 5, and counter 6 when inputted to the phase adjuster 2.
The value changes in the direction of decreasing the value of 08.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

A reference phase signal 103 that has been regenerated and phase-shifted from an input signal 101 by a carrier wave regenerator 1 and a phase adjuster 2 is input to a demodulator 3 . Demodulator 3 receives reference phase signal 1
The input signal 101 is demodulated using the phase of 03 as a reference, and its output, a baseband signal 104, is subjected to identification reproduction and error correction in the discriminator 4 and error corrector 5, and is output as an output signal 106. Also,
Each time a code error is detected, the error corrector 5 outputs an error pulse as an error pulse signal 107 using the method described in the "Prior Art" section. The number of pulses of the error pulse signal 107 generated during the time T is counted by the counter 6, and a signal having the value of the counted value is outputted to the control unit 7 every time T as an error rate signal 108. The quotient obtained by dividing the value of the error rate signal 108 by T is approximately equal to the average code error rate before error correction during the counting time T (the true average code error is increased by the code errors that could not be detected by the error corrector 5). (There is an error in the rate, but this error can be ignored).

When the value of the control signal 109 changes, the phase adjuster 2
Since the amount of phase shift exhibited by the signal changes, the reference phase of the demodulator 3 changes, and as a result, the average code error rate of the reproduced signal 105, that is, the average code error rate before error correction described above changes, so that the error rate signal 108 changes. The value also changes. The control unit 7 detects the direction of increase/decrease of the control signal 109 and the direction of increase/decrease of the value of the error rate signal 108 as a result, and based on these detection results, controls the control signal in the direction to decrease the value of the error rate signal 108. 1
Increase or decrease the value of 09. That is, the control signal 109
Since the value of always changes in the direction of decreasing the average code error rate before error correction, the amount of phase shift exhibited by the phase adjuster 2, which changes with the change in the value of the control signal 109, converges to the optimum value.

When the reference phase of the demodulator 3 deviates from the optimum value due to changes in ambient temperature and the average code error rate before error correction increases, the value of the control signal 109 changes in the direction of decreasing it, and the phase adjuster 2 The amount of phase shift exhibited by the phase shift changes in a direction approaching the optimum value and finally converges to the optimum value.

In this way, it is possible to prevent an increase in the average code error rate before error correction due to fluctuations in the reference phase of the demodulator 3 due to changes in ambient temperature, etc., and therefore the average code error rate of the output signal 106 after error correction can be It is possible to prevent the error rate from increasing due to changes in ambient temperature, etc., and to improve the stability of the bit error rate performance of the receiving device against changes in ambient temperature.

FIG. 2 is a block diagram showing the details of the configuration of the control section 7. As shown in FIG.

The control unit 7 includes a latch circuit 71 which inputs the error rate signal 108 and the control clock signal 110, stores and holds the value of the error rate signal 108 for a time T, and outputs the value as a signal 701;
01 and the control clock signal 110 are input, and the signal 7
A latch circuit 72 stores and holds the value of 01 for a time T and outputs a signal 702 having that value, inputs signals 701 and 702, compares the values of these two signals, and determines that the value of signal 701 is the signal 702. 70
When the value is greater than or equal to 2, the logic value is “1”, and the signal 70
Logic value “0” when the value of 1 is less than the value of signal 702
A comparator 73 outputting a signal 703 and a signal 70
3 and a signal 704 which is the output of the latch circuit 75, and outputs a signal 705 having the value of the exclusive OR of the values of these two signals;
A latch circuit 75 inputs the signal 705 and the control clock signal 110, stores and holds the value of the signal 705 for a time T, and outputs the signal 704 having the value;
10 is input, and when the value of the signal 705 is a logical value "1", the numerical value "1" is added to the counted value, and when the value of the signal 705 is a logical value "0", the numerical value "1" is added from the counted value.
, and an up-down counter 76 that outputs a control signal 109 whose value is a count value that changes every time T.

Next, the operation of the control section 7 will be explained.

The error rate signal 108 is input to the latch circuit 71 of the control section 7 every time T. The value of the error rate signal 108 input to the latch circuit 71 at time t is held in the latch circuit 71 from time t to (t+T), and during this period (t to (t+T)
This is the value of the signal 701 output during the interval). On the other hand, the value of the signal 702 between time t and (t+T) is the value held in the latch circuit 72, and this is the value held in the latch circuit 71 from time (t-T) to t, that is, the value held in the latch circuit 72 during this period. Equal to the value of the signal 701 (between (t-T) and t),
This also means that at time (t-T) the latch circuit 7
It is equal to the value of the error rate signal 108 input to 1.
The increase/decrease in the value of the error rate signal 108 from time (t-T) to t, that is, the increase/decrease in the value of the signal 701 from immediately before to immediately after time t, is expressed as from time t to (t+
The comparator 73 detects the magnitude of the values of the signal 701 and the signal 702 during the period T), and the result is output as the value of the signal 703 between the time t and (t+T). On the other hand, the value of signal 704 between time t and (t+T) is the value held in latch circuit 75, which is the value of signal 705 between time t and time (t-T). Therefore, the value of signal 705, which is the output of EX-OR circuit 74, between time t and (t+T) is the same as the value of signal 703 between time t and (t+T), and time (t+T).
-T) to the value of the signal 705 between t and the exclusive OR value. Depending on whether the value of the signal 705 between time t and (t+T) is the logical value "1" or the logical value "0", the up-down counter 76 changes the value of the control signal 109 which is its output to the time. The value increases or decreases by "1" from immediately before to immediately after t. Also, whether the value of the signal 704 from time t to (t+T) is a logical value "1" or logical value "0" is determined by the value of the control signal 109 from immediately before to immediately after time (t-T). This corresponds to increases and decreases in FIG. 3 shows the increase/decrease in the value of the control signal 109 from immediately before to immediately after time (t-T), the value of the signal 704 between time t and (t+T) corresponding to this increase/decrease, and the above-mentioned increase/decrease. An increase or decrease in the value of the resulting error rate signal 108 from time (t-T) to t, that is, an increase or decrease in the value of the signal 701 from immediately before to immediately after time t, and an increase or decrease in the value of the signal 701 from time t to (t+T) determined from this increase or decrease. The value of signal 703,
This figure illustrates the correlation between this value and the value of the signal 705 from time t to (t+T) determined from the value of 704 above, and the increase/decrease in the value of the control signal 109 from immediately before to immediately after time t determined from this value. be. As is clear from this figure, the control unit 7 detects an increase or decrease in the value of the error rate signal 108 as a result of an increase or decrease in the value of the control signal 109, that is, an increase or decrease in the value of the signal 701, and decreases the value of the error rate signal 108. The value of the control signal 109 is changed in the direction of the change and output.

It should be noted that a receiving device in which the phase adjuster 2 in the embodiment shown in FIG. be.

〔Effect of the invention〕

As explained in detail above, the receiving device of the present invention generates a control signal based on the error pulse signal output from the error corrector, and uses this control signal to always adjust the phase so that the bit error rate is minimized. By using the receiving device of the present invention, there is no need for temperature compensation of the reference phase, and the code This has the effect of providing an economical receiving device with excellent temperature stability and stability over time of error rate performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the receiving device of the present invention, FIG. 2 is a block diagram showing the configuration of the control section of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing the control section shown in FIG. 2. FIG. 2... Phase adjuster, 5... Error corrector, 7...
control section.

Claims (1)

[Claims] 1 A carrier wave reproducing means for branching and inputting an input signal modulated by a digital signal including an error correction code, regenerating its carrier wave component, and outputting it as a carrier wave signal; a phase adjusting means for outputting a signal having a phase different from the phase of the carrier signal by a controlled phase amount as a reference phase signal; and a baseband signal for demodulating the input signal by inputting the input signal and the reference phase signal. demodulating means for inputting the baseband signal, identifying and reproducing it, and outputting it as a reproduced signal; an error correction means that outputs an error pulse as an error pulse signal every time an error is detected; and an error correction means that inputs the error pulse signal and counts the number of error pulses that are input within a certain period of time, and calculates a signal whose value is the count value as an error rate. a counting means for periodically outputting as a signal, inputting the error rate signal and detecting the direction of increase/decrease in the error rate signal as the control signal increases/decrease, and if these two directions of increase/decrease match, the and control means for outputting, as the control signal, a signal whose value changes in the direction of decreasing the value of the error rate signal by decreasing the control signal and increasing the control signal if they do not match. Receiving device.