JPH0775355B2 - DC drift compensation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit configuration method for compensating for DC drift on the demodulation side in a digital communication system.

[Conventional technology]

FIG. 1 is a diagram showing an input / output relationship when an 8-value amplitude signal is identified by an A / D converter. Regarding the DC drift and its compensation using the figure, taking an 8 (= 2 ³ ) value signal as an example,
explain.

In FIG. 1, the most significant bit has the center level of the eight-valued signal as the discrimination level (hereinafter referred to as "path 1 discrimination").
In addition, the upper 2nd bit uses a half of the amplitude of path 2 as the identification level (hereinafter referred to as identification of path 2). Furthermore, the upper 3 bits have a further half amplitude as an identification level (hereinafter referred to as the identification of path 3), and the upper 4 bits have an 8-level signal point as an identification level, and the information is intersymbol interference or The direction of the identification error is shown (hereinafter referred to as identification of pass 4).

In the case of an octal signal in the system scrambled on the transmitting side, the existence probability of “0” and “1” is 50% in the identification of the path 1 and the path 4, but, for example, in FIG. If the signal point is slightly above, the path 4 has all information "1".
Therefore, control is performed to lower the DC level.

Further, in the pseudo stable state as shown in FIG.
Controls the lowering of the DC level because the existence probability of "1" increases at a ratio of 5 to 3.

When the signal arrangement is erroneous (shifted) due to the DC drift or the like, the DC offset is conventionally controlled by the circuit having the configuration shown in FIG.

In FIG. 3, an 8-value signal is input to the input terminal 1 to change the amount of DC offset.
Then, the signal is input to the A / D converter 3 to identify the signal. The A / D converter 3 uses the timing signal from the terminal 4 for identification.

Next, a control signal is obtained by passing the resistors 5 and 6 for adding the output signals of the path 1 and the path 4 and a low pass filter 7 for integrating the added output to obtain the control signal. The signal is fed back to the DC amplifier 2 and the amount of DC offset is controlled to prevent the noise margin from being reduced by the DC offset.

[Problems to be solved by the invention]

As described above, the conventional DC drift compensation circuit requires the DC amplifier capable of changing the offset amount, and since it is the control method using the analog signal, the control loop gain and the loop time constant are delicate. There was a problem that adjustment was necessary.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a DC drift compensation circuit capable of effectively adjusting the DC offset and increasing the noise margin of the multi-level signal discriminator without finely adjusting the circuit such as the offset adjustment of the DC amplifier. I am trying.

[Means for solving problems]

The present invention achieves the above object by the means described in the claims, and in a circuit for compensating for DC drift in a digital communication system, a conventional LCR is used.
In the present invention, a reversible counter is used to correspond to an analog integrator circuit using a DC amplifier, and in the past, a DC amplifier capable of changing a DC offset amount was used. This is replaced with a fixed DC amplifier and full adder. It is also different from the prior art in that a fixed value is added to the full adder in order to detect normality / synchronism, perform normal control during synchronization, and prevent the main signal system from being adversely affected during asynchronousness.

〔Example〕

FIG. 4 is a block diagram of the first embodiment of the present invention and corresponds to the claim (1).

To explain using an 8-value (= 2 ³ ) signal as an example with reference to FIG. 1, the 8-value signal is input from the input terminal 1 and extracted from the received signal by the A / D converter 3 having an 8-bit output, for example. The signal is identified using the timing signal (input from the terminal 4). Of the 8 bits, the upper 3 bits are demodulated data (path 1 to path 3 in FIG. 1). Then, the output of the A / D converter 3 is passed through the full adder 9 and input to the 8-stage reversible counter 10 for integrating the upper 4th bit of the output.

Here, the upper 4th bit indicates the direction of intersymbol interference. When it is "1", the direction of DC drift is positive, and when it is "0", the direction of DC drift is negative. Suppose

In the synchronous state, "1" is input to the monitor terminal 11, so a clock signal is input to a counter as shown in FIG. 7 described later, and when the value of the upper 4th bit is "1", the reversible counter is The reversible counter 10 operates so as to count down 10 while counting up when "0". Of the output of the reversible counter, for example, the upper 6 bits are the full adder 9
When the initial value of the counter is “00000000” and the value of the upper 4th bit “1” is input to the reversible counter, the output is counted down to “111111” (in this case Ignore the carry or borrow that occurred). If this value is added to the full adder, 8-bit A /
The D converter output and the 6-bit counter output are added so that the LSBs match, so, for example, the A / D converter output is "1.
When it is 0011001 ", it becomes“ 10011001 ”+“ × 111111 ”((×
Is optional), the least significant bit is reduced by 1 and "xx0110"
It becomes 00 "and the least significant bit is shifted to the negative side, and the offset can be returned to normal.

In the above example, the counter is the upper 6 bits of the 8-bit input.
Bits are used and the output of the counter is 4
Since it changes bit by bit, the subtraction is performed at a rate of 1/4 of the identification clock.

When the upper 4th bit is "0", it is the opposite of the above example,
The offset can be returned to normal by shifting to the positive side by the amount shifted to the negative side.

On the other hand, in the case of asynchronous, a “0” signal is input to the asynchronous detection monitor 11, the clock input of the counter is stopped, and the operation of the counter is effectively stopped, so the data immediately before the asynchronous is added to the full adder as fixed data. .

Therefore, the normal control is performed at the time of synchronization, and the data immediately before the asynchronous is added to the full adder as fixed data so as not to adversely affect the main signal at the time of asynchronous. The offset compensation accuracy improves as the number of output bits of the A / D converter, the number of stages of the reversible counter, and the number of bits of the full adder are increased.

FIG. 5 is a block diagram showing a second embodiment of the present invention and corresponds to the claim (2).

In the case of the pseudo stable state like the state (b) in FIG. 2 described above, it becomes difficult to control the offset correctly with the information of the upper 4 bits. Therefore, in such a case, it is possible to control by using the most significant bit of the output of the A / D converter. Further, at this time, if the state is returned to the state (a) in FIG. 2, it becomes possible to control by the information of the upper 4th bit.

In this embodiment, a reversible counter 13 for integrating the most significant bit, a full adder 12 for adding its output and the output of the A / D converter, and a reversible counter 10 for integrating the upper 4th bit at the time of synchronization. The offset is compensated by the full adder 9 that adds the output of the output and the output of the full adder 12.

Here, each of the two full adders requires a high-speed full adder that operates at a speed equivalent to the code speed. Further, at the time of asynchronous operation, the clocks of the counters 10 and 13 are stopped by "0" input to the asynchronous detection monitor 11 so that the data immediately before the asynchronous operation is generated as fixed data so that the main signal is not adversely affected. .

FIG. 6 is a block diagram of a third embodiment of the present invention,
The high speed full adder in the embodiment shown in FIG.
The circuit configuration for saving the individual pieces is shown. That is, the most significant bit and the upper 4th bit are separately integrated by the independent reversible counters 10 and 13, respectively, and a full adder 14 for adding the output and a full addition for adding the output and the A / D converter output are added. The offset compensating circuit is realized by the device 9. Since the number of output bits of the counter is smaller than the number of stages, and the difference is P, the data rate of the counter output is 1 / 2P of the input clock. Therefore, the full adder 14 in the configuration of FIG.
Needs to be operated at a low speed, and only one high speed full adder has to be operated at a speed equivalent to the code speed.

FIG. 7 is a block diagram showing an example of an 8-stage reversible counter configuration. In this case, the case where the upper 6 bits of the 8 stages are taken as the output bits is shown.

In FIG. 7, the clock signal is input to the terminal 15 and the synchronous / asynchronous detection signal is input to the motor terminal 11, and the AND circuit 25 controls the on / off of the counter. Further, the up / down control information is input to the input terminal 16 and the T flip-flop 17
The output is obtained from the Q terminal through 24. In the figure, in addition to the above, 26 is an AND circuit, 27 is an OR circuit, and 28 is an inverting circuit.

〔The invention's effect〕

As described above, the DC drift compensation circuit according to the present invention having the synchronous / asynchronous detection function uses the digital signal of the A / D converter for the DC offset of the input analog signal of the A / D converter. Can be realized with
It has an advantage that it can provide a circuit configuration that is suitable for LSI without adjustment.

[Brief description of drawings]

FIG. 1 is a diagram showing an input / output relationship when an 8-level amplitude signal is discriminated by an A / D converter, and FIG. 2 is a diagram showing an example of a state when the DC level of the amplitude signal is changed, FIG. Is a block diagram showing an example of a conventional circuit for controlling a DC offset, FIG. 4 is a block diagram showing a first embodiment of the present invention, and FIG. 5 is a diagram showing a second embodiment of the present invention. FIG. 6 is a block diagram showing a third embodiment of the present invention, and FIG. 7 is a block diagram showing an example of the configuration of an 8-stage reversible counter. 1 ... Input terminal, 2 ... DC amplifier, 3 ... A / D converter, 4 ... Timing signal terminal, 5, 6 ... Resistor, 7
...... Low-pass filter, 8 …… Fixed DC amplifier, 9, 12
…… Full adder, 10, 13 …… Reversible counter, 11 …… Monitor terminal, 14 …… Low speed full adder, 15 …… Clock signal input terminal, 16 …… Up-down control signal input terminal, 17 to 24… …
T flip-flop, 25, 26 ... AND circuit, 27 ... OR circuit, 28 ... Inversion circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yasuhisa Nakamura, Yasuhisa Nakamura, 2356 Take, Yokosuka City, Kanagawa, Japan, Yokosuka Electro-Communications Research Laboratories, Nippon Telegraph and Telephone Corporation (56) Reference JP-A-60-25356 (JP, A) Kai 60-80348 (JP, A)

Claims (2)

[Claims] 1. A scrambled 2 ^N value (N
Is a whole number, and J (J is J ≧ N +)
1) An A / D converter that outputs a bit signal, a full adder that receives the output of the A / D converter as an input, and an upper N of the full adder
A reversible counter having M stages (M is an integer of 2 or more) for integrating the + 1st bit output and having a signal input terminal for monitoring the synchronization / asynchronization of the system; A DC drift compensation circuit characterized in that (K is K ≧ M) bits are input to a full adder, and when asynchronous, data immediately before becoming asynchronous is input as fixed data to the full adder. 2. An A / D converter that receives a scrambled 2 ^N- valued multi-valued amplitude signal on the transmission side and outputs a J (J is J ≧ N + 1) bit signal, and the A / D converter. A first full adder having an output of the converter as an input; a second full adder having an output of the first full adder as an input; the second full adder;
A reversible counter having M signal stages (M is an integer of 2 or more) for integrating the most significant bit output of the full adder and having a signal input terminal for monitoring the synchronization / asynchronization of the system; A second reversible counter having M signal stages for integrating the output of the upper N + 1th bit of the adder and having a signal input terminal for monitoring the synchronization / asynchronization of the system; The high-order K (K is K ≧ M) bits are input to the first full adder, and the high-order K bits of the output of the second reversible counter are input to the second full adder. 1
The DC drift compensation circuit, wherein the data immediately before being asynchronous is input as fixed data to the full adder and the second full adder.