JPH0422057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field The present invention relates to an optical receiving circuit in an optical communication system.

This is done by converting an optical communication signal into an optical signal, transmitting it through an optical fiber, and then converting the optical signal back into an electrical signal. The receiving circuit includes a photoelectric conversion element such as a photodiode or an avalanche photodiode, and a circuit that amplifies the current flowing through the element and restores the signal.

The signal sent may be a digital signal or an analog signal. here,
Deals with optical receiving circuits for digital signals.

Since it is a digital signal, a signal identical to the original digital signal can be restored by amplifying the minute photocurrent in the receiving circuit and shaping the waveform through a binarization circuit including a comparator.

(b) Conventional technology and its problems FIG. 4 shows a conventional optical receiving circuit.

The cathode of the photodiode 20 is connected to the power supply Vcc, and the anode is connected to the inverting input of the operational amplifier 21. The inverting input of operational amplifier 21 is pulled above ground potential by battery 22.
The resistor 23 feeds back the output of the operational amplifier 21 to the inverting input.

The output voltage Vd is the sum of the DC voltage V ₀ of the battery 22 and the product (−Rf Ip) of the photocurrent Ip and the resistance Rf. The photodiode current is controlled by the resistor Rf and the amplifier.
Current-voltage conversion is performed.

The reason for adding the DC voltage V ₀ is that the output voltage Vd can fluctuate up and down between 0 V and Vcc with V ₀ as the center without being saturated.

The AC component of the output voltage Vd is given by the product of the photodiode current Ip and the resistance Rf.

Rf determines the amplification factor. If Rf is too small, and the amount of light incident on the photodiode is small, the alternating current component of the output voltage Vd will become too small and fall below the threshold level of the next-stage comparator, making it difficult for the comparator to binarize correctly. I can't.

Increasing Rf can alleviate this difficulty with respect to weak optical signals. However, conversely, when the optical power incident on the photodiode is large, the transistor in the amplification section becomes saturated.
This reduces the response speed and distorts the waveform.

Therefore, in such a circuit configuration, for example, a single
When using a 5V power supply, it is extremely difficult to obtain a large dynamic range (for example, 30dB).

Furthermore, when trying to make the entire circuit a monolithic IC, it is difficult to create high resistance. 100KΩ
It is difficult to create resistance. If the photocurrent of the photodiode is 0.1 μA to 100 μA, using this resistor will result in an AC output of 10 mV to 10 V. When using a 5V power supply, it will saturate at high optical power.

When making a monolithic IC, the resistance should be 20KΩ~
A value of 30KΩ or less is selected. This is because it is easy to make products with such low values. However, in this case, weak signals cannot be sufficiently amplified.

If a large dynamic range is not required, saturation can be prevented by appropriately selecting the value of the negative feedback resistor Rf. However, even in this case, since the output voltage is proportional to the optical power incident on the light receiving element, it becomes difficult to set the reference voltage of the comparator.

This will be explained with reference to FIG. Suppose that three types of signals with different powers come in. These are designated as S ₁ , S ₂ , and S ₃ in descending order of size. Suppose that the output after amplification appears as shown in FIG. 5a in proportion to the intensity of the optical signal. The pulse width is the same in both cases, but S ₁ ,
The pulse height increases in the order of S ₂ and S ₃ .

Since they are originally digital signals and have the same pulse width, they must be waveform-shaped to have equal pulse widths. However, if the reference voltage Vc of the comparator is fixed to a constant value, this will not happen.

For example, assume that the reference potential Vc is set to 1/2 of the peak value of the output of the signal _S3 corresponding to the minimum reception level. The waveform after passing through the comparator is S ₃ ,
S ₂ and S ₁ are shown in b, c, and d.

In _S1 , where the optical power is large, it exceeds Vc at an early rise time and returns to below Vc at a late fall time. This is the longest pulse width W ₁ as shown in d.
have.

Regarding _S3 , where the optical power is small, it is slow to exceed Vc and quick to return below Vc. As shown in b, it has the shortest pulse width _W3 .

In this way, if the power of the light is strong, the pulse width will be long, and if the power of the light is weak, the pulse width will be short.

However, since the original pulse widths are the same, they should not change to different pulse widths like this.

This is because the comparator reference voltage Vc of the comparison circuit is fixed regardless of the magnitude of the pulse signal.

It should be sufficient to change the reference voltage Vc according to the amplified output. For this purpose, an ATC (Auto Threshold Level Control) method has already been proposed that detects the maximum and minimum values of the amplifier output and sets the reference potential Vc of the comparator so that it is always 1/2 of the amplifier output. It's being served. However, if we try to implement this circuit using a monolithic IC, the circuit becomes complicated.

() There were problems such as the need for external capacitors to store the maximum and minimum values.

The capacitor for storing the maximum and minimum values needs to have a capacitance of, for example, 0.1 μF to 1 μF. However, at present, the capacitors that can be fabricated on a wafer using monolithic IC technology are no more than 10 pF to 20 pF.

(c) Purpose of the present invention The purpose of the present invention is to provide a monolithic optical receiver circuit with a wide dynamic range and low pulse distortion.

(D) Embodiment FIG. 1 is an optical receiving circuit diagram according to an embodiment of the present invention.

This circuit consists of a current-voltage conversion circuit A, a differentiation circuit B, a reference voltage generation circuit C, a comparison circuit D, and an output stage E.
It's getting more and more familiar.

R1 to R13 are resistors. Tr1 to Tr24 are transistors, and C1 and C2 are capacitors.
I1 to I13 indicate constant current circuits.

All of these are circuit elements of a monolithic IC. Manufactured using a wafer process on a semiconductor single crystal board. It is not made by assembling individual parts on a printed circuit board.

Capacitors C1 and C2 are small capacitance capacitors, for example, C1 is about 5PF and C2 is about 10pF, but these can be manufactured by a wafer process.

A constant current circuit is a combination of several transistors and resistors, and is already widely used in monolithic ICs. Since it can be constructed using a well-known circuit, illustration of the internal circuit is omitted.

Although the power supply voltage is 5V, this circuit will always function well no matter what the power supply voltage is, as long as the constants are changed appropriately.

The current-voltage conversion circuit A will be explained in order.

A Current-Voltage Conversion Circuit A constant current circuit I1, the collector and emitter of the transistor Tr1, and forward diodes D1 and D2 are connected between the power supply Vcc and the ground.

A transistor Tr2 and a constant current circuit I2 are connected in series between the power supply and the ground.

The base of transistor Tr2 is the transistor
It is connected to the collector of Tr1 and constant current circuit I1. A photodiode PD is connected in the opposite direction between the base of the transistor Tr1 and the ground.

A voltage equal to the base-emitter voltage drop of the transistor Tr1 and the voltage drops D1 and D2 of the pn junction of the diode is applied to the photodiode PD. For example, it is about 1.8V.

The base of transistor Tr1 and the transistor
A capacitor C1 and a resistor R1 are connected between the connection point of Tr2 and constant current circuit I2.

The capacitor C1 is for preventing oscillation and has a value of about 5 pF, for example.

Resistor R1 is a resistor for current-voltage conversion. The larger the value, the higher the amplification factor, but since it is an element of a monolithic circuit, it is limited to 20KΩ to 30KΩ.

When the photocurrent Ip is 0, transistors Tr1 and Tr2
Constant currents I1 and I2 are flowing in both. The value of the base current of the transistor Tr1 is fixed to a constant value by I1. Only this base current flows through the resistor R1. The emitter potential of transistor Tr2 is the base emitter of Tr1, D
It is given by the sum of the forward voltage drop of 1, D2 and R1×(base current).

Suppose that an optical signal enters a photodiode PD.
A photocurrent Ip flows. Then, the emitter voltage of the transistor Tr2 increases by the product of Ip and R1. This is the voltage signal. transistor
Since the potential at the connection point between Tr2 and constant current circuit I2 is not determined by their own states, it can be determined by Ip R1.

B. Differentiating circuit In the present invention, after amplifying the photocurrent, it is passed through a differentiating circuit instead of immediately entering a comparator circuit for binarization. A differentiation circuit converts the rising portion of the signal into an upward pulse, and the falling portion of the signal into a downward pulse.

However, this is not entirely new;
An optical receiving circuit in which the signal is passed through a differentiation circuit after amplification has already been proposed.

The two transistors Tr3 and Tr4 are balanced and used as a differential amplifier. The emitters of the two transistors are common and connected to ground via a constant current circuit I3. The base of the transistor Tr3 is connected to the output of the current-voltage conversion circuit A mentioned earlier via the resistor R2. transistor
The base of Tr4 is also connected to the output of current-voltage conversion circuit A via resistor R3.

However, the base of transistor Tr4 is further connected to ground via capacitor C2. Resistor R3 and capacitor C2 constitute a delay circuit.

The collector of transistor Tr3 is connected to power supply Vcc. The collector of transistor Tr4 is
It is connected to Vcc via resistor R4.

The solid line in FIG. 2a shows the output signal of the current-voltage conversion circuit A. This is equal to the base voltage of transistor Tr3.

The change in the base voltage of transistor Tr4 is R
3. Since there is a delay due to C2, it changes as shown by the broken line a.

Then, the solid line s and the broken line t differ at the rise and fall of the pulse. At this time, the two transistors Tr3 and Tr4 become unbalanced. Although approximately the same current flows through both transistors in a balanced state, the current flowing through the resistor R4 changes in the shaded area (between st) in FIG.

Therefore, the collector voltage of Tr4 changes. This is a differential waveform as shown in FIGS. 2b and 2c.
The speed of temporal decay of the differential waveform depends on R3C2. In one example, R3 is 30KΩ and C2 is 10pF.

If the power of the input optical signal is small, the differential waveform will be like b, and if the power is large, the differential waveform c may be saturated at the top and bottom. However, R
Since the product of 3 and C2 is narrower than the pulse width, the differential waveform always returns to its original level before one pulse ends. Therefore, there is no problem of delay in operation time due to saturation.

In this way, a differential waveform of the amplified signal appears at the collector u of the transistor Tr4.

C Reference voltage generation circuit This is the voltage that becomes the reference for dividing the differential signal u into “H” and “L” in the next stage comparator.
This is a circuit for generating Vc.

If the average value of the differential signal is determined and used as a reference voltage, the pulse width can be a constant value regardless of the pulse height. In order to find the average value of the differential signal, it is sufficient to create a series body of a resistor and a capacitor, and use this to average the differential signal. The values thus obtained are exact average values.

To do this, the time constant of the averaging (smoothing) circuit of the resistor and capacitor must be significantly longer than the pulse repetition time. This makes the capacitor too large.

I would like to make the entire circuit monolithic, but if I had to add a large capacitor, a monolithic circuit element would not be enough and I would have to use an external capacitor.

Adding external capacitors increases circuit volume and can reduce reliability.

Therefore, instead of directly averaging the differential signals, the average value is determined in advance.

Power supply for transistor Tr6 and constant current circuit I5
Connect in series between Vcc and ground.

The resistor R7 and the constant current circuit I6 are connected in series,
Connect between Vcc and ground.

Connect the resistor R7, the constant current circuit I6, and the base of Tr6. The potential of this connection point w is made equal to the average value <u> of the output u of the differentiating circuit.

To do this, it is sufficient that the average voltage applied to resistor R4 and the voltage applied to R7 in the differentiating circuit are equal, so R4I3/2=R7I6. The right side is the potential at point w (from Vcc)
The left side is the potential at equilibrium at point u. at equilibrium
A current of I3/2 flows through Tr3 and Tr4.

For example, if I3=I6, R7 is 1/1/1 of R4.
Set it to a value of 2.

The potential at point w is determined in this way. Transistors Tr6 and Tr7 are in the form of emitter followers, and the base-emitter drop is 2 times higher than this potential.
The subtracted reference voltage Vc is applied to the comparator of the comparison circuit D.

Since the voltage relationship must not deviate due to temperature changes, Tr5 and Tr6, Tr8 and Tr7, and resistors R5 and R6 should have the same characteristics.

The voltage at the point w given in advance and the average of the differential signal u <
There is a possibility that there may be a discrepancy between ``u'' and ``u''. However, since the average of the differential is always 0, if there is a drift, it is the DC component that drifts.

The DC component is a constant value and does not drift as long as Tr3 and Tr4 are balanced.

Therefore, the voltage at point w can always give the average value <u> of the differential signal u.

D Comparison circuit This is a circuit that compares the differential signal obtained by the differential circuit with a reference voltage and converts it into two values (H and L).

If the differential waveforms shown in FIGS. 2b and 2c are directly compared with the reference voltage using a comparator, the pulses will simply be shaped into a rectangular shape. Figure 2 a, s
The pulse width is not restored to be equal to the original pulse, as shown in .

“H” between upward pulse and downward pulse
, “L” between the downward pulse and the upward pulse
must be converted to

Therefore, we decided to give hysteresis to the differential signal. If there is hysteresis, after the upward pulse enters the comparator and the output becomes “H”,
Even if the input returns to 0, the output remains at "H".
The output changes to "L" only when a downward pulse is input to the comparator.

To provide hysteresis, do the following: Let the differentiated signal be U. This is the potential of the emitter of Tr8, which is obtained by subtracting a constant voltage from the output u of the differentiating circuit.

Let the reference voltage be Vc. This is obtained by subtracting a constant voltage from the potential at point w of the reference voltage generating circuit C.

If the output of the comparator circuit is D, the signal U is not simply compared with the reference Vc and D is set to L or H.

Assuming hysteresis as ΔV () When D=H, compare Vc and (U+ΔV).

If the latter is large, D=H is maintained, and if the latter is small, D is changed to L.

() When D=L, compare Vc and (U-ΔV).

If the latter is small, D=L remains, and if the latter becomes large, D is changed to H.

The reference voltage Vc obtained by the reference voltage generation circuit C is
It is applied to the base of transistor Tr11. The signal voltage from the differentiating circuit is connected to resistor R6 and transistor
It is applied to the base of transistor Tr12 through Tr8 and resistor R8.

The comparator is a transistor Tr
11 and Tr12, transistors Tr13 and Tr14 whose emitters are connected to each other, and transistors Tr15 and Tr16 whose collectors are connected to each other.

The transistors Tr9 and Tr10 are for supplying a constant current to these symmetrical comparators.

The emitters of the pnp type transistors Tr9 and Tr10 are connected to Vcc, and the bases are connected to each other.

The collector of the transistor Tr9 is connected to ground through a constant current circuit I9. The bases of transistors Tr13 and Tr14 in the symmetrical comparator are also connected to the collector of Tr9.

The base and collector of the transistor Tr10 are connected. The collector is further connected to the collectors of two transistors Tr11 and Tr12 of the comparator.

The emitters of the transistors Tr15 and TR16 are grounded, and the base and collector of the transistor Tr16 are connected.

Transistors Tr9 to Tr16 constitute a comparator, and the output becomes the collector of transistor Tr15.

The base voltages of transistors Tr11 and Tr12 are compared. The base voltage of Tr11 is Vc, Tr12
The base voltage of is (U±ΔV).

If the base voltage of Tr11 is lower than that of Tr12, the base current of Tr12 and Tr14 becomes Tr1.
1. It becomes larger than the base current of Tr13. Tr1
Since the base current of Tr 3 decreases, the collector current of Tr 13 decreases, and the collector voltage decreases. In other words, the voltage at the collector X of the transistor Tr15 decreases.

If the base voltage of Tr11 is higher than that of Tr12, the voltage of X increases.

A series body of a constant current circuit I10 and a transistor Tr17 is connected between the power supply Vcc and ground. The base of the transistor Tr17 is connected to the X point.

The collector of the transistor Tr17 is a resistor R9,
Transistors Tr18 and Tr21 via R10
is connected to the base of

When the voltage at point X is low, transistor Tr17 is
It is off because no base current flows.

When the voltage at the X point is high, the transistor Tr17 is conductive. Accordingly, transistors Tr18,
Tr21 also operates on and off accordingly.

The hysteresis circuit included in the comparison circuit D includes constant current circuits I11 and I12, and transistors.
It consists of Tr18, Tr19, Tr20 and resistor R8.

Transistor Tr18 and emitter are grounded,
The collector is connected to the power supply Vcc via a constant current circuit I11.

The emitter of transistor Tr19 is grounded,
The base and collector are connected to each other. The collector is also connected to a constant current circuit I11.

The emitter of transistor Tr20 is grounded.
The collector is connected to Vcc via a constant current circuit I12. The collector is also connected to the base of a transistor Tr12 that serves as a comparator.

From the constant current circuit, the base of Tr12, resistor R8
Let e be the current flowing to the collector of Tr20, and f be the current flowing to the collector and emitter of Tr20. e, f, I12 are e+f=I12 (1).

The current flowing from the constant current circuit I11 to Te18 is assumed to be g, and the current flowing to Tr19 is assumed to be h. g, h,
During I11, g+h=I11 (2) holds true.

The emitters of Tr19 and Tr20 are grounded, and the base voltages are always equal. Since they are made as equivalent transistors, the current is always the same and there is a relationship h=f (3).

When Tr17 is off, Tr18 is saturated. Tr1
Since all I11 flows through 8, f and h become 0. In other words, e=I12, and this much current flows through R8.

Then, the base of the transistor Tr12 rises by R8I12. These are upward hysteresis.

When the base voltage of Tr12 is higher than that of Tr11, the voltage at point X drops and Tr17 is turned off.
At this time, the feedback current e is positive, so Tr12
The base is R8I12 from the emitter U of Tr8.
, giving upward hysteresis +ΔV=R8I12 (4).

When the base voltage of Tr12 is lower than that of Tr11, the voltage at point X rises and Tr17 is turned on.
Since Tr18 is off, I11 is all connected to Tr19.
flows. h becomes equal to I11, and from equations (1) and (3), the feedback current e becomes e=I12-I11 (5). Set this so that it is negative.
Due to the negative feedback current, the base of Tr12 is connected to Tr8
The emitter voltage U will drop by the downward hysteresis -ΔV=(I12-I11)R8 (6).

If I12=I11/2 (7) is selected, the absolute values of upward and downward hysteresis will be equal.

Let me give an example. I11=20μA, I12=10μA, R8=
If it is 1KΩ, the hysteresis will be ±ΔV=±10mV.

FIG. 3a shows the voltage waveform at the base of the transistor Tr12. Above Vc, it becomes U + ΔV,
Below Vc, it becomes U-ΔV. Since there is hysteresis in this way, the output U (or u) of the differentiator circuit is above Vc between the upward pulse and the downward pulse, and is below Vc between the downward pulse and the upward pulse. Can be done.

E Output stage This amplifies the output of the comparator. Base of comparator Tr12 (U+
When ΔV) is higher than Vc, Tr17 is off.
Conversely, when (U-ΔV) is lower than Vc, Tr17 is on.

The output stage E includes transistors Tr21 to Tr24, resistors R11 to R13, and a diode D3.

A series body of a constant current circuit I13 and a transistor Tr21 is connected between Vcc and ground.

The collector of Tr22 is connected to Vcc via resistor R11.
The emitter is connected to ground via R12. The base of Tr22 is connected to the collector of Tr21.

In the final stage, resistor R1 is connected between Vcc and ground.
3. A series body of Tr23, diode D3, and Tr24 is connected. The base of the output transistor Tr23 is connected to the collector of Tr22, and the base of Tr24 is connected to the emitter of Tr22.

Diode D3 prevents reverse voltage from being applied to the emitter and base of Tr23. Output E is D3
It is taken out from the connection point of the collector of the transistor Tr24.

() When U+ΔV>Vc, the collector voltage of Tr17 increases. Tr21 turns on. Tr22 is turned off. The base voltage of Tr23 increases and the base voltage of Tr24 decreases. Tr2
3 becomes conductive, and Tr24 becomes non-conductive. Output E becomes "H".

() When U-ΔV<Vc, the collector voltage of Tr17 decreases. Tr21 turns off. Tr22 turns on. Tr23 is turned off and Tr24 is turned on. Output E becomes "L".

Diode D3 changes the collector voltage of Tr24,
By lowering the emitter voltage of Tr23 by the pn junction voltage drop (approximately 0.6V), Tr23 is prevented from becoming partially conductive when Tr22 is saturated.
D3 allows Tr23 to be more completely turned off.

FIG. 3b is a graph showing the waveform of the output E.
This restores the optical signal (Fig. 2 a, s)
I understand. Regardless of the strength of the optical signal, the width of the restored pulse is equal to the width of the original pulse. This is because the portion of the differential circuit that outputs differential pulses (upward and downward) is independent of the strength of the optical signal.

Because the signal is differentiated, the strength of the original optical signal does not directly appear in the subsequent signal. Even if the optical power is too high, a sharp pulse is generated and then the equilibrium state is reached immediately.
Since the signal returns to Tr3 and Tr4, there is no possibility that the transistor will become saturated due to a large signal and the operation will become slow.

(E) Structure of the present invention The optical receiver circuit of the present invention includes: (1) One or more diodes D1, ... are connected in the forward direction to the emitter of the transistor Tr1, and a light receiving element is connected to the base with a reverse bias for amplification. (2) a current-voltage conversion circuit A that converts a photocurrent into a voltage by a resistor R1 connecting the output of the transistor Tr2 and the base of the transistor Tr1; and (2) a current-voltage converted signal s and passing the signal to a delay circuit. and (3) a reference voltage generation circuit C that generates a constant reference voltage Vc that is predetermined to be equal to the average voltage of the differential signal. (4) A comparator that compares the differential signal plus a constant hysteresis voltage ±ΔV with the reference voltage Vc, and a constant positive voltage (+ΔV) on the differential signal when the differential signal is higher than the reference voltage Vc. and (5) an output stage E that amplifies the output of the comparison circuit D. It is composed of

(f) Effects The optical receiving circuit of the present invention can achieve the following excellent effects.

(1) You can get a large amount of dynamic cleansing.

This is because a differentiating circuit is used in the amplification section.

(2) Pulse distortion can be reduced.

This is because the differentiating circuit can accurately detect the changing points (rising, falling) of the input pulse.
The pulse width does not vary depending on the magnitude of the optical power.

(3) Can cancel the influence of dark current of the photodetector.

Since the dark current of a light-receiving element fluctuates depending on the temperature, it is difficult to eliminate the influence of dark current in conventional optical receiving circuits that perform DC amplification. In the present invention, since it passes through a differential circuit, all DC components such as dark current are cut out.

(4) Decrease in frequency characteristics caused by junction capacitance of the light-receiving element can be improved to some extent.

This is because the light receiving element is connected to the base of the transistor in a reverse bypass manner, and one or more (two in this example) diodes are connected to the emitter of this transistor in the forward direction. Therefore, the reverse voltage applied to the light receiving element increases, and the frequency characteristics are improved.

In the conventional circuit shown in FIG. 4, the output Vd is always lower than the battery potential _V0 . In order to widen the output range, V ₀ must be increased,
It was not possible to apply a sufficient reverse voltage to the light receiving element.

(5) Since large capacitance capacitors are not required, it can be made into a completely monolithic IC. This results in a small, reliable, and easy-to-use device.

[Brief explanation of drawings]

FIG. 1 is an optical receiving circuit diagram according to an embodiment of the present invention.
FIG. 2 is an example diagram of waveforms of each circuit in the optical receiving circuit.
A solid line s in a indicates the output s of the current-voltage conversion circuit, and a broken line t indicates the output t of the delay circuit. b
represents the output u (or U) of the differentiating circuit when the optical power is small. c indicates the output u (or U) of the differentiating circuit when the optical power is large. 3a shows the base voltage waveform of one of the transistors constituting the comparator of the comparison circuit D, and FIG. 3b shows the voltage waveform of the output E of the output stage. FIG. 4 is a circuit diagram of an amplifier section of an optical receiving circuit according to a conventional example. FIG. 5 is a waveform diagram for explaining that the pulse width varies depending on the magnitude of the amplified signal. a is the amplified signal S ₁ , S ₂ ,
The waveform of _S3 is shown. The pulse width is the same. The reference voltage of the comparator is fixed at a constant value Vc.
b, c, and d show pulse waveforms when the signals S ₃ , S ₂ , and S ₁ are binarized by the comparators. w ₃ , w ₂ ,
w ₁ is the width of each binarized pulse. A... Current-voltage conversion circuit, B... Differential circuit,
C... Reference voltage generation circuit, D... Comparison circuit, E...
...Output stage, I1-I13... Constant current circuit, R1-
R13...Resistor, Tr1-Tr24...Transistor, C1, C2...Capacitor, D1-D3...
Diode, PD...Photodiode, U...Signal from the differentiation circuit, Vc...Reference voltage of the comparator of the comparison circuit, ±ΔV...Positive and negative hysteresis voltage.

Claims (1)

[Claims] 1 One or more diodes D1, . A differential signal is generated by differentially amplifying the current-voltage converted signal s and the signal t which is passed through a delay circuit. a differentiating circuit B that generates a constant reference voltage that is predetermined to be equal to the average voltage of the differential signal, a reference voltage generating circuit C that generates a constant reference voltage that is predetermined to be equal to the average voltage of the differential signal, a constant hysteresis voltage ±ΔV added to the differential signal, and a reference potential. When the differential signal is higher than the reference voltage Vc, a constant positive voltage (+ΔV) is applied to the differential signal, and when the differential signal is lower than the reference voltage Vc, a constant negative voltage (-ΔV) is applied to the differential signal. An optical receiving circuit characterized in that it is comprised of a comparator circuit D that additionally includes a hysteresis imparting circuit, and an output stage E that amplifies the output of the comparator circuit D. 2 The hysteresis applying circuit is a resistor 8 connected between the output U of the differentiating circuit B and the input of the comparator.
, constant current circuits I11 and I12, transistors Tr19 and Tr20 whose collectors are connected to these and whose emitters are grounded, and whose collectors are connected to the constant current circuit I
Connected to 11 and turned on and off by the output of the comparator
The base and collector of the transistor Tr19 are connected to each other, and the collector of the transistor Tr20 is connected to the input of the comparator and one end of the resistor R8.
When the entire current of I11 flows through the transistor Tr18, a constant current I12 flows from the constant current circuit I12 through the resistor R8 in the direction of the output of the differentiating circuit, and when the transistor Tr18 is off, the constant current I12 flows through the resistor R8 in the direction toward the transistor Tr20. (I11-I12)
2. The optical receiving circuit according to claim 1, wherein a current flows through the optical receiving circuit.