JPH0422877B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in an insulating crystal substrate on which a semiconductor layer can be grown. For convenience, in this specification, the term "substrate" simply refers to the lowest layer, regardless of whether it is an insulating crystal or a semiconductor crystal.
The term "substrate" refers to anything on which an insulating crystal layer is grown, a semiconductor layer is grown, or a processed material is formed on the "substrate".

Prior Art and Problems Several types of insulating crystal substrates with an SOI (silicon on insulator) structure have been known.

FIG. 1 is a cutaway side view of essential parts showing an SOS (silicon on sapphire) structure, which is an example of such an insulating crystal substrate.

In the figure, 1 is sapphire (α-Al ₂ O ₃ ),
2 shows a substrate made of magnesium spinel (MgO.Al ₂ O ₃ ), etc., and 2 shows a silicon (Si) layer, respectively. In addition, MgO・Al ₂ O ₃ is exactly (MgO)
x.(Al ₂ O ₃ ) _1-x (0<x<1), which is abbreviated as described above in this specification.

When a semiconductor device is fabricated using this insulating crystal substrate, it has excellent features such as reduced stray capacitance and easy and complete isolation between elements. .

However, there are also disadvantages, for example, the thermal expansion coefficients of the substrate 1 and the silicon layer 2 are significantly different, so that if the silicon layer 2 is formed to be thick, the wafer may warp significantly.
This causes inconvenience in the normal semiconductor device manufacturing process.

In addition, with silicon/sapphire structure,
Due to the difference in lattice constant between silicon and sapphire, silicon is prone to defects and its crystal quality is poor, so even though MOS (metal oxide semiconductor) transistors are good, they cannot be used in devices such as bipolar transistors where junctions are important. If you manufacture a semiconductor device that fulfills its role, you will not be able to obtain one with good characteristics.

Furthermore, in the silicon/magnesia spinel structure, although the crystal quality of the silicon layer is good, since high quality magnesia spinel cannot be obtained, the substrate 1 is likely to break.

FIG. 2 is a cross-sectional side view of a main part of a semiconductor wafer developed by the present inventors in order to eliminate the drawbacks of the conventional example explained with reference to FIG.

In the figure, 3 indicates a silicon substrate, 4 indicates a magnesia spinel layer, and 5 indicates a silicon layer.

This conventional example has a structure in which a magnesia spinel layer 4 is epitaxially grown on a silicon substrate 3, and a silicon layer 5 is further epitaxially grown on top of that, so the crystallinity of the magnesia spinel layer is The crystal quality of the silicon layer 5 is also excellent compared to that of the conventional example shown in FIG. 1, and it is fully possible to form a bipolar transistor.

Further, since the magnesia spinel layer 4 is sandwiched between the silicon substrate 3 and the silicon layer 5, no warpage occurs.

However, even this conventional example is not completely satisfactory from the viewpoint of crystal quality.
There is still room for improvement. That is, in this conventional example, there are surprisingly many crystal defects such as stacking faults. A possible cause of this is a crystal lattice misfit between the silicon layer 5 and the magnesia spinel layer 4.

Purpose of the Invention The present invention provides that when, for example, a silicon layer is grown on the surface, the misfit of the crystal lattice between the silicon layer and the silicon layer is reduced, and as a result, a high quality silicon layer with few crystal defects can be obtained. We are trying to provide an insulating crystal substrate that can.

Structure of the Invention The insulating crystal substrate of the present invention has a structure including a magnesia layer and a magnesia spinel layer formed in this order on a magnesia spinel substrate or a magnesia spinel layer. , it is possible to grow silicon, gallium arsenide (GaAs), gallium phosphide (GaP), etc. with good crystallinity on the top layer, the magnesia spinel layer.

Embodiment of the Invention FIG. 3 is a cutaway side view of essential parts of an embodiment of the invention.

In the figure, 6 is a silicon substrate, 7 is a magnesia spinel layer, 8 is a magnesia (MgO) layer,
9 indicates a magnesia spinel layer, and 10 indicates a silicon layer.

Next, the features of the embodiment shown in FIG.
This will be explained with reference to the figures.

FIG. 4 is a diagram showing the lattice constant of the magnesia spinel system.

The magnesium spinel layer formed on a silicon substrate that has been obtained to date has a lattice constant of 7.9 [Å] to 7.9 [Å], as shown in B in the figure.
The range is 8.08 [Å], but due to problems with crystallinity, the range of 7.9 [Å] to 8.01 [Å] is practical.

When silicon grows on magnesia spinel, it has a double lattice of magnesia spinel,
Triple lattice of silicon (16.29 [Å] = 5.43 [Å] x 3)
It is believed that the misfit is 0%, and the lattice constant is
8.15 [Å], that is, it is necessary to use a material indicated by A in the figure as a substrate, which cannot be achieved with the current insulating crystal substrate made of magnesia spinel/silicon. However, the present inventors used a growth substrate with a lattice constant of 4.21 [Å].
When a magnesia-spinel layer was grown on top of magnesia with did it.

For this reason, a magnesia spinel layer is placed on a silicon substrate, and a magnesia layer is placed on top of that.
Furthermore, by growing a magnesia spinel layer thereon, an insulating crystal substrate with less crystal lattice misfit with silicon can be obtained.

Based on this knowledge, the present inventors discovered that magnesia
When magnesia growth experiments were repeated using a spinel/silicon system, the double lattice was 8.35 [Å] to 8.45 Å, as shown as D in the figure.
[Å], therefore, the lattice constant is 4.17 [Å] to 4.22
Since we were able to grow magnesia of [Å], we were able to grow a magnesia spinel layer and a silicon layer in order on the magnesia layer, thereby achieving the intended purpose.

Next, this experiment will be explained in detail.

FIG. 5 is an explanatory diagram of a main part of a vapor phase growth apparatus in which a magnesia spinel layer and a magnesia layer are grown according to the present invention.

In the figure, 11 is a reaction tube, 12A, 12B,
12C is a gas introduction pipe, 13 is a source chamber,
14A and 14B are source boats, 15 is a wafer holder, 16 is a wafer, 17 is an exhaust pipe, 18
A, 18B, 18C are resistance furnaces, 19A, 19B,
19C indicates arrows representing gas inflow.

In this device, a source boat 14A containing MgCl 2 is placed in the upper stage of a source chamber 13 installed in a reaction tube 11, and the source boat 14A containing MgCl ₂ is heated in a resistance furnace 18B to produce gaseous MgCl _{2 .} occurs,
The gaseous MgCl ₂ is sent onto the wafer 16 by the H ₂ gas which is introduced from the gas introduction pipe 12A and acts as a carrier gas.

In addition, a source boat 14 containing metal aluminum (Al) is placed at the bottom of the source chamber 13.
B is placed and heated in the resistance furnace 18A, and reacts with HCl gas fed together with H ₂ gas as a carrier gas from the gas introduction pipe 12B to generate gaseous AlCl ₃ . Similarly, wafer 16
sent to the top.

Furthermore, CO ₂ gas, which is introduced from the gas introduction pipe 12C together with H ₂ gas as a carrier gas, is also sent onto the wafer 16.

In such an atmosphere, on the wafer 16 heated by the resistance furnace 18C, a reaction as shown in the following equation occurs and magnesia spinel grows.

MgCl ₂ +2AlCl ₃ +4CO ₂ +4H ₂ →MgO・Al ₂ O ₃ +8HCl+4CO Also, magnesia was grown in the same equipment as the one used to grow magnesia spinel, in which the temperature was lowered in a resistance furnace 18A, and a gas inlet pipe was used to grow the magnesia. From 12B
The growth was carried out in the same manner as the growth of magnesia spinel described above, with only H ₂ gas being introduced and the generation of AlCl ₃ being stopped.

At this time, magnesia grows on the wafer 16 by a reaction as shown in the following equation.

MgCl ₂ +CO ₂ +H ₂ →MgO+2HCl+CO The conditions under which the growth experiment was carried out as described above are listed below.

Substrate material: Silicon Surface index: (100) Diameter: 5 [cm] (2 [inches]) First layer magnesia spinel growth temperature T _sub = 925 [℃] MgCl ₂ temperature T ₁ = 850 [℃] CO ₂ Flow rate F ₁ = 200 [cc/min] HCl flow rate F ₂ = 25 [cc/min] H ₂ flow rate F ₃ = 20 [l/min] Growth film thickness t ₁ = 0.4 [μm] Magnesia growth temperature T _sub = 925 [℃] MgCl ₂ temperature T ₁ = 830 [℃] CO ₂ flow rate F ₁ = 100 [cc/min] H ₂ flow rate F ₃ = 20 [l/min] Growth film thickness t _M90 = 0.2 [μm] Second layer Magnesia spinel Same as the first layer magnesia spinel On the wafer 16 manufactured under these conditions, vapor phase epitaxial growth using the thermal decomposition of monosilane (SiH ₄ ) gas, which has been widely used in the past, was performed. A silicon layer with a thickness of 40 [μm] was grown at a growth temperature of 950 [°C].

Thereafter, the crystallinity of the magnesia spinel layer and the magnesia layer was evaluated by X-ray diffraction.

As a result, both the first and second magnesia spinel layers or magnesia layers have good crystallinity, and the lattice constant of the first magnesia spinel layer is 8.01 [Å]. The magnesia layer
4.17 [Å], the second layer of magnesia spinel layer
It was 8.08 [Å].

Furthermore, the silicon layer finally grown was etched using a mixed solution of potassium dichromate and fluoric acid (so-called Secco etching solution), and the density of crystal defects was measured.

As a result, it was possible to obtain a stacking fault (SF) density of 7.1×10 ⁵ [cm ^-2 ] on the surface of the silicon layer.

FIG. 6 is a micrograph showing the state of crystal defects on the surface of the silicon layer, and the magnification is 1×1100.

A in the figure shows the surface of the silicon layer in the wafer obtained by the embodiment of the present invention, and in the figure,
What looks like a line is a stacking fault, an example of which is indicated by an arrow.

In addition, b is the silicon/
The state of crystal defects on the surface of the silicon layer in the magnesia spinel/silicon structure is posted for comparison, and the stacking fault density in this case is
It is approximately 7.6×10 ⁶ [cm ^-2 ]. Even with this level, the conventional one shown in Figure 1 is 2.3
~11.0×10 ⁶ [cm ^-2 ], which is excellent in comparison.

Therefore, there are significant advantages when the present invention is applied.

By the way, the present inventors set the MgCl ₂ temperature T ₁ as the magnesia growth condition, 700 [℃]≦T ₁ ≦950 [℃], and the magnesia growth temperature T _sub as 700 [℃]≦T _sub ≦1200 [℃]. ℃] Growth experiments were conducted by changing the growth rate S _G as follows: 0.01 [μm/min] ≦ S _G S _G ≦ 1 [μm/min], but in all cases, the crystallinity was good. Magnesia grows, and its lattice constant is 4.17 [Å] to 4.22 [Å]. When the wafer shown in Figure 3 was fabricated using this magnesia, the stacking fault density in the silicon layer was 0.46 to 4.22 [Å]. 1.2×10 ⁶ [cm ⁻² ] was obtained, which was able to be reduced to 1/2 to 1/10 of that obtained using the conventional technology.

In the above embodiment, magnesia was grown using a vapor phase growth apparatus that grew magnesia spinel, but it was also possible to grow magnesia using a vapor phase growth apparatus dedicated to growing magnesia, as illustrated in FIG. It's okay. In FIG. 7, the same parts as those explained in connection with FIG. 5 are indicated by the same symbols.

Furthermore, it goes without saying that the two magnesia spinel layers and the magnesia layer described above may be grown successively in the same growth apparatus.

By the way, conventionally, in a semiconductor wafer having an SOI structure, a recess is formed in the semiconductor substrate, and a semiconductor region for forming a semiconductor element in the recess is provided insulated from other parts, thereby achieving high voltage insulation. However, when manufacturing such wafers, it is not possible to obtain a high-quality silicon layer, and the ion implantation method is used to add silicon dioxide into the silicon semiconductor substrate. (SiO ₂ ) layer and use it as an insulating substrate, or by forming a convex part on a silicon semiconductor substrate and alternately stacking silicon dioxide layers and polycrystalline silicon layers on it. There is also a known technique of forming an insulating substrate and then polishing the silicon semiconductor substrate from the back side to remove all the remaining parts except for the convex portions, but all of these techniques are expensive.

However, the present invention is also extremely effective when manufacturing semiconductor wafers having such a structure.
Next, this will be explained in detail.

FIG. 8 is a cross-sectional side view of a main part of another embodiment of the present invention, in which, as described above, a recess is formed in a semiconductor substrate, and a semiconductor region for forming a semiconductor element is formed in the recess. A semiconductor wafer provided insulated from others is illustrated.

In the figure, 21 is a silicon semiconductor substrate;
A is a recess formed in the silicon semiconductor substrate 21;
22 is a magnesia spinel layer, 23 is a magnesia layer, 24 is a magnesia spinel layer, and 25 is a silicon active layer.

FIGS. 9 to 13 are cross-sectional side views of the main parts of a semiconductor wafer at key points in the process to explain the manufacturing of the embodiment shown in FIG. 8, and these figures will be referred to below. I will explain as I go along. In each figure, the same parts as those explained in connection with FIG. 8 are indicated by the same symbols.

See FIG. 9. For example, a silicon dioxide film (not shown) is formed on the silicon semiconductor substrate 21 by applying a thermal oxidation method, and patterning is performed by applying ordinary photolithography technology to the silicon dioxide film (not shown).
An opening is formed in the portion where the recess is to be formed.

Using the silicon dioxide film as a mask, the silicon semiconductor substrate 21 is etched to a depth of, for example, ? A recess 21A of approximately [μm] is formed, and then the silicon dioxide film serving as a mask is removed.

See Figure 10. For example, by applying the vapor phase growth method, magnesia
The spinel layer 22 is grown to a thickness of, for example, about 0.4 [μm].

See FIG. 11. For example, by applying a vapor phase growth method, the magnesia layer 23 is grown to a thickness of, for example, about 0.2 [μm].

See Figure 12. For example, by applying the vapor phase growth method, magnesia
The spinel layer 24 is grown to a thickness of, for example, about 0.4 [μm].

Refer to FIG. 13. For example, by applying a vapor phase growth method, the silicon active layer 25 is grown to a thickness of, for example, about 35 [μm].

See FIG. 8. For example, by applying a polishing method such as etching or lapping, until the silicon active layer 25 in the recess 21A is completely isolated from the surroundings,
Unnecessary silicon active layer 25 is removed to flatten the surface.

It goes without saying that the silicon active layer 25 in the semiconductor wafer produced in this way is of high quality with few crystal defects and also has a high breakdown voltage.

Effects of the Invention The insulating crystal substrate of the present invention has a structure including a magnesia layer and a magnesia spinel layer formed in this order on a magnesia spinel substrate or a magnesia spinel layer, and the magnesia spinel layer on the surface Since the lattice constant of the spinel layer is increased, when silicon, gallium arsenide, gallium phosphide, etc. are grown on it, the lattice misfit between the magnesia spinel layer and the grown crystal layer must be significantly reduced. As a result, crystal defects are reduced and a high quality product is obtained. Moreover, the same type of semiconductor layer (or substrate) is formed under the bottom magnesia spinel layer and on the top magnesia spinel layer. Since it is possible to have the presence of , there is almost no warping of the insulating crystal substrate.

Therefore, when a semiconductor device is manufactured using this insulating crystalline substrate, excellent characteristics can be obtained, and there are no inconveniences in the manufacturing process.

[Brief explanation of drawings]

Figures 1 and 2 are cut-away side views of essential parts of different conventional examples, Figure 3 is a cut-away side view of essential parts of an embodiment of the present invention, and Figure 4 shows lattice constants in the magnesia-spinel system. Fig. 5 is an explanatory view of the main part illustrating the vapor phase growth apparatus used in manufacturing an embodiment of the present invention, and Fig. 6 a and b are micrographs showing the crystal structure on the surface of the silicon layer. , FIG. 7 is an explanatory diagram of a main part illustrating a vapor phase growth apparatus used in manufacturing one embodiment of the present invention, FIG. 8 is an explanatory diagram of a main part of another embodiment of the present invention, and FIG. 9 13 to 13 respectively represent cut-away side views of essential parts of the insulating crystal substrate at key points in the process for explaining the case of manufacturing the embodiment shown in FIG. 8. In the figure, 6 is a silicon substrate, 7 is a magnesia spinel layer, 8 is a magnesia layer, 9 is a magnesia spinel layer, and 10 is a silicon layer.

Claims (1)

[Claims] 1. An insulating crystal substrate comprising a magnesia layer and a magnesia spinel layer sequentially formed on a magnesia spinel substrate or a magnesia spinel layer.