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JPH0618174B2 - Semiconductor substrate - Google Patents
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JPH0618174B2 - Semiconductor substrate - Google Patents

Semiconductor substrate

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Publication number
JPH0618174B2
JPH0618174B2 JP16030286A JP16030286A JPH0618174B2 JP H0618174 B2 JPH0618174 B2 JP H0618174B2 JP 16030286 A JP16030286 A JP 16030286A JP 16030286 A JP16030286 A JP 16030286A JP H0618174 B2 JPH0618174 B2 JP H0618174B2
Authority
JP
Japan
Prior art keywords
film
substrate
silicon
stabilized zirconia
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16030286A
Other languages
Japanese (ja)
Other versions
JPS6315442A (en
Inventor
司 土居
修治 榎本
敏幸 篠崎
良亘 柿原
文弘 厚主
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16030286A priority Critical patent/JPH0618174B2/en
Publication of JPS6315442A publication Critical patent/JPS6315442A/en
Publication of JPH0618174B2 publication Critical patent/JPH0618174B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、主に半導体基板の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention mainly relates to improvement of a semiconductor substrate.

(ロ)従来の技術 SOS(silicon on sapphire )基板が、シリコン基板
の代わりに半導体用絶縁物基板として用いられるように
なってきている。これは、サファイア単結晶基板上にシ
リコン薄膜をエピタキシャル成長させて成形したもの
で、集積回路製作に必要な素子間分離(アイソレーショ
ン)を容易にするとともに、配線容量と拡散容量を小さ
くすることにより、集積回路の高密度化と高速化をはか
ろうとするものである。
(B) Conventional Technology SOS (silicon on sapphire) substrates have come to be used as insulator substrates for semiconductors instead of silicon substrates. This is formed by epitaxially growing a silicon thin film on a sapphire single crystal substrate, and facilitates element isolation (isolation) required for integrated circuit fabrication, and by reducing the wiring capacitance and diffusion capacitance, The aim is to increase the density and speed of integrated circuits.

(ハ)発明が解決しようとする問題点 しかしながら、サファイア基板上に高温で、たとえば、
シリコンをエピタキシャル成長させると、原料ガスのキ
ャリヤーに使用している水素によってサファイア基板の
一部が還元され、その上に形成したシリコン膜中に金属
Alもしくは酸素がドープされてシリコン膜が汚染され
ることがある。しかも、エピタキシャルシリコンと基板
サファイアのエピタキシャル面における格子間隔が著し
く異り(約10%)、ミスフィット転位が高密度に含まれ
るためエピタキシャルシリコンの結晶性が低下する。し
たがってサファイア基板上にエピタキシャル成長したシ
リコン半導体層に形成した素子の電気的特性が著しく低
下する。さらに、またサファイア基板自体は他の半導体
基板にくらべて高価である。
(C) Problems to be solved by the invention However, at high temperature on a sapphire substrate, for example,
When silicon is epitaxially grown, a part of the sapphire substrate is reduced by hydrogen used as a carrier of the source gas, and the silicon film formed on the sapphire substrate is doped with metal Al or oxygen to contaminate the silicon film. There is. Moreover, the lattice spacing between the epitaxial silicon and the substrate sapphire is significantly different (about 10%), and misfit dislocations are contained at a high density, which lowers the crystallinity of the epitaxial silicon. Therefore, the electrical characteristics of the device formed on the silicon semiconductor layer epitaxially grown on the sapphire substrate are significantly deteriorated. Furthermore, the sapphire substrate itself is more expensive than other semiconductor substrates.

この発明は、このような事情を考慮してなされたもの
で、高性能で安価な半導体基板を提供するものである。
The present invention has been made in consideration of such circumstances and provides a high-performance and inexpensive semiconductor substrate.

(ニ)問題点を解決するための手段 この発明は、シリコン基板と、そのシリコン基板に被覆
される安定化ジルコニア単結晶膜と、上記安定化ジルコ
ニア単結晶膜の被覆されたシリコン基板をO雰囲気で
熱処理することにより上記シリコン基板と上記安定化ジ
ルコニア単結晶膜の間に形成されるSiO膜とを備え
てなることを特徴とする半導体基板である。
(D) Means for Solving the Problems The present invention provides a silicon substrate, a stabilized zirconia single crystal film coated on the silicon substrate, and a silicon substrate coated with the stabilized zirconia single crystal film on an O 2 substrate. A semiconductor substrate comprising a silicon substrate and a SiO 2 film formed between the stabilized zirconia single crystal film by heat treatment in an atmosphere.

前記安定化ジルコニア単結晶膜は酸化ジルコニウムZr
中に、Y,MgO,CaO,Sm,G
,Tb,Yb,Scなどの
うちの一種あるいは複数を安定化剤として添加して形成
した単結晶膜を用いることが好ましい。
The stabilized zirconia single crystal film is made of zirconium oxide Zr.
O in 2, Y 2 O 3, MgO , CaO, Sm 2 O 3, G
It is preferable to use a single crystal film formed by adding one or more of d 2 O 3 , Tb 2 O 3 , Yb 2 O 3 , Sc 2 O 5 and the like as a stabilizer.

(ホ)作 用 半導体基板の表面は酸化物単結晶の安定化ジルコニア膜
によって覆われている。したがって高温で安定であるた
め、サファイア基板のように還元反応がおこってエピタ
キシャル成長半導体層が汚染されることがない。また安
定化ジルコニアが薄膜であっても、熱酸化により安定化
ジルコニア膜とシリコン基板の間に形成されたSiO
層が電気的特性を向上させる役割を果すとともに、シリ
コン基板を用いることにより熱誇張率差に基づく残留応
力を低減することができる。
(E) Working The surface of the semiconductor substrate is covered with a stabilized zirconia film of oxide single crystal. Therefore, since it is stable at high temperature, reduction reaction does not occur and the epitaxially grown semiconductor layer is contaminated unlike the sapphire substrate. Even if the stabilized zirconia is a thin film, SiO 2 formed between the stabilized zirconia film and the silicon substrate by thermal oxidation.
The layer plays a role of improving electric characteristics, and by using the silicon substrate, the residual stress due to the difference in thermal exaggeration ratio can be reduced.

(ヘ)実施例 以下、図面に示す実施例に基づいてこの発明を詳述す
る。なお、これによってこの発明が限定されるものでは
ない。第1図(a)〜第1図(c)はこの発明の一実施例の製
造工程と構成を示す説明図である。
(F) Embodiment Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. The present invention is not limited to this. 1 (a) to 1 (c) are explanatory views showing the manufacturing process and structure of an embodiment of the present invention.

まず、第1図(a)に示すようにシリコン基板(1)の表面に
存在する自然酸化膜の影響を除去するため、基板処理を
施こす。この実施例における基板処理には、予めHCl
とHとHOとを3:1:1の割合で溶解し、90
〜 100℃に熱した溶液に 5〜10分間浸して表面処理した
基板を、スパッタ装置内で真空中( 3×10-5pa)、 900
℃、30分熱処理する方法を用いた。
First, as shown in FIG. 1 (a), a substrate treatment is performed to remove the influence of the natural oxide film existing on the surface of the silicon substrate (1). Before processing the substrate in this embodiment, HCl was previously used.
And H 2 O 2 and H 2 O are dissolved in a ratio of 3: 1: 1, 90
The substrate surface-treated by immersing it in a solution heated to ~ 100 ° C for 5 to 10 minutes is vacuumed (3 × 10 -5 pa) in a sputtering system,
A method of heat treatment at ℃ for 30 minutes was used.

次に第1図(b)に示すようにシリコン基板(1)の全面にC
VD法,スパッタ法,原子層エピ法,ICB法,減圧C
VD法のいずれかにより単結晶安定化ジルコニア膜(2)
を被覆する。この実施例においては、シリコン基板( 1
00)1の全面に安定化ジルコニア膜2をAr+Oガス
を用いて反応性マグネトロンスパッタ法により作製し
た。そのスパッタは、ガス圧(Ar+O) 0.5pa、R
f出力4W/cm2、基板温度 900℃の条件のもとで行う
ようにし、立方晶の単結晶の安定化ジルコニア膜2を膜
厚3000Åに成長させた。またジルコニア膜の安定化は、
酸化ジルコニウムZrOの中に安定剤として、酸化イ
ットリウムYや酸化マグネシウムMgO、酸化カ
ルシウムCaO、酸化サマリウムSm、酸化ガド
リニウムGd、酸化テルビウムTb、酸化
イッテリビウムYb、酸化スカンジウムSc
等のうちの1種または複数を10モル%前後添加するこ
とにより行ない、成長温度 550℃〜1000℃で立方晶の単
結晶膜を得るようにした。
Next, as shown in FIG. 1 (b), C is deposited on the entire surface of the silicon substrate (1).
VD method, sputtering method, atomic layer epitaxy method, ICB method, low pressure C
Single crystal stabilized zirconia film by either VD method (2)
To cover. In this embodiment, the silicon substrate (1
A stabilized zirconia film 2 was formed on the entire surface of (00) 1 by a reactive magnetron sputtering method using Ar + O 2 gas. The sputter is gas pressure (Ar + O 2 ) 0.5pa, R
Under the conditions of f output of 4 W / cm 2 and substrate temperature of 900 ° C., a cubic single crystal stabilized zirconia film 2 was grown to a film thickness of 3000 Å. The stabilization of the zirconia film is
As a stabilizer in zirconium oxide ZrO 2 , yttrium oxide Y 2 O 3 , magnesium oxide MgO, calcium oxide CaO, samarium oxide Sm 2 O 3 , gadolinium oxide Gd 2 O 3 , terbium oxide Tb 2 O 3 , ytterbium oxide Yb. 2 O 3 , scandium oxide Sc 2 O
It was carried out by adding about 10 mol% of one or a plurality of 5 or the like to obtain a cubic single crystal film at a growth temperature of 550 ° C to 1000 ° C.

次に、第1図(c)に示すように熱酸化(たとえば、dry
酸化,スチーム酸化又はパイロジュニック酸化な
ど)をおこなうことによって、シリコン基板1と安定化
ジルコニア膜2の間にSiO層3を形成する。この実
施例では 900℃、1時間のスチーム酸化を行ない、1500
ÅのSiO膜3を形成した。即ち、安定化ジルコニア
膜2が高温で酸素導伝体であることを利用してシリコン
基板1と安定化ジルコニア膜2の界面にSiO膜3を
形成した。
Next, as shown in FIG. 1 (c), thermal oxidation (for example, dry
The SiO 2 layer 3 is formed between the silicon substrate 1 and the stabilized zirconia film 2 by performing O 2 oxidation, steam oxidation, pyrogenic oxidation, or the like. In this example, steam oxidation was carried out at 900 ° C. for 1 hour to obtain 1500
The Å SiO 2 film 3 was formed. That is, the SiO 2 film 3 was formed at the interface between the silicon substrate 1 and the stabilized zirconia film 2 by utilizing the fact that the stabilized zirconia film 2 is an oxygen conductor at high temperature.

第2図は、この半導体基板を用いたシリコン基板の構成
例を示し、シリコンの半導体エピタキシャル層4は、モ
ノシラン(SiH),四塩化ケイ素(SiCl)ジ
クロロシラン(SiHCl)などの原料ガスを、 9
50〜1250℃に加熱した半導体基板全面にわたって作用さ
れることにより、 0.3〜20μmの厚さの範囲内に形成さ
れる。より具体的には、例えばSiHガスの熱分解に
よる常圧CVD法によって安定化ジルコニア膜2上にS
iのヘテロエピタキシャル成長を行う。そのSiのエピ
タキシャル成長を、成長温度 950〜1250℃、H流量 1
00/分、SiH濃度 0.1%の条件のもとで行なえ
ば、良好な単結晶成長膜を形成することができる。
FIG. 2 shows an example of the structure of a silicon substrate using this semiconductor substrate. The silicon semiconductor epitaxial layer 4 is made of monosilane (SiH 4 ), silicon tetrachloride (SiCl 4 ) dichlorosilane (SiH 2 Cl 2 ), or the like. Raw gas, 9
By acting on the entire surface of the semiconductor substrate heated to 50 to 1250 ° C., it is formed in the thickness range of 0.3 to 20 μm. More specifically, for example, S is formed on the stabilized zirconia film 2 by an atmospheric pressure CVD method by thermal decomposition of SiH 4 gas.
i heteroepitaxial growth is performed. The Si epitaxial growth is performed at a growth temperature of 950 to 1250 ° C. and a H 2 flow rate of 1
A good single crystal growth film can be formed under the condition of 00 / min and SiH 4 concentration of 0.1%.

このように、この発明の半導体基板は、酸化物の単結晶
膜を直接シリコン基板上に形成し、単結晶安定化ジルコ
ニア膜が高温で酸素導伝体であることを利用してシリコ
ン基板と安定化ジルコニア膜の界面にSiO層を形成
し、単結晶安定化ジルコニア膜とSiO層との組み合
わせによって耐圧特性、界面特性などを改善するもので
ある。また、単結晶安定化ジルコニア薄膜は高温で安定
であるため、サファイア基板のように還元反応がおこっ
てエピタキシャル成長層に汚染を与えることがない。さ
らに、単結晶安定化ジルコニアは、シリコンと同じく立
方晶系結晶であり格子定数がシリコンの格子定数( 5.4
3 Å)に近く、エピタキシャルシリコンにミスフィット
転位が含まれにくい。
As described above, the semiconductor substrate of the present invention forms a single crystal oxide film directly on a silicon substrate, and utilizes the fact that the single crystal stabilized zirconia film is an oxygen conductor at high temperature to stabilize the silicon substrate. By forming a SiO 2 layer at the interface of the zirconia oxide film and combining the single crystal stabilized zirconia film and the SiO 2 layer, the breakdown voltage characteristic, the interface characteristic and the like are improved. In addition, since the single crystal stabilized zirconia thin film is stable at high temperature, it does not cause a reduction reaction unlike the sapphire substrate to give pollution to the epitaxial growth layer. Furthermore, single-crystal stabilized zirconia is a cubic crystal like silicon and has a lattice constant of silicon (5.4
It is close to 3Å) and misfit dislocations are hard to be included in epitaxial silicon.

なお、この発明はシリコン半導体デバイスだけでなくG
aAsやInPなどの化合物半導体デバイスにも適用出
来ることは言うまでもない。
The present invention is not limited to silicon semiconductor devices
It goes without saying that it can be applied to compound semiconductor devices such as aAs and InP.

(ト)発明の効果 この発明によれば、シリコン基板上に酸化物の単結晶膜
の形成された半導体基板が構成され、それによって高性
能で安価なSOI基板が提供される。
(G) Effect of the Invention According to the present invention, a semiconductor substrate in which an oxide single crystal film is formed on a silicon substrate is formed, and thereby a high-performance and inexpensive SOI substrate is provided.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜第1図(c)はこの発明の一実施例の製造工程
と構成を示す説明図、第2図は、この実施例の応用例を
示す説明図である。 (1)……シリコン基板、 (2)……単結晶安定化ジルコニア膜、 (3)……SiO層。
1 (a) to 1 (c) are explanatory views showing the manufacturing process and structure of one embodiment of the present invention, and FIG. 2 is an explanatory view showing an application example of this embodiment. (1) …… Silicon substrate, (2) …… Single crystal stabilized zirconia film, (3) …… SiO 2 layer.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 柿原 良亘 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 (72)発明者 厚主 文弘 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryokan Kakihara 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Fumihiro Atsushi 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】シリコン基板と、そのシリコン基板に被覆
される安定化ジルコニア単結晶膜と、上記安定化ジルコ
ニア単結晶膜の被覆されたシリコン基板をO雰囲気で
熱処理することにより上記シリコン基板と上記安定化ジ
ルコニア単結晶膜の間に形成されるSiO膜とを備え
てなることを特徴とする半導体基板。
1. A silicon substrate, a stabilized zirconia single crystal film coated on the silicon substrate, and a silicon substrate coated with the stabilized zirconia single crystal film, which is heat-treated in an O 2 atmosphere to obtain the silicon substrate. A semiconductor substrate comprising a SiO 2 film formed between the stabilized zirconia single crystal films.
JP16030286A 1986-07-08 1986-07-08 Semiconductor substrate Expired - Fee Related JPH0618174B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16030286A JPH0618174B2 (en) 1986-07-08 1986-07-08 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16030286A JPH0618174B2 (en) 1986-07-08 1986-07-08 Semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS6315442A JPS6315442A (en) 1988-01-22
JPH0618174B2 true JPH0618174B2 (en) 1994-03-09

Family

ID=15712024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16030286A Expired - Fee Related JPH0618174B2 (en) 1986-07-08 1986-07-08 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH0618174B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828080A (en) * 1994-08-17 1998-10-27 Tdk Corporation Oxide thin film, electronic device substrate and electronic device
FI117979B (en) 2000-04-14 2007-05-15 Asm Int Process for making oxide thin films
KR20030011083A (en) * 2000-05-31 2003-02-06 모토로라 인코포레이티드 Semiconductor device and method for manufacturing the same
US7452757B2 (en) * 2002-05-07 2008-11-18 Asm America, Inc. Silicon-on-insulator structures and methods
EP1975988B1 (en) * 2007-03-28 2015-02-25 Siltronic AG Multilayered semiconductor wafer and process for its production
CN101641806B (en) * 2007-03-30 2011-11-30 佳能株式会社 Epitaxial film, piezoelectric element, ferroelectric element, their manufacturing method, and liquid discharge head
JP7612383B2 (en) * 2020-11-02 2025-01-14 日産自動車株式会社 Capacitor and manufacturing method thereof

Also Published As

Publication number Publication date
JPS6315442A (en) 1988-01-22

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