JPH0424728B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an arithmetic method that uses a multi-bit input arithmetic element and enables arithmetic operations on multiple inputs having a smaller number of bits.

[Industrial application field]

The present invention relates to an arithmetic method using multi-bit input arithmetic elements.

When calculating two inputs consisting of n bits,
For example, when performing addition of two inputs, the sum output of both inputs can be obtained using a full adder for n bits, but as the number of bits in the operation input increases, the corresponding The number of full adder bits is also increasing.

In the early stages when multi-bit input arithmetic elements were not available, when performing arithmetic operations on multi-bit inputs, it was necessary to prepare the required number of easily available low-bit (for example, 4-bit) arithmetic elements to perform the desired operation. I was gone.

However, with the advancement of technology related to LSI, it has become possible to realize arithmetic elements for multi-bit inputs, and it has become possible to perform arithmetic operations for multi-bit inputs using one arithmetic element.

[Conventional technology]

However, when performing an operation using one such multi-bit input arithmetic element, the multi-bit input arithmetic element is effectively used when performing an operation on an input with the same number of bits as this arithmetic element. However, when performing an operation on an input with a smaller number of bits than the number of bits of the arithmetic element, this multi-bit input arithmetic element is not effectively utilized.

For example, when performing an operation using a 12-bit multi-bit input arithmetic element, when performing an operation on a 12-bit input, the multi-bit input arithmetic element is effectively used, but 1, 2, 3, 4, 5 When performing calculations on low-bit inputs such as bits, the higher bits are not used at all, so the multi-bit input calculation element is not used effectively.

[Problem that the invention seeks to solve]

In an arithmetic method using a multi-bit input arithmetic element, as described above, the multi-bit input arithmetic element is effectively used when performing an arithmetic operation on an input with the same or similar number of bits as this arithmetic element. but,
There is a problem in that it cannot be used effectively when performing an operation on an input with a smaller number of bits than the number of bits.

[Means for solving problems]

The means taken by the present invention to solve the above-mentioned problems in the conventional arithmetic system using multi-bit input arithmetic elements and achieve the above object will be explained with reference to FIG.

In FIG. 1, LBCD is a multi-bit input arithmetic element that computes multi-bit inputs A and B consisting of a maximum of N bits and outputs the computed output C.

A ₀ to A _N-1 are the input terminals of multi-bit input A, and A _0
ANI is the input terminal for the most significant bit.

B ₀ to _{B N-1} are the input terminals of multi-bit input B, and B ₀
is the input terminal for the least significant bit, and _BNI is the input terminal for the most significant bit.

C ₀ to C _N are output terminals for the calculation output C, with C ₀ being the output terminal for the least significant bit and C _N being the output terminal for the most significant bit.

Furthermore, since the calculation output for two inputs having a maximum of t bits is t+1 bits at most, the calculation output C for inputs A and B having a maximum of N bits is a maximum of N+1 bits.

a ₀ , b ₀ , a ₁ , b ₁ , . . . , a _n-1 , b _n-1 are m small-bit input pairs that are operated independently.

The maximum number of bits in any input pair a _i , b _i is P _i
Assuming that, m, P _i ( _i = 0 to m-1) is N
The selection is made so that the following conditional expression holds true for .

_n-1 〓 ⁱ⁼⁰ (P _i +1)≦N+1 ...(1) This equation (1) can be transformed as follows.

_n-1 〓 ⁱ⁼⁰ (P _i +1) + P _n-1 ≦N ...(2) m small-bit input pairs that satisfy this conditional expression
a ₀ , b ₀ , a ₁ , b ₁ , ..., a _n-2 , b _n-2 , a _n-1 , b _n-1
is applied to the input terminals A and B as shown in FIG. 1, for example, if the equality sign holds in the above equation.

a ₀ is input terminal A ₀ to _{A P0} , a ₁ is input terminal A (P ₀
+1) to A(P ₀ +P ₁ +2), ..., a _n-2 is the input terminal A(N-P _n-1 -P _n-2 -1) to A(N-P _n-1 -
1), a _n-1 is the input terminal A(N-P _n-1 ) to A(N-
1), respectively.

b ₀ is input terminal B ₀ ~ B _P0 , b ₁ is input terminal B (P ₀
+1) to B(P ₀ +P ₁ +2), ..., b _n-2 is the input terminal B(N-P _n-1 -P _n-2 -1) to B(N-P _n-1 -
1), b _n-1 is the input terminal B(N-P _n-1 ) to B(N-
1), respectively.

Each small bit input a _i , b _i is input such that the least significant bit of each small bit input matches the least significant bit at the corresponding input terminal.

Note here that a ₀ ~ a _n-2 and b ₀ ~ b _n-2
are respectively P ₀ +1, P ₁ +1, ..., P _n-2 +1
input to n-1 input terminals, but enters the top level a _n-1
and b _n-1 are points input to P _n-1 input terminals.

In this way, output terminals C ₀ to C _P0 have a ₀ and b ₀
The calculation output S ₀ is output, and the output terminal C (P ₀ +1)
The calculation output S ₁ of a ₁ and b ₁ is output to ~C (P ₀ + P ₁ + 2), ..., output terminal C (N-P _n-1 -P _n-2 -
1) The calculation output S n _- 2 of a _n-2 and b _n-2 is output to ~C (N-P _n-1 -1), and the output terminal C (N-P _n-1 ) ~
The calculation output S _n-1 of a _n-1 and b _n-1 is output to CN.
For each calculation output S _i , the least significant bit of its output terminal is the least significant bit of the calculation output.

The number of bits of the calculation output S ₀ , S ₁ , ..., S _n-2 , S _{n-1 is}
P ₀ +1, P ₁ +1, ..., P _n-2 +1, P _n-1 +1,
And all of them are a ₀ , b ₀ , a ₁ , b ₁ , ..., a _n-2 ,
Maximum number of bits for each input pair of b _n-2 , a _n-1 , b _n-1 P _{0
and P 1 , .}

At each input terminal to which each input a _i and b _i is input,
Since there is always no input to the most significant bit, ie, the P _i +1st bit, "0" is input.

When inputting each input a _i and b _i to input terminals A and B, it is sufficient that a _i and b _i are placed in the same bit position, and the order is arbitrary.

The above is a case where the equality sign holds in equation (1) or (2) above, but if the inequality sign holds, the number of empty bits is set to the upper bit part of a _n-1 and b _n-1. It can be placed as a "0" bit or inserted between any pair of inputs. In the latter case, it is necessary to insert an empty bit or "0" bit into the corresponding output terminal as well. The latter can ensure separation of adjacent inputs and calculation outputs and prevent malfunctions. Furthermore, the above effect can be more reliably achieved by filling empty bits with "0" rather than "1".

[Effect]

For multi-bit inputs A and B, multi-bit input arithmetic elements perform calculations in the same manner as in the prior art.

When m pairs of arithmetic inputs satisfying the above formula (1) (or (2)) are input, at least 1 bit is connected between the input terminals to which input A of the multi-bit input arithmetic element is applied. Input a ₀ , a ₁ , ... with intervals of
a _n-1 is input in an arbitrary array.

Similarly, an interval of at least 1 bit is provided between the input terminals of the multi-bit input arithmetic element to which input B is applied, and the corresponding arithmetic inputs a ₀ , a ₁ , . . .
..., a Input in the same arrangement as _n-1 .

If the equality sign holds in equation (1) (or (2)) above,
A one bit interval is provided between each input, and if an inequality holds, an interval of one bit or more is provided.

Each input a _i , b _i is input such that its least significant bit matches the least significant bit in its input terminal string. Furthermore, "0" is input to the next bit after the most significant bit, that is, the P _i +1st bit. When an empty bit is inserted between the P _i +1st bit and the least significant bit of the next input, it is better to also set "0" to the empty bit.

In this way, from the calculation output terminal of the multi-bit input calculation element, the calculation output of each input a _i and b _i is independently and independently transmitted from the output terminal corresponding to the input terminal of each input a _i and b _i . is output.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.
Figure 2 shows a multi-bit input arithmetic element LBCD that performs arithmetic operations on multi-bit inputs A and B with a maximum bit count of 16 bits and outputs an arithmetic output of a maximum of 17 bits.
This figure shows an example in which operations are performed on operation input pairs a ₀ , b ₀ and a ₁ , b ₁ whose maximum number of bits is 8 bits and 4 bits.

Since the calculations for multi-bit inputs A and B are the same as before, below, we will explain the small-bit calculation input pair a ₀ ,
Operations on b ₀ , a ₁ , and b ₁ will be explained.

A ₀ to _{A 15} are input terminals to which each bit of multi-bit input A is added, B ₀ to _{B 15} are input terminals to which each bit of multi-bit input B is added, and C ₀ to C ₁₆ are each bit of calculation output C. is the output terminal where is output.

This multi-bit input arithmetic element LBCD allows a small-bit input a ₀ whose maximum number of bits is 8 bits P ₀ =8.
and b ₀ operations, and the maximum number of bits is 4 bits P ₁
The operations on the small bit inputs a ₁ and b ₁ where =4 are performed in parallel and independently as follows.

Since P ₀ = 8, P ₁ = 4, m = 2, and N = 16, _n-1 〓 ⁱ⁼⁰ (P _i + 1) = 14, N + 1 = 17, and since 14 < 17, the above Conditional expression (1) (or (2)) is satisfied.

In this example, there are 3 empty bits (=17-14)
Therefore, in order to ensure separation between each input and calculation output and eliminate malfunction, input terminals A ₉ ,
A ₁₄ , A ₁₅ , B ₉ , B ₁₄ , B ₁₅ are empty bit terminals,
Enter “0” into these. Corresponding to these empty bits, C ₉ , C ₁₅ , and C ₁₆ on the output terminal side are made empty bits. At this time, from the output terminals C ₉ , C ₁₅ , C ₁₆ ,
Naturally, "0" is output.

The input _a0 inputs the least significant bit _a00 to the input terminal _A0 and the most significant bit _a07 to the input terminal _A7 . "0" is input to the input terminal _A8 next to the most significant bit _a07 . Correspondingly, the input b ₀ is
The least significant bit _b00 is input to input terminal _B0 , and the most significant bit _b07 is input to input terminal _B7 . "0" is input to the input terminal _B8 next to the most significant bit _b07 .

Input _a1 inputs the least significant bit _a10 to input terminal _A10 and the most significant bit _a13 to input terminal _A13 . Correspondingly, input b ₁ is
b ₁₀ is input to input terminal B ₁₀ , and the most significant bit b ₁₃ is input to input terminal B ₁₃ . Since inputs a ₁ and b ₁ are in the top level, input terminals A ₈ , in case of inputs a ₀ , b ₀
No input terminal corresponding to _B8 is required.

In this way, the small bit inputs a ₀ , b ₀ and a ₁ , b ₁
is input, the output terminals C ₀ to C ₈ of the multi-bit input arithmetic element LBCD output the calculation output S ₀ for the inputs a ₀ and b ₀ , and the output terminals C ₁₀ to C ₁₄ output the input
A calculation output S ₁ for a ₁ and b ₁ is output. output
In S ₀ and S ₁ , S ₀₀ and S ₁₀ are the least significant bits, and S ₀₈ and S ₁₄ are the most significant bits.

As described above, the small bit inputs a ₀ , b ₀ and a ₁ ,
Operations on the two sets of b ₁ can be performed in parallel and independently.

If an operation is to be performed on 2-bit input, it can be performed using the 3 empty bits. In that case, the three empty bit parts are naturally rearranged so that they are continuous. It should be noted that the present invention is not limited to the above embodiments.
Of course.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to perform calculations on original multi-bit inputs using conventional multi-bit input arithmetic elements, and in the case of small-bit inputs with a smaller number of bits, , it is possible to perform operations on multiple small bit inputs in parallel and independently. Therefore, the multi-bit input arithmetic element can be effectively utilized for both multi-bit input and small-bit input.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the calculation method of the present invention, and FIG. 2 is an explanatory diagram of an embodiment of the present invention. In Fig. 1, LBCD is a multi-bit input arithmetic element, A and B are multi-bit inputs, C is the arithmetic output of A and B, A ₀ to _{A N-1} are input terminals of input A, and B ₀ to B _{N- 1} is the input terminal of input B, C ₀ to C _N is the output terminal of calculation output C, a ₀ to a _n-1 and b ₀ to _{b n-1} are small bit inputs, S ₀
~S _n-1 indicates the calculation outputs of a ₀ and b ₀ , a ₁ and b ₁ , ..., a _n-1 and b _n-1, respectively.

Claims (1)

[Scope of Claims] 1. In an arithmetic method using a multi-bit input arithmetic element that performs arithmetic operations on two multi-bit inputs A and B with a maximum number of N bits and outputs an arithmetic output C of a maximum of (N+1) bits. , (a) m input pairs a ₀ that are operated independently of each other,
b ₀ , a ₁ , b ₁ , ..., a _n-1 , b _n-1 is the input pair a _i ,
When the maximum number of bits for b _i is P _i , it is an input pair that satisfies the relationship _n-1 〓 ⁱ⁼⁰ (P _i +1)≦N+1, and (b) the input A of the multi-bit input arithmetic element is Input the inputs a ₀ , a ₁ , ..., a _n-1 in an arbitrary arrangement to the input terminals to be added, with an interval of at least 1 bit between each input, and (c) input the inputs of the multi-bit input arithmetic element. An interval of at least 1 bit is provided between input terminals to which input B is applied, and corresponding calculation inputs a ₀ , a ₁ , . . .
Input b ₀ , b _{1 ,} ..., b _n-1 in the same arrangement as ..., a n-1, (d) Each input a _i , b _i has its least significant bit the lowest bit in its input terminal string. The bit is input to match the lower bit, and the next bit after the most significant bit, i.e.
“0” is input to the P _i +1st bit _, and (e ₎ each input a _i , b An arithmetic method using a multi-bit input arithmetic element, characterized in that the arithmetic output of b _i is taken out.