JPH0426735B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a debugging device, and particularly to a debugging device suitable for program development in a microcomputer.

(Prior Art) Debugging devices are used for program development on microcomputers and the like. This debugging device has a special CPU for emulation and a function to detect program errors. Generally, this type of debugging device is equipped with a RAM memory for replacement for debugging, and even if the memory in the device to be debugged is non-rewritable memory such as ROM, the contents of this ROM can be used for replacement. Since the program can be copied to memory and run, it can be rewritten as needed.

A typical error in a program is an error related to the usage division of memory space. This occurs, for example, when accessing a prohibited memory space or writing into a write-protected memory space.

An example of a conventional general debugging device is shown in FIG. Here, the components on the right side of the dash-dotted line are the components of this debugging device 100, and the components on the left side are the components of the device 200 to be debugged. device 20
0 has a CPU 210 and a memory 220, which are connected by an address bus A, a data bus D, and a control bus C. However, during debugging, the CPU 210 is removed and the debugging device 100 is connected instead. FIG. 2 shows the state during debugging.

This debugging device 100 is an emulation
It has a CPU 110 and a replacement memory 120, which are connected by an address bus a, a data bus d, and a control bus c. Further, the address bus a is connected to the address bus A via the address bus buffer 131, the data bus d is connected to the data bus D via the data bus buffer 132, and the control bus c is connected to the control bus buffer 133.
The emulation CPU 110 is connected to the control bus C via the
Both memory 220 and replacement memory 120 can be accessed. The replacement memory 120 is
Since it is composed of RAM, the memory 220
Even if it is a ROM, its contents can be rewritten by copying it to the replacement memory 120 via the emulation CPU 110.

This debugging device 100 handles errors when writing to a write-protected memory space.
That is, in order to detect a write error, the write detection circuit 141 and the write error signal generation circuit 14
2, and a write prohibited area setting circuit 143. The debugging device 100 also includes an access detection circuit 151, an access error signal generation circuit 152, and an access prohibition circuit 151 to detect an error when accessing a memory space that is prohibited to access, that is, an access error. A region setting circuit 153 is provided. Further, the debugging device 100 includes a memory selection detection circuit 161, a replacement signal generation circuit 162, a replacement area setting circuit 163, and an inverter 164 for switching between the memory 220 and the replacement memory 120.

The operation of this debugging device 100 is as follows. First, the operator sets in the write prohibited area setting circuit 143 an address value to be set as a write prohibited area. For example, an address used as a work area by another program is designated as this write-prohibited area. Subsequently, the operator sets an address value to be set as an access-prohibited area in the access-prohibited area setting circuit 153. For example, an address of a memory space in which no memory device is actually prepared is designated as this access-prohibited area. Furthermore, the operator sets in the replacement area setting circuit 163 an address value at which the replacement memory 120 should be accessed. As described above, the address area to be used by copying from the memory 220 to the replacement memory 120 is designated as a replacement area.

After completing each address setting in this way,
Memory 2 by emulation CPU 110
20 or the program in the replacement memory 120 is executed. At this time, emulation
When an access command is output from the CPU 110 via the control bus c, the memory selection detection circuit 161 supplies the memory selection detection circuit 165 to the replacement signal generation circuit 162. Replacement signal generation circuit 162
receives this memory selection detection signal 165,
The address given from the emulation CPU 110 via the address bus a is compared with the address set in the replacement area setting circuit 163 to determine whether the address currently being accessed is in the replacement area. Then, a replacement signal 166 is generated which indicates "0" if it is a replacement area and "1" if it is not a replacement area. If it is a replacement area, the replacement signal 166 activates the replacement memory 120 through the inverter 164, and the replacement memory 120 is accessed. If it is not a replacement area, the replacement signal 166 is transferred to the data bus buffer 132.
is made active, and the memory 220 is accessed. In this way, memory switching is performed as set.

Further, when an access command is output from the emulation CPU 110 via the control bus c, the access detection circuit 151 provides an access detection signal 154 to the access error signal generation circuit 152. The access error signal generation circuit 152 is
When this access detection signal 154 is received, the address given from the emulation CPU 110 via the address bus a is compared with the address set in the access prohibited area setting circuit 153, and it is determined whether or not the address currently being accessed is prohibited from accessing. Access error signal 15 that determines and indicates the result
Generates 5. The operator can detect this access error signal 155 and recognize that an access error has occurred.

On the other hand, when a write command is output from the emulation CPU 110 via the control bus c, the write detection circuit 141 outputs the write detection signal 14.
4 is given to the write error signal generation circuit 142.
When the write error signal generation circuit 142 receives this write detection signal 144, the write error signal generation circuit 142 performs an emulation
It compares the address given from the CPU 110 via the address bus a with the address set in the write prohibited area setting circuit 143, determines whether or not the address to which writing is currently being performed is write prohibited, and indicates the result. A write error signal 145 is generated. The operator can read this write error signal 1
45 can be detected to recognize that a write error has occurred. This write error signal 145 is also applied to the control bus buffer 133 to prevent execution of the write command. Therefore, erroneous rewriting of the memory can be prevented.

(Problems to be Solved by the Invention) However, the conventional debugging apparatus has the problem that the circuit configuration is complicated and the operation by the operator is complicated. That is, as shown in Figure 2,
Since the means for detecting a write error, the means for detecting an access error, and the means for performing memory selection are provided independently, the operator must make settings for each means separately. Also, in terms of circuit configuration,
Since each signal generation circuit 142, 152, 162 must be provided with an independent comparator,
It was getting very complicated. In order to deal with particularly detailed address settings, the comparator must be constructed from a huge number of logic elements. Furthermore, as the size of the memory space increases, the number of logic elements forming the comparator also increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a debugging device that has a simple circuit configuration and is easy to operate by an operator.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a debugging device including: an emulation CPU for debugging a program; a usage classification information storage circuit that stores information indicating usage classification of memory space used by the program; An address setting circuit that generates an address for accessing the usage classification information storage circuit, and an emulation
An address switching circuit that selects either the address generated by the CPU or the address generated by the address setting circuit and gives it to the usage classification information storage circuit for access, and the usage classification information storage circuit is generated by the address setting circuit. a data setting circuit that generates data to be written to the accessed address when accessed by the accessed address;
Emulation CPU of usage classification information storage circuit
A processing circuit that performs the processing necessary for debugging based on the data read from the accessed address when accessed by the address generated by the address is provided, simplifying the circuit configuration and facilitating operation. It is something.

(Function) In the debugging device according to the present invention, the usage classification information regarding the memory space of the program to be debugged can be stored all at once in the storage circuit, and the usage classification information can be read by accessing this storage circuit. Therefore, there is no need to provide a number of comparators for verifying addresses as in conventional devices, and the circuit configuration can be simplified and operation can be facilitated.

(Example) The present invention will be described below based on an illustrated example. FIG. 1 is a block diagram of a debugging device according to an embodiment of the present invention. Here, the elements on the right side of the dash-dotted line are the components of this debugging device 300, and the ones on the left side are the components of the device 200 that is the object of the debugging device. The device 200 has a CPU 210 and a memory 220, which are connected by an address bus A, a data bus D, and a control bus C. However, when debugging, the CPU210
is removed, and a debugging device 300 is connected in its place. FIG. 1 shows the state during debugging.

This debugging device 300 is an emulation
It has a CPU 310 and a replacement memory 320, which are connected by an address bus a, a data bus d, and a control bus c. Further, the address bus a is connected to the address bus A via the address bus buffer 331, the data bus d is connected to the data bus D via the data bus buffer 332, and the control bus c is connected to the control bus buffer 333.
The emulation CPU 310 is connected to the control bus C via the
Both memory 220 and replacement memory 320 can be accessed. The replacement memory 320 is
Since it is composed of RAM, the memory 220
Even if it is a ROM, its contents can be rewritten by copying it to the replacement memory 320 via the emulation CPU 310.

This debugging device 300 includes a usage classification information storage circuit 340 that stores information indicating the usage classification of the memory space used by the program to be debugged.
and an address setting circuit 341 that generates an address for accessing this usage classification information storage circuit 340, and selecting either the address generated by the emulation CPU 310 or the address generated by the address setting circuit 341. An address switching circuit 342 that is applied to the usage classification information storage circuit 340 to access it, and an address switching circuit 342 that inputs data to be written to the accessed address when the usage classification information storage circuit 340 is accessed by an address generated by the address setting circuit 341. A data setting circuit 343 for generating data is provided. Furthermore, this debugging device 300
An operation detection circuit 351 receives a command output from the CPU 310 via the control bus c and performs predetermined operation detection, and a usage classification information storage circuit 34
0 and a detection signal from the motion detection circuit 351.

The operation of this debugging device 300 is as follows. First, the operator uses the address switching signal 34.
4, the address switching circuit 342 selects the address from the address setting circuit 341 and performs switching so as to apply it to the usage classification information storage circuit 340. If such switching is performed, since the usage classification information storage circuit 340 is composed of RAM, the operator can set the address in the usage classification information storage circuit 340 specified by the address setting circuit 341 using the data setting circuit 343. Data can be written. Usage classification information storage circuit 340
The address space of the device 20 to be debugged is
It is mapped to address space 0. When making the most detailed correspondence between addresses, it is sufficient to make a one-to-one correspondence. That is, memory 220
The classification information storage circuit 34 uses exactly the same storage capacity as
It is secured within 0. If you want to reduce the storage capacity of the usage classification information storage circuit 340,
The correspondence relationship may be 16 to 1, 256 to 1, etc., and only the upper addresses may have a 1 to 1 correspondence. now,
Here, for convenience of explanation, we will consider a case where the two have a complete one-to-one correspondence. Therefore, any 1-byte address in memory 220 corresponds to a 1-byte address in usage classification information storage circuit 340. The operator stores usage classification information indicating the usage classification of the address space of the memory 220 in the usage classification information storage circuit 340. In this embodiment, the usage classification information includes information indicating whether the address is write-prohibited, information indicating whether the address is access-prohibited, and memory allocated to the replacement memory 320 during emulation. Is it space or memory 220?
It consists of three pieces of information: information indicating whether the memory space is allocated to Each of these pieces of information can be expressed with 1 bit, so a total of 3 bits of memory is sufficient. However, since access is generally performed in 1-byte units, it takes more time to store usage classification information for one address. 1 byte of memory is used. In this way, for example, in order to obtain the usage classification information for address x in the memory 220, it is sufficient to read the data at address x in the usage classification information storage circuit 340. Note that in order to set such usage classification information, the operator does not need to set it for each address; for example, addresses 1000 to 2000 are allocated to write-protected, accessible, and replacement memory 320. Three pieces of information can be set all at once across a certain memory area, such as a memory area. Therefore, the operator's effort is reduced compared to conventional devices.

After completing the setting of usage classification information for all addresses as described above, the emulation
A program in memory 220 or replacement memory 320 is executed by CPU 310. At this time, the operator uses the address switching signal 344 to switch the address switching circuit 342 so that it selects the address from the emulation CPU 310 and applies it to the usage classification information storage circuit 340. Therefore, when an address is output from the emulation CPU 310 via the address bus a, this address is always output to the address switching circuit 34.
2, and is applied to the usage classification information storage circuit 340. As mentioned above, since the usage classification information storage circuit 340 is constituted by a RAM, 1 byte of data stored at a given address, ie, usage classification information, is read out.

Of this 1-byte read data, valid data includes the write prohibition signal 353 indicating whether or not writing is prohibited, the access prohibition signal 354 indicating whether access is prohibited, and the memory replacement signal 355 indicating whether or not memory replacement is to be performed. There are only 3 bits. Of these, write prohibition signal 353 and access prohibition signal 354 are applied to operation comparison circuit 352 . Further, the memory replacement signal 355 is applied to the data bus buffer 332 and is also applied to the replacement memory 320 via an inverter 356. If the address currently being accessed is a replacement area, the replacement signal 355 becomes "0", this replacement signal 355 activates the replacement memory 320 through the inverter 356, and
0 is accessed. If it is not a replacement area, the replacement signal 355 becomes "1",
Data bus buffer 332 is activated and memory 220 is accessed. In this way, memory switching is performed as set.

On the other hand, when an access command is output from the emulation CPU 310 via the control bus c, the operation detection circuit 351 outputs an access detection signal 3.
57 is applied to the operation comparison circuit 352. Further, if this access command is a write command, the operation detection circuit 351 provides a write detection signal 358 to the operation comparison circuit 352. Operation comparison circuit 352
generates an access error signal 359 when receiving the access prohibition signal 354 and the access detection signal 357 at the same time, that is, when the address currently being accessed is prohibited from access. The operator can detect this access error signal 359 and recognize that an access error has occurred. Further, the operation comparison circuit 352 generates a write error signal 360 when receiving the write prohibition signal 353 and the write detection signal 358 at the same time, that is, when the address to which writing is currently being performed is write prohibited. . The operator can detect the write error signal 360 and recognize that a write error has occurred. The write error signal 360 is also applied to the control bus buffer 333 to prevent execution of the write command. Therefore, erroneous rewriting of the memory can be prevented.

As described above, the debugging device 300 according to the present invention
It will be appreciated that the debugging device 100 has the same functionality as the conventional debugging device 100. However, its circuit configuration is extremely simple. That is, all of the various usage classification information is collectively stored in the usage classification information storage circuit 340 consisting of RAM, and this information is read by accessing this RAM, so it is not necessary to check addresses as in the conventional device. There is no need for a comparison circuit for this purpose. Although a comparator is used in the operation comparison circuit 352, it does not compare addresses but only compares data of a few bits, and can be realized by a very simple logic circuit.

〔Effect of the invention〕

As described above, according to the present invention, in the debugging device, the usage classification information regarding the memory space of the program to be debugged is stored all at once in the storage circuit, and the usage classification information is read out by accessing this storage circuit. As a result, the circuit configuration can be simplified and the operation can be facilitated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a debugging device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional debugging device. 100... Conventional debugging device, 110... Emulation CPU, 120... Replacement memory,
131...Address bus buffer, 132...Data bus buffer, 133...Control bus buffer, 141...Write detection circuit, 142...
...Write error signal generation circuit, 143...Write prohibited area setting circuit, 144...Write detection signal,
145...Write error signal, 151...Access detection circuit, 152...Access error signal generation circuit, 153...Access prohibited area setting circuit, 1
54...Access detection signal, 155...Access error signal, 161...Memory selection detection circuit, 1
62...Replacement signal generation circuit, 163...Replacement area setting circuit, 164...Inverter, 165...Memory selection detection signal, 166...Replacement signal, 200
...The device to be debugged, 210...
CPU, 220...Memory, 300...Debug device according to the present invention, 310...Emulation
CPU, 320...Replacement memory, 331...Address bus buffer, 332...Data bus buffer, 333...Control bus buffer, 3
40...Use classification information storage circuit, 341...Address setting circuit, 342...Address switching circuit, 3
43...Data setting circuit, 344...Address switching signal, 351...Operation detection circuit, 352...Operation comparison circuit, 353...Write prohibition signal, 354
... Access prohibition signal, 355 ... Memory replacement signal, 356 ... Inverter, 357 ... Access detection signal, 358 ... Write detection signal, 359 ...
...Access error signal, 360...Write error signal, A, a...Address bus, C, c...Control bus, D, d...Data bus.

Claims (1)

[Claims] 1. An emulation CPU for debugging a program, a usage classification information storage circuit for storing information indicating usage classification of memory space used by the program, and accessing the usage classification information storage circuit. an address setting circuit that generates an address for the purpose of the application, and an address that selects either the address generated by the emulation CPU or the address generated by the address setting circuit and supplies it to the usage classification information storage circuit for access. a switching circuit; a data setting circuit that generates data to be written to the accessed address when the usage classification information storage circuit is accessed by the address generated by the address setting circuit; and the usage classification information storage circuit. a processing circuit that performs processing necessary for debugging based on data read from the accessed address when accessed by the address generated by the emulation CPU. 2. The debugging device according to claim 1, wherein the information indicating the usage classification of the memory spaces includes information indicating whether or not each memory space is write-protected. 3. When the processing circuit reads information indicating write prohibition from the usage classification information storage circuit, it generates an error signal to indicate a write error and also performs an operation to prevent the emulation CPU from performing a write operation. A debugging device according to claim 2. 4. The debugging device according to claim 1, wherein the information indicating the usage classification of memory spaces includes information indicating whether access to each memory space is prohibited. 5. Claim 4, characterized in that the processing circuit performs an operation of generating an error signal for displaying an access error when the processing circuit reads information indicating access prohibition from the usage classification information storage circuit.
Debugging device as described in section. 6. The debugging device according to claim 1, further comprising a replacement memory for debugging. 7 For each memory space, determine whether the information indicating the usage classification of memory space is the memory space allocated to the replacement memory or the memory space allocated to the memory in the device that is the target of debugging. 7. The debugging device according to claim 6, further comprising memory selection information indicating the debugging device. 8. The processing circuit performs an operation of switching the memory to be accessed by the emulation CPU to the replacement memory or the memory in the device to be debugged, based on the memory selection information read from the usage classification information storage circuit. A debugging device according to claim 7.