JPH0428307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a graphic display device using the bitmap prefresh method, and particularly to an image display device capable of speeding up the display of characters such as Chinese characters.

[Background of the invention]

The code refresh method was often used for character display devices such as word processors, but the demand for graph and graphic displays made it necessary to use graphic displays. In order to perform a graphic display, it is preferable to use a bitmap refresh method in which a refresh memory (bitmap type graphics memory) is provided for each display pixel. However, although this BITMATSU pre-refresh method is suitable for displaying graphs and figures, it is also necessary to develop the character pattern on the graphics memory when displaying characters. The disadvantage is that the display processing speed is slower in comparison. In particular, character generators conventionally used for generating character patterns have character patterns stored therein for code refresh, and are not suitable for display devices for bitmap pre-refresh.

This problem is the same in personal computers with BITMATSU pre-refresh type display devices, and in order to improve this shortcoming, a barrel shifter and a BIT mask controller are installed in the CRT interface section to improve display speed. . However, in the conventional device, the circuit scale has become large in order to realize both in a circuit.
A BITSUTOMATSU prefresh type personal computer is disclosed in "PC-100 Technical Manual" regarding the general-purpose personal computer PC-100 manufactured by Nippon Denki Co., Ltd.

[Purpose of the invention]

The access time from the present invention is determined, and screen refresh is performed so that the video signal to be provided to the CRT monitor 23 is not interrupted. When there is an access from the CPU 111, control is performed to make the access by the CPU 111 wait with a "Not Ready" signal until the time reserved for the CPU 111.

Figure 14 shows a timing chart when there is an access from the CPU 111.
When there is no access from the CPU 111 during the CPU access time, the CAS signal is not issued, and the address and RAS signal to the graphic memory 117 are not issued as a function of DRAM. The object of the present invention is to realize an image display device that can utilize the high-speed processing function of a CPU with a simple circuit configuration and can also achieve high-speed display processing in character display processing.

[Summary of the invention]

In order to achieve this objective, the present invention
writing means for accessing a character generator and a bit map type refresh memory to write a predetermined image pattern to a specified address under the control of the character generator; In the image display device, the character generator divides the dot data of the character pattern dot matrix in units of bytes in the scanning direction of the scanning lines, and divides the dot data of the character pattern dot matrix into byte units in the scanning direction of the scanning lines. The character pattern of the character generator is provided by providing a memory in which the memory is stored consecutively in the direction order, and the writing means is provided with means for switching the order of the refresh memory access addresses by the CPU to the order of the scanning direction of the scanning line and the order of the alignment direction. Dot matrix data can be transferred and written to refresh memory at high speed under the control of the CPU.
Another feature is that refresh memory control such as scrolling of the display screen can be processed at high speed.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

As shown in FIG.
0, consists of a keyboard 21 as an input section, a printer 22 as a printing section, and a CRT monitor 23 as a display section, and these main body 20, printer 22, keyboard 21, and CRT monitor 23 are arranged as shown in , respectively, cable 2
01 to 203, control signals or information signals are exchanged. In addition, in FIG. 2, 24 is a flexible disk drive device (hereinafter referred to as FDD), which is integrally assembled to the main body 20.

Inside the main body 20, there is a control section 2 within the broken line in the control circuit shown in the block diagram of FIG.
5 is installed. That is, the control section 25
A host CPU 251 consisting of a program storage type computer unit (hereinafter referred to as CPU), and a boot ROM 25 consisting of a non-volatile memory (hereinafter referred to as ROM) having a program executed when the power is turned on.
2. A memory that can be read and written at any time (hereinafter referred to as RAM) to store programs and information for executing the function of a word processor.
A program memory 253 consisting of a host CPU
Generates a screen display pattern according to the instructions of 251 and sends a video signal to the CRT monitor 23
A CRT display circuit 254 , a flexible disk control circuit (hereinafter referred to as FDC) 255 that controls the FDD 24 according to commands from the host CPU 251 , and sends signals for controlling the printer 22 and print signals to the printer 22 according to commands from the host CPU 251 a printer controller 256 that receives printer 22 status signals from the printer 22 and sends them to the host CPU 251; a key input controller that controls the keyboard 21 according to commands from the host CPU 251 and sends input signals from the keyboard 21 to the host CPU 251; 257, and said host
CPU251, boot ROM252, program memory 253, CRT display circuit 254, FDC255,
It is composed of an internal wiring path d that connects the printer controller 256 and the key input controller 257.

Here, the FDD 24 drives a flexible disk, which is a magnetic storage medium, and records information on the flexible disk and reads information from the flexible disk. An opening for the FDD 24 related to the storage section is provided substantially on the front surface of the main body 20.

Next, the overall operation of this word processor will be explained. When the power is turned on in the above configuration, the host CPU 251 loads the boot ROM 2.
52 program, a program for operating this device as a word processor with the data processing flow shown in FIG. 4 is installed on the FDD 24.
The word processor is transferred from the flexible disk set in the program memory 253 to the program memory 253, and then starts operating as a word processor in accordance with the program transferred to the program memory 253. Furthermore, at the same time, a program for the CPU 111 to operate as a CRT display circuit, which controls a CRT display circuit 254, which will be described later, is also transferred from the flexible disk stored in the FDD 24 to the memory 122, which will be described later. In the data processing flow shown in FIG. 4, the auxiliary function is a general term for a function that aggregates functions such as copying text data in a flexible disk to another flexible disk.

When input processing is selected by the work selection input, the host CPU 251 starts executing an input processing program having a data processing flow as shown in FIG. The document data being inputted is sent to the CRT display circuit 254 via the signal line a by sending commands and data according to the input processing program in the program memory 253 as shown in FIG.
The display circuit 254 creates an image pattern, converts it into a video signal, and provides it to the CRT monitor 23.
An image is displayed on the screen of a CRT monitor 23. Processing instructions associated with data input to the document data are performed according to data and function instructions input from the keyboard 21.

When only character display is to be performed on the CRT display circuit 254, the unit of data given by the host CPU 251 to the CRT display circuit 254 is data corresponding to one line of display characters on the screen according to the instructions of the program. be. In other words, the host CPU 251 sends one line of data with a new display character added to the end of the line through the signal line a in response to each character input from the keyboard 21.
It is sent to the CRT display circuit 254.

The operator inputs characters one by one, but the host CPU 251 and CRT display circuit 25
4 must display one line of data, so input processing within the host CPU 251,
Furthermore, the drawing process on the screen within the CRT display circuit 254 requires high-speed data processing in order to avoid waiting time for the operator.

From now on, by repeating this operation until you receive an instruction to end data input, the input data will be
This is what is displayed on the CRT monitor 23.

When an instruction to end data input is input from the keyboard 21, the host CPU 251 detects this, executes the end processing (ends the input processing shown in FIG. 5), returns to the flow shown in FIG. 4, and starts the next process. This is to prepare for the

The termination process in FIG. 5 is a process in which input data is written to a flexible disk and temporarily stored.

In the editing process shown in FIG. 4, the keyboard 21
The screen is rewritten according to the function key data input from. Even in the case of other processing, work instructions, progress, etc. are displayed on the CRT monitor 23.

Next, the CRT display circuit 254 will be explained.

FIG. 1 shows a block diagram of one embodiment of CRT display circuit 254. Shown in Figure 1
The CRT display circuit 254 is connected to the CPU 111 (for example, Intel's 8086 or
8088 etc. are suitable. ), a clock generator 112 that supplies clocks and other signals necessary for the CPU 111, and a CRT that generates address signals for sequentially reading out the contents of the graphics memory 117 and a synchronization signal that controls the CRT monitor 23.
A controller (hereinafter referred to as CRTC) 113, a shift register that converts parallel data from the graphics memory 117 into a serial video signal,
Sync signal from CRTC113 to CRT monitor 2
3, a CRT monitor 23 that receives video signals and synchronization signals and displays images, and controls the access signals from the CPU 111 and the CRTC 113 in a time-sharing manner to display graphics. A memory peripheral control circuit 116 sends out data from the memory by supplying it to the memory 117, and a 128 kilobyte dynamic RAM (64 kilobits x 16 bit word, however
It is accessed by the CPU in 8-bit byte units. ), a host CPU 251 shown in FIG. 2 which is located above the CRT display circuit 254, an interrupt controller 118 that gives an interrupt signal to the CPU 111 and branches the program in response to an external event, and a shift controller. Control register 1 that holds control information such as read and write control bits and address switching selection signals
19. Collision prevention control circuit 120 configured to multiplex control access from CPU 111 to memory 122 and character generator (hereinafter referred to as CG) 123, and access signals from host CPU 251 in FIG. 3, to memory 122. Controls multiplexed address signal generation and refresh operation of
DRAM controller 121, dynamic RAM 122 (hereinafter referred to as
It is called DRAM. ), kanji, kana, alphanumeric characters, etc., in a dot matrix pattern.

Host CPU 251 and CRT display circuit 2 in Figure 3
54 is connected by a control signal and data signal line a, and the CPU 111 of the CRT display circuit 254 and the CRTC
113, memory peripheral control circuit 116, interrupt controller 118, control register 119, and collision prevention control circuit 120 are interconnected by CPU bus b, which multiplexes access signals from signal lines a and b to There is a memory bus c that supplies the controller 121 and CG 123.

Next, details of the CG 123 are shown in FIG. CG1
23 is a CGROM 231 consisting of a plurality of ROMs, and serves as a bus driver for supplying 1-byte data of the CGROM 231 designated by an address signal from the memory internal bus to the data line of the memory bus c. A bus driver 232 that supplies data lines;
A bus driver 2 that replaces the data in the CGROM 231 in 4-bit units and supplies it to the memory bus c.
It consists of 33 etc. Here, signal line e
is set in the control register 119 by the CPU 111 and transmits the signal given from the control register 119.

Furthermore, of the memory peripheral control circuit 116 and the graphic memory 117, circuit portions related to write control are shown in FIG.

A control signal to the graphics memory 117 is given from a time division control signal generation circuit 161.
Address selector 16 that switches between the address signal when reading from the CRTC 113 and the address signal when accessing from the CPU 111
3. Shift register 141 for converting parallel data read by access from CRTC 113 into a serial video signal, bus driver 162 for exchanging data with CPU bus b when accessed from CPU 111, graphics memory 117 A data latch 191 is part of the control register 119 that controls the masking of the write enable signal WE that controls bit-by-bit writing.
and data latch 1 when writing from CPU111.
WE driver 164 and CPU which give write enable signal WE of 91 to graphics memory 117;
111 and latched in the control register 119, the CPU
An address switching circuit 165 for switching the configuration of addresses from 111, etc. is connected to the graphic memory 1.
It is connected to the surrounding area of 17.

Next, the configuration of the CGROM 231 will be explained in detail using figures. Figure 8 shows a character generator with a 24 x 24 bit configuration that has been commercially available.
ROM (for example, sold by Hitachi)
This includes HN613256PA10~PA18. ) is shown in the ROM using the kanji character ``Dou'' as an example. In this ROM, one character is divided into 8x to match the code refresh display circuit system.
Divided into 8-bit patterns for a total of 9 ROMs
This memorizes the dot pattern of a single character. This has the advantage of requiring a minimum hardware configuration in order to obtain CG scanning line data from character numbers and scanning line addresses in the code refresh method.
In the bit map display method in which the CG 123 is accessed by 11 to read the data and the display pattern is written to the graphic memory 117, when the CPU 111 reads the adjacent 8 x 8 bit pattern, it is stored in the next ROM. Since the addresses of the patterns are located in spaces 32 kilobytes apart, the addressing register must be operated each time, which is not suitable for CG read processing. Therefore,
In this embodiment, as shown in Figure 9, the CGROM configuration suitable for CPU control is an aligned type in which a 24 x 24 bit pattern is divided into 8 x 24 bits in bytes and stored consecutively in one ROM. It composes CG. The addresses are shown in hexadecimal when all ROMs are arranged in order.

Next, the address structure of the graphics memory 117 will be explained using a diagram.

A video signal is composed of a series of image bits in units of scanning lines. That is, reading by the CRTC 113 for refreshing the screen is performed in units of 16 bits from the beginning of the screen.
It is serially converted starting from the MSB, and after the LSB, the following
A series of 16-bit MSBs.

FIG. 10 shows the address structure of a conventional graphic memory. Area 117a is CRT monitor 2
This is the range displayed on screen 3. A total of 71,680 bytes of the graphics memory 117 can be displayed on the screen of the CRT monitor 23, with 1024 horizontal dots (128 bytes) and 560 vertical scanning lines. Of these, 984 dots horizontally and 560 scanning lines vertically are used to form a kanji display screen of 41 characters x 20 lines, with each character consisting of 24 x 28 dots. Of the 41 characters x 20 lines of Kanji display screen, 17 lines are used as a text area, and the rest is used as a management information area to display management information and information being processed.

On the other hand, for the CPU, when handling a 24 x 24 bit character pattern, the depth is 3 bytes in the scanning direction of the scanning lines, and the depth is 24 bytes in the direction of the order of the scanning lines. For the Intel 8086 and 8088 used as the CPU 111, string instructions are provided for repeated processing of consecutive addresses. That is, data transfer of the number of bytes specified from the source address specified in a predetermined register to the destination address specified in a predetermined register is performed in the minimum number of instruction steps and in the shortest processing time. In order to obtain the maximum effect in this processing method, it is effective to increase the number of bytes transferred at one time, and for this purpose, it is necessary that the byte addresses are continuous. Focusing on this point,
Graphic memory 117 seen from CPU 111
The address of CG is stored in the graphics memory 117.
When character pattern data is transferred from 123 and character display processing is performed, the scanning lines should be arranged in the forward direction. On the other hand, when moving a large block in the graphics memory 117, such as during screen scroll processing, the address structure of the graphics memory 117 should be aligned in the same direction as the CRT access (that is, the scanning direction of the scanning lines). It is.

The address configuration of the graphics memory 117 in this embodiment is such that two types of access methods can be selected according to instructions from the CPU 111: the forward direction of the scan lines and the scan direction of the scan lines. It is shown in Figure 11.

In order to realize the addresses shown in FIG. 11, the correspondence between the two groups of inputs of CRT addresses and CPU addresses to the address selector 163 shown in FIG.
It looks like the picture. Among them, bank switching in memory address is a 16-bit configuration.
These are signals for selecting each 8-bit block in the DRAM, and RA0-7 indicate the RAS address of the DRAM, and CA0-7 indicate the CAS address.

As described above, the address structure of the graphic memory 117 is arranged as CPU address selection 1.
Being accessible in the same way as the CGROM 231 is suitable for character display processing by the CPU 111, and in the case of CPU address selection 2, the CPU 11
This configuration is also suitable for scrolling processing, which is processing for moving blocks of the contents of the graphics memory 117 according to the method.

Next, the operation will be explained. The area occupied by a single kanji character in bitmap memory is a full-width character.
24 (horizontal) x 28 (vertical) bits, 12 x 28 bits for half-width characters. In the vertical direction, 24 bits are allocated for the character pattern section, and 4 bits are allocated for the interline space, underline, and horizontal ruled line area. Vertical ruled lines are overlaid on the 24-bit area of the character pattern.

Instructions regarding screen display from the host CPU 251 are sent to the memory 12 through the signal line a shown in FIG.
It is placed in the information transmission area of 2. Once that information is set, host CPU 251 provides an activation signal to interrupt controller 118. CPU111
The processing program is started by an interrupt and performs screen control, data writing, etc. Screen controls include erasing the entire screen and scrolling the screen. Writing data, whether it is displaying a new screen or overwriting new data on an old screen,
Even when a new line is added due to scrolling, data for each line is transferred from the host CPU 251 to the CPU 111 as a unit.

One line of display data is prepared in the information transmission area of the memory 122, and when data writing is given as a command and activated by the interrupt controller 118, the CRT display circuit stored in the memory 122 is controlled. The program to be executed is activated and writing is given as a command to the information transmission area of the memory 122, so that the CPU 111 executes the program having the flow shown in FIG.

In this flow, first, the processing step
In step 1201, matrix values (X, Y) indicating the beginning of one line to be displayed are obtained from among the display control parameters accompanying the display data in the information transmission area of the memory 122;
The address in the graphics memory 117 is calculated. Next, in processing step 1202, one character is extracted from the character data of the display data according to the pointer indicating the character to be displayed, and the CG number is obtained.
Move to processing step 1203 and set the CG number to CGROM2.
Using the address of 31 and the address of CGROM 231 as factors, the process branches to one-character display subprogram processing step 1204, which will be described later. When the display of one character is completed, the process moves to processing step 1205, where the character pointer indicating the position of the character data to be displayed is advanced by one, and then the process moves to processing step 1206, where the display control accompanying the display data in the information transmission area of the memory 122 is performed. It is checked whether the display processing for the specified number of display characters in the parameter has been completed, and if it has not been completed, the process returns to processing step 1202 to move on to displaying the next character, and if it has been completed, the processing is terminated.

The graphics memory 117 must be accessed for writing by the CPU 111 in order to write a pattern to be displayed on the screen, and must also be read by the CRTC 113 to refresh the screen in order to illuminate the screen of the CRT monitor 23. In order to control the above operations as if they were being performed simultaneously, the memory peripheral control circuit 11
6 is for screen refresh as shown in Figure 14.
Read time from CRTC113 and CPU111
It becomes effective.

Next, regarding the operation during use, the CPU 1 which forms the screen pattern on the graphics memory 117
The processing operations starting from 11 and the operation of sequentially reading out the completed patterns from the graphics memory and displaying them on the CRT monitor 23 will be explained separately.

(1) Processing from the CPU The display information is displayed in bits in the graphics memory 1.
"1" (bright spot) or "0" (dark spot) is written in 17 and stored. Characters are displayed on the screen by writing a specified character pattern from the CG 123 to the byte address of the graphics memory 117 to be stored using a string command.

Regarding the one-character display subprogram processing for newly displaying one half-width character A (12×24 dots) as shown in FIG. 15, the processing time in the conventional circuit and the circuit according to this embodiment will be compared. In addition,
At this time, CPU111 uses a 15MHz clock.
It is assumed that the calculation is performed assuming that the program operates without Wait and that instruction fetching is performed during internal processing.

FIG. 16 is a flowchart of a write process using a conventional circuit, in which the basic process of drawing a pattern of a half-width character A in the graphics memory 117 takes about 1.12 mS.
It takes.

FIG. 17 shows the flow of write processing according to this embodiment. For the display of one half-width character shown in FIG. 15, CPU address selection 1 is specified in processing step 1600, and CGROM 2
A shift read from 31 is set in the control register 119 to select the bus driver 233, and a mask is set in the control register 119 to prevent writing of the upper 4 bits in the next processing step 1602. Then, in processing step 1603, 24-byte pattern data is transferred from the CGROM 231 to the graphics memory 117. However, graphic memory 1
17, a 24×4 bit pattern is drawn. Next, in processing step 1604, the area between the lines is cleared, and then 4 bits on the right side are drawn. For this purpose, the CG address is recovered in processing step 1605, the mask is changed in processing step 1606, the graphics memory address is updated in processing step 1607, and 24×4 bit drawing processing step 1608 is performed. Finally processing steps 1609-1613
As in the beginning, the 4 bits on the left side of the CGROM are transferred 24 times and the process ends.

In the processing in the circuit of this embodiment, the CGROM23
The transfer of the pattern from 1 to the graphics memory 117 is performed by a string instruction under the configuration of the CPU address selection (1) shown in FIG. In addition, since pattern transfer, which accounts for most of the processing, is based on string instructions, the number of required clocks is reduced, and the same drawing requires only about 0.366 mS.

Next, the scrolling operation will be explained. 18th
The figure shows a flow for performing a scrolling operation using address selection (1) in this embodiment without address switching. In this embodiment, scrolling is performed according to the flow shown in FIG. 19, and in processing step 1701, address selection (2) is set, and in processing steps 1702 to 1704, parameters for string operation are set. That is, the address address of the graphic memory 117 corresponding to the second line of text is set as the source, the address address of the graphic memory 117 of the first line of text is set as the destination, and the program moves from the second line of text to the last 17 lines of text. Graphic memory up to the eyes 11
Let the number of bytes of 7 be the number of transferred bytes. In processing step 1705, the specified transfer string command is
57344 bytes are transferred. Thereafter, in processing step 1706, one line of display data to be newly displayed on the 18th line is drawn.

Even without address switching, string instructions are used to speed up processing, but if address switching is further implemented, as shown in Figure 19, it is possible to complete the process with a single transfer of string instructions, without switching. Compared to the flow shown in Figure 18, the preprocessing before executing the string instruction is
This means that it only takes a few times, resulting in even faster operation.

In the above explanation, we used an example of upward scrolling in which the screen content appears to rise from the bottom to the top, but even in the opposite case of downward scrolling, the operation is similar, only the source address and destination address are different. becomes.

(2) Refresh operation In the order of CRT addresses shown in parentheses in Figure 11, according to the synchronization timing of CRT monitor control.
CRTC 113 generates a read signal to graphics memory 117. The CRTC 113 generates addresses in the order of screen positions and provides read signals to the time division control signal generation circuit 161. Time division control signal generation circuit 161 controls address selector 163 during CRTC read time to provide an address to graphic memory 117. The data read from the graphics memory 117 during the CRTC read time is given to the shift register 141, then converted from parallel to serial by the video clock, and sent to the CRT via the drive circuit in the peripheral control circuit 114 as a video signal. The signal is given to the monitor 23.

[Modification of the embodiment]

The address structure of the vertically arranged graphics memory is also effective in image display devices that use a DMA controller that performs DMA transfer for data transfer from memory to memory.
The same effect can be obtained even if the command does not have a string instruction.

Intel's 8086 and 8088 are suitable as CPUs, but it is obvious that the same effect can be obtained by using other CPUs with the same functionality as the product in question.

〔Effect of the invention〕

As described above, according to the present invention, in an image display device using a bit map display method, it is possible to make full use of the characteristics of the CPU to quickly write characters such as kanji to a graphic memory, and to write characters such as kanji at high speed. It is possible to provide a device that is capable of scroll processing, graphical display, and fast character display. In particular, in single character drawing processing, compared to the processing example of the circuit of the conventional device, the circuit of the present invention can perform high-speed processing using string instructions, and it can be exemplified that the speed can be increased.

The time required to rewrite screen memory is shortened,
In addition, by speeding up scrolling, which is often used during document editing, the response time for word processing processing performed interactively by the operator is shortened, allowing for faster kanji input and screen rewriting. Improves operability in all editing processes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image display device according to the present invention, FIG. 2 is an external view of a word processor using the image display device of the present invention, FIG. 3 is a block diagram of a circuit section of the word processor, and FIG. Figure 4 is a flowchart of the word processor operation program, Figure 5 is a flowchart of the word processor operation program related to input processing, Figure 6 is a detailed block diagram of CG, and Figure 7 is a circuit related to WE control. 8 is a diagram showing the pattern configuration of a conventional CGROM, and FIG. 9 is a block diagram of the conventional CGROM.
Figure 10 shows the address structure of a conventional graphics memory. Figure 11 shows the address structure of the graphics memory in this embodiment. Figure 12 shows the CRT address and CPU address.
A diagram showing the relationship between addresses and memory addresses. FIG. 13 is a flowchart of a one-line display program executed by the CPU for this embodiment to operate as an image display device. FIG. FIG. 15 is a diagram showing a graphics memory displaying the half-width character A. FIG. 16 is a flowchart of writing processing to the graphics memory in a conventional device. The figure is a flowchart of the write process in this embodiment, FIG. 18 is a flowchart of conventional scrolling, and FIG. 19 is a flowchart of scrolling in this embodiment. 23...CRT monitor, 111...CPU, 1
13...CRT controller (CRTC), 116...
...Memory peripheral control circuit, 117...Graphic memory, 123...Character generator (CG), 165...Address switching circuit, 231
...CGROM.

Claims (1)

[Claims] 1 A writing means for accessing a character generator and a bit map type refresh memory to write a predetermined image pattern to a designated address under the control of a CPU; In the image display device, the character generator divides the dot data of the character pattern dot matrix into byte units in the scanning direction of the scanning line, and divides the dot data of the character pattern dot matrix into units of bytes in the scanning direction of the scanning line. 1. An image display device comprising a memory that is stored in a continuous manner in an arrangement direction, and wherein the writing means includes means for switching the order of the refresh memory access addresses by a CPU to a forward direction in which the addresses are arranged in the scanning direction of a scanning line.