JPH0693178B2 - Display device - Google Patents

Description

The present invention relates to a display device, and more particularly to a bitmap type display device.

[Prior Art] When a screen memory data is partially changed in a conventional device, a microcomputer (hereinafter referred to as a CPU) reads (1) data already written in a memory as a CP.
Take in U.

(2) Shift the character pattern to be written.

(3) The non-rewriting portion of the original data in the memory is masked and taken out, the write bit of the shifted character pattern is taken out, and the logical sum of the two is taken.

(4) The processing step of writing the completed data to the memory of the same address was taken.

Further, the bit processing of the CPU is slow, and in particular, in the case of shifting, a command of multiple bit shift is a system in which command steps of one bit shift are repeated multiple times.

On the other hand, as described in Japanese Patent Laid-Open No. 59-90156, a method has been proposed in which a shift register and a counter are used to realize rewriting in bit units by an external circuit. Even if the write operation ends, the shift register ends the operation, and it takes time until the data is actually written in the memory, so it is not possible to instruct continuous writing, but it is suitable for writing 1 bit, but writing a large amount of data Was not suitable for.

That is, in the conventional device, for example, the address configuration of the screen memory is as shown in FIG. In this case, for example, when handling a 24 × 24 bit character pattern, the depth is 3 bytes in the raster scan direction and 24 bytes in the raster order direction. The CPU has a string instruction for normal sequential address repetition processing.
That is, the transfer of the specified number of bytes from the source address specified in the predetermined register to the destination address is performed in the minimum instruction step and the minimum processing time.
Therefore, to obtain the maximum effect in this processing method, 1
It is effective to take a large number of bytes transferred at one time. Therefore, paying attention to this point, as shown in FIG. 7, the address configuration of the screen memory arranged in the raster forward direction is used.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, since the address configuration of the memory is horizontally arranged or vertically arranged,
The address configuration of the screen memory could not be arbitrarily selected, which was not enough to speed up the CPU.

An object of the present invention is to provide a display device capable of accessing a memory in which pixel information is stored with an address configuration of either a horizontally arranged address or a vertically arranged address.

[Means for solving problems]

The purpose is to set a pixel information storage area for storing pixel information to 2
The addresses of one area are arranged horizontally and the addresses of the other area are arranged vertically, and are stored in the pixel information storage area by using one of the pixel information storage areas. It is achieved by providing pixel information access means for accessing the pixel information, and display means for converting the pixel information accessed by the pixel information access means into a video signal and displaying an image on the screen.

[Action]

When the pixel information stored in the memory means is accessed, the pixel information storage area corresponding to the horizontally or vertically arranged addresses is used for access, so that the display speed is increased.

〔Example〕

Hereinafter, an example in which the present invention is applied to a word processor will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the word processor. 201 is a CPU that controls the entire device, and 202 is a non-volatile memory (hereinafter referred to as ROM
Boot ROM having a program to be executed when the power is turned on, 203 is an interrupt controller for giving an interrupt signal to the CPU 201 to branch the program, and 204 is the CPU 20.
Keyboard 205 is controlled according to the command of 1, and keyboard 20
The key input controller that sends the input signal from the CPU 5 to the CPU 201, 206 sends a signal for controlling the printer 207 and a print signal to the printer 207 according to the command of the CPU 201, and receives the status signal of the printer 207 from the printer 207, Printer controller to send to the
Flexible disk controller (F
DC), 210 is a main memory including a memory (hereinafter referred to as RAM) that can be read and written as needed to store programs and information, and 211 is a CRT display device that sends a video signal to a CRT monitor 212.

Next, the overall operation of the word processor will be described. That is, in the above-mentioned configuration, when the power is turned on, this apparatus executes a program for operating as a word processor stored in the flexible disk of the FDD 209 according to the program of the boot ROM 202 in the main memory 210.
Then, the operation as a word processor is started in accordance with the program transferred to the main memory 210. The document input process is performed according to the input process program in the main memory 210. In other words, the CRT controller 211 creates a screen pattern by sending a command or data to the CRT controller 211 by the input processing program, converts it into a video signal and gives it to the CRT monitor 212, and displays it on the screen of the CRT monitor 212. To form. The command of the process associated with the data input is given in accordance with the data or the function instruction input from the keyboard 205. After that, this operation is repeated until there is an instruction to end the data input. When the data input is completed, the end instruction is the keyboard 205.
When further input, the CPU 201 detects this, executes the ending process, and prepares for the next process.

FIG. 1 shows a block diagram of a display device according to the present invention. 101 is a graphic display controller (hereinafter referred to as GDC) that generates an address signal for sequentially reading the contents of the screen memory 108, and also generates a synchronization signal for controlling the CRT monitor 212, and 103 is a CPU 20 for the screen memory 108.
A screen memory control circuit that supports the drawing process of the CPU 201 by synchronizing the write signal from 1, 102 is a control signal generation circuit that generates a timing signal for the circuits around the screen memory, and 108 is one of the double-sided image bits. It is a screen memory that exists as a bitmap corresponding to bits, and is composed of dynamic RAM. Reference numeral 109 is a shift register for performing parallel-serial conversion on the data read from the screen memory 108, and 110 is a horizontal / vertical synchronization signal from the GDC 101.
The 09 is a synchronizing circuit for synchronizing with the video signal from the shift register, and 212 is a CRT monitor that receives the video signal and the synchronizing signal and displays a screen. Reference numeral 104 is a data selection multiplexer, 111 is a screen memory address selection multiplexer, and 107 is a refresh address selection multiplexer, both of which select and output a set of signals from the input signal lines. 105 is the screen memory 108
Is a buffer for the output of, and 106 is an address conversion circuit for converting the expanded address area into the memory area of the screen memory 108. For example, a method of performing address conversion by ROM can be considered.

Next, the operation mode of the screen memory 108 will be described with reference to FIG. The screen memory 108 operates by read modify write when the CPU 201 writes. That is, the data from the CPU 201 is the data latch 301.
Are stored once, processed by the parrel shifter 302, and input to the light controller 303. Screen memory 1
The contents of the designated address of 08 are read and given to the other input terminal of the write controller 303. According to the instruction stored in the operation register 305, the above two inputs are logically operated bit by bit and written to the designated address of the screen memory 108.

Next, the address configuration of the screen memory 108 will be described in detail with reference to the drawings. The video signal is configured in raster units as a series of video bits. That is, reading from the GDC 101 for refreshing the screen is in 16-bit units from the beginning of the screen, serially converted in order from the LSB, and the MSB is followed by the next 16-bit LSB.

This is because the arrangement of the above-mentioned address configurations can be arbitrarily selected, and the address area of the screen memory 108 as seen from the CPU is expanded to access the screen memory 108, thereby providing two address configurations. By selecting the address area of, the arrangement of address configurations can be arbitrarily selected. FIG. 4 shows the address structure.

In this case, the address area of the screen memory 108 is the 64-Kbyte area 1 (702) from the 0th address to the 65535th address, and the 64Kbyte area 2 (703) from the 65536th address to the 131071th address.
Is expanded so that the screen memory 108 can be accessed from either area. The address configuration as seen from the CPU is the same horizontal arrangement as the raster scan direction of address area 1 (702) from address 0 to address 65535.
Address area 2 (703) at address 071 is arranged vertically as in the raster forward direction. As a result, when a horizontal line is drawn on the screen memory 108, for example, from address 0 of area 1 (702) to 127
A string command may be issued to the address, and when drawing a vertical line, for example, from address 65536 to 6604 of area 2 (703).
A string command may be given to address 7. Of course, the address configuration in this case is such that addresses 0 to 65535 are arranged side by side and addresses 65536 to 131071 are arranged vertically, but the opposite is also possible.

The relationship between the CPU memory map 701 and the screen memory 108 is shown in FIG. In this case, the address area 702 from the CPU address 10000H (H indicates a hexadecimal number. The same applies hereinafter) has a laterally arranged address configuration, and the CPU addresses 20000H to 2H.
The address area 703 of FFFFH has a vertically arranged address configuration, and when the address area 703 is accessed, the multiplexer 111 is switched so as to access the screen memory 108 via the address conversion circuit 106. A method in which access conversion is performed by ROM is also conceivable.
Of course, the arrangement of the address configurations in this case may be opposite.

When the screen memory is divided into two and one is used as the screen memory area and the other is used as the data area, by accessing the horizontally aligned address areas in the raster scan direction as the data area. Since the data area can be used as a continuous address, and it is not necessary to separately provide a memory peripheral circuit for the screen memory area and the data memory area, the circuit configuration can be simplified.

Next, the operation of this circuit will be described with reference to FIG.

(1) Processing from CPU201 (screen creation). The display information is "1" (bright spot) or "0" in the screen memory 108 in bit units.
Displayed by writing (dark dot). Characters are displayed on the screen by writing the character pattern designated by the character generator to the byte address of the screen memory 108 to be displayed using a string instruction. By the way, since the width of the half-width character is 1.5 bytes, if even one half-width character is included in the sentence, the bit position of the character pattern in the screen memory 108 may be shifted by 4 bits and the situation may not match. At this time, in the configuration without the screen memory control circuit, bit processing had to be performed every time 1 byte was transferred in the transfer process of the character pattern from the character generator to the screen memory 108. In other words, the 8086 and 8088 CPUs cannot use the memory movement by the string instruction. In the present invention, by providing the screen memory control circuit 103, it is possible to perform bit shift processing, mask processing, etc. in place of the CPU 201. Therefore, using the string instruction,
Writing to the screen memory 108 at high speed can be realized.

(2) Processing from the CPU 201 (data processing). Screen memory 10
When drawing a vertical line on 8, write data from CPU201 is
It is written to the screen memory 108 via the multiplexers 104 and 105. The CPU address at this time is a vertically arranged address area in the raster forward direction. The control signal generation circuit 102 is C
The PU address is determined, and a signal for selecting the address converted by the address conversion circuit 106 or the through address is given to the multiplexer 111. Multiplexer 107
Selects an address in the raster forward direction and supplies the address to the screen memory 108.

When part of the screen memory 108 is used as a data storage area, write data from the CPU 201 is written in the screen memory 108 via the multiplexers 104 and 105. The CPU address at this time is a horizontally arranged address area in the raster scan direction. The control signal generation circuit 102 determines the address of the CPU, and gives the multiplexer 111 a signal for selecting the address converted by the address conversion circuit 106 or the through address. The multiplexer 107 selects an address in the raster scan direction and selects the screen memory 108.
Give an address to. According to this method, addresses can be continuously used, and a memory can be effectively used as a data area.

(3) Refresh operation (screen display).

The GDC 101 generates a read signal to the screen memory 108 according to the synchronization timing of the CRT monitor 212. The GDC 101 generates addresses in the order of screen positions and applies a read signal to the screen memory 108 through the control signal generation circuit 102. The data read from the screen memory 108 at the time given for CRT reading is added to the shift register 109, then converted from parallel to serial by a video clock and given to the CRT monitor 212 as a video signal.

〔The invention's effect〕

As described above, according to the present invention, the pixel information storage area for storing pixel information is configured by two groups, and the address of one area is arranged horizontally and the address of the other area is arranged vertically, and the pixel information storage area is formed. Pixel information access means for accessing the pixel information stored in the pixel information storage area is provided by using one of the areas, and the pixel information accessed by the pixel information access means is converted into a video signal. Since the display means for displaying an image on the screen is provided, the pixel information can be accessed either horizontally or vertically, and the display speed can be increased with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part of a device according to the present invention, FIG. 2 is an overall configuration diagram of the device according to the present invention, FIG. 3 is a specific configuration diagram of a screen memory control circuit, and FIG. FIG. 5 is an address configuration diagram of the screen memory according to the present invention, FIG. 5 is a diagram for explaining the address configuration of the screen memory according to the present invention, FIG. 6 is an address configuration diagram of a conventional screen memory, and FIG. It is an address block diagram of a screen memory. 101 ... Graphic display controller, 102 ... Control signal generation circuit, 103 ... Screen memory control circuit, 106 ... Address conversion circuit, 108 ... Screen memory, 201 ... CPU, 211 ... CRT
Controller, 212… CRT monitor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G09G 5/36 G 9177-5G

Claims (1)

[Claims] 1. Two pixel information storage areas for storing pixel information.
The addresses of one area are arranged horizontally and the addresses of the other area are arranged vertically, and are stored in the pixel information storage area by using one of the pixel information storage areas. Pixel information access means for accessing the existing pixel information, and display means for converting the pixel information accessed by the pixel information access means into a video signal and displaying an image on the screen are provided. apparatus.