JPH042970B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer incorporating a RAM (random access memory) with a divided storage area.

Conventionally, in microcomputers that have display drive circuits and RAM built into their chips, part of the RAM or registers has been used as the display area. Necessary data is transferred from this display area to a data store circuit for display, and the display element is driven by a display driver. Or read out necessary data from the display area and change the display data. FIG. 1 shows an example of a conventional display driver circuit. A RAM 5 with a storage capacity of 2 ⁿ × 2 ^m bits is used to hold internal data, and an n-bit X register 4 and Y
It has an m-bit Y register 1 that outputs an address signal 2. The output of the RAM 5 is coupled to an accumulator 7 via a bus 6 having an 1-bit configuration. In addition, the display circuit serially transfers data from the accumulator to the shift register 9, and inputs the data from its parallel output 10 to the driver 12, and the output of the driver 12 is sent to the drive output 11.
The display device 13 is driven by. A part of RAM5 is used as a storage circuit for display data, and each time it is
The data is transferred from the RAM 5 to the shift register via the accumulator 7 in response to a transfer command. Liquid crystals, light emitting diodes, and fluorescent displays are commonly used as display devices, and a dynamic drive system is used to efficiently drive multiple segments with a small number of pins. For example, to drive 128 segments, use a matrix of 8 timing signals and 16 data signals at 1/8 duty. This time problem is if one cycle of display duty is 8
Data transfer for msec must be performed once every 1/8 of 8 msec, that is, every 1 msec. This timing is shown in Figure 2. If To is the period for rewriting data once, that is, 1 msec, and the time for rewriting data is TD.T., in this system, to rewrite data once, the address setting of RAM, that is, the X register. 4. Set the Y register 1, transfer the data in the RAM to the accumulator 7, and from there to the shift register 9.
When this is repeated several times (for example, 4 times if the data is 4 bits parallel in a 16-bit shift register), rewriting of the drive data is completed. In this case, as shown in FIG. 2, the processing time required to rewrite the data is too long, resulting in a serious drawback in that the original processing time of the microcomputer is reduced. Furthermore, if processing during the remaining time after rewriting data does not fall within To, To will vary, causing uneven brightness on the display device.

The purpose of the present invention is to provide a system that can automatically send necessary data to a display device without having to transfer the display data one by one using software, in order to eliminate these conventional drawbacks, thereby reducing the software processing time of a microcomputer. The purpose is to provide a sufficient display without being bothered by the display, and to eliminate fluctuations in brightness and flickering of the display device.

The present invention provides a working area connected to a data input circuit, a display area having a data output circuit and storing display data input from the data input circuit, the display area, the working area, and the display area. In a microcomputer equipped with a memory circuit having a control means for connecting or separating from the data input circuit, means for generating a time division signal, means for selecting an address of the display area based on the time division signal; a holding circuit that latches the display data read out from the display area via the data output circuit based on the time division signal and supplies it to display driving means; When the display data is read out via the control means, the display area, the working area, and the data input circuit are separated from each other by the control means.

FIG. 3 is a diagram for explaining the present invention.
The RAM 17 can read or write the contents of cells whose addresses are specified by the contents of the Y register 15 and the X register 16 via the bus line 25, and can also directly read the contents to the display store circuit 18 without going through the bus line. At this time, due to the action of the timer 19, the X address designated by the necessary signal 23 is separated from the X data 22 by the signal 26 and selected once when necessary.
At this time, 1 bit specified by the RAM address corresponds to 1 display segment on a 1:1 basis. In other words, in 128 segments, out of this RAM 17
Display information is stored in 128 bits. Therefore, data rewriting can be completed by simply rewriting the data in the bits of the RAM corresponding to the segment for which data needs to be rewritten. In addition, the display data can be read out in exactly the same way as before, and as a result, compared to the conventional method, the software does not need to be concerned with the transfer of display data at all, so there is no burden on the software, and the program area can be saved. It becomes possible to simplify the program.

FIG. 4 is a diagram that further embodies the circuit shown in FIG. 3. The Y data is input to the Y register 34, and further converted into two CAS signals by the Y decoder 33.
A circuit 30 that performs read/write control and data multiplexing is connected to data lines 51 and 5.
2 on bus line 45 or read.
RAM consists of 2 ⁿ × 2 ^m × 4 bit cells, where 2 ⁿ ′ × 2 ^m ′ × 4 bits are the display area, and 2 ⁽ⁿⁿ ′ ⁾ × 2 ⁿ × 4 bits are normally used. This will serve as a working area. The X data enters the X register 36 and then directly goes to the X decoder 3.
5 is a working area of 2 ⁽ⁿⁿ ′ ⁾ × 2 ^m × 4 bits, and a display area of 2 ⁿ ′ × 2 ⁿ × 4 bits is input by the multiplexer 38 to the signal from the X register or from the timer. One of the signals is selected and inputted to the _XD decoder 37. timer 3
9 has a function of generating a time division signal for dynamic drive of the display, and a frequency divider 40 is a RAM for outputting the data input to the latch 43.
Multiplexer 3 to select the X address of
Sent to 8th. A new latch 43 is set to set the display data to the next timing by the timer 39.
The differentiator 41 generates a multiplex signal 57 to indicate that it is time to replace the data.
Only at this time, the X _D decoder selects the address set by the frequency divider 40 instead of the X data. 4
2 further narrows the width of signal 57 to generate a strobe signal for latching. FIG. 7 shows this situation. Display selection signal is signal 57
Additionally, the latch strobe signal corresponds to signal 56. The X address is switched to a signal on the timer side only when the display is selected. The latch 43 transfers data from the RAMs 31 and 32 to signals 51 and 5.
2, and all signals are input to the latch 43 in parallel without multiplexing, and are further input to the display driver 44 in parallel.
is input. As a result, you can read and write the entire RAM working area and display area completely freely most of the time, and at the same time, the data in the display area can be sequentially latched only by hardware using a timer.
The data is sent to the dynamic drive and becomes time-division data. At this time, if you are having trouble reading or writing the RAM while reading the display area to the latch side, please refer to Figure 4.
If you output it as a WAIT signal and wait for one instruction only during this period, there will be no problem.

FIG. 5 shows an embodiment of the memory circuit of the present invention, and is a specific example of one bit in the Y direction of the RAM. In the figure, m is the number of bits in the Y register 34, and n and n' are numerical values each indicating the number of bits in the X register 36, each of which corresponds to a specific storage area in the RAM. Input data DI is tri-state inverter 61 when write enable WE is present.
The BIT line is connected to the row where one of the Y addresses selected through 62, that is, one of CAS1 to CAS2 ^m , is selected and transistors 64 and 65 are turned on.
It is input via the line. This data is RAS1~
2 ⁽ⁿⁿ ′ ⁾ or RAS′1 to 2 ⁿ ′ are written to cells in one selected column. Cells 71-73, Cell 7
RAM cells 4 to 75 each correspond to one bit, and the written data is sent to the inverter 63 as an amplifier via the Y address selected by CAS1 to CAS2, and becomes output data Do. At the same time, the BIT line is directly input to the data terminal of latch 69 using inverter 68 as an amplifier. Therefore, in FIG. 4, transistors 64, 65 and inverters 60-63 correspond to control circuit 30, one bit of latch 43 corresponds to latch 69, and one bit of driver 44 corresponds to driver 70. When the timer requests rewriting of the drive data and selects one of RAM'1 to RAM'2n ^' , the data in the inverter 68 becomes valid at this time, so the latch strobe signal STB is input at the same time. Data is latch 69
Stored in BIT line, signal that separates the line
If the DRAM-EN is divided into a working area and a display area on the software, by separating these areas with transistors 66 and 67, reading and writing to the working area and strobe to latch 69 by triggering a timer can be performed simultaneously. This is convenient because the weighting rate can be drastically reduced by the weight signal.

FIG. 6 is another diagram for explaining the present invention, in which the RAM working area 81 and display area 82 are divided in the X direction, and the register for Y address selection and the output of the decoder are data control. is input to the multiplex circuit 80. On the one hand, the X data is sent to the X register that selects the working area 81 and the decoder 8
4 is input. Also, on the display area 82 side, the X data is multiplexed with the signal of the timer 88 as in FIG. 4, and is selected by the decoder 87. Therefore, the signal from the display area 82 enters the latch 85 in parallel m' bits in the Y direction.
Furthermore, it is input to the driver 86.

As described above, the microcomputer of the present invention divides the memory circuit (RAM) into a working area and a display area, and reads data from the display area based on time-division signals.
By providing a holding circuit to latch the read data and separating the above areas during readout, it is possible to reduce the burden placed on the microcomputer in the process of transferring display data from the storage circuit, and improve display quality. .

[Brief explanation of drawings]

Fig. 1 shows an example of a microcomputer with a built-in conventional display driving circuit, Fig. 2 shows the operation timing of the example shown in Fig. 1, and Fig. 3 shows a microcomputer with a built-in display driving circuit to explain the present invention. An example of a computer, FIG. 4 is a specific example of FIG. 3, and FIG. 5 is an embodiment of the present invention.
A specific example of the RAM part, FIG. 6 shows another example of a microcomputer with a built-in display driving circuit for explaining the present invention, and FIG. 7 shows the operation timing of the embodiment of FIG. 4. 30...Write control and data multiplexer, 38...Multiplexer, 40...
... Frequency divider, 41 ... Differential signal generator, 42 ... Strobe signal generator, 31, 81 ... RAM working area, 32, 82 ... RAM display area, 71, 75 ... RAM cell 1 Bit minute.

Claims (1)

[Scope of Claims] 1. A working area connected to a data input circuit, a display area having a data output circuit and storing display data input from the data input circuit, and a display area connected to the display area and the working area. In a microcomputer equipped with a memory circuit having a control means for connecting or separating an area and the data input circuit, means for generating a time division signal, and means for selecting an address of the display area based on the time division signal. and a holding circuit that latches the display data read out from the display area via the data output circuit based on the time division signal and supplies the display data to display driving means, A microcomputer characterized in that when reading out the display data via an output circuit, the display area, the working area, and the data input circuit are separated by the control means.