JPS6227411B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer in which a display driving circuit is built into one LSI chip.

Conventionally, microcomputers that have a display drive circuit built into their chip have used a built-in RAM (random access memory) or part of a register as a display area. Necessary data is transferred from this display area to a data store circuit for display, and the display element is driven by a display driver. Or read out necessary data from the display area and change the display data. FIG. 1 shows an example of a conventional display driver circuit. RAM 5 with a storage capacity of 2 ⁿ × 2 ^m bits is used to hold internal data.
An n-bit X register 4 outputting an X address signal 3 and a Y address signal 2 for addressing
It is equipped with an m-bit Y register 1 that outputs . The output of the RAM 5 is coupled to an accumulator 7 via a bus 6 of l-bit configuration. Further, the display circuit serially transfers data from the accumulator to the shift register 9, and inputs the data from the parallel output 10 to the driver 12, and the output of the driver 12 drives the display device 13 by the drive output 11. A part of the RAM 5 is used as a storage circuit for display data, and each time data is transferred from the RAM 5 to the shift register by software via the accumulator 7 in response to a transfer command. Liquid crystals, light emitting diodes, and fluorescent displays are commonly used as display devices, and a dynamic drive system is used to efficiently drive multiple segments with a small number of pins. For example, to drive 128 segments, set the duty to 1/8 and drive 8 segments.
A matrix is created using 1 timing signals and 16 data signals. The problem with this time is that if one cycle of the display duty is 8 msec, data transfer must be performed once every 1 msec, that is, 1/8 of 8 msec. Figure 2 shows this timing, and To is the cycle of rewriting data once,
Assuming that the time to rewrite data is 1 msec and TDT, in order to rewrite data once in this system, the address of RAM is set, that is, the X register 4 and Y register 1 are set, and the data in RAM is transferred to the accumulator 7. , and further transferred to the shift register 9 from there. When this is repeated several times (for example, 4 times if the data is 4 bits parallel in a 16-bit shift register), rewriting of the drive data is completed. In this case, as shown in FIG. 2, the processing time required to rewrite the data is too long, resulting in a serious drawback in that the original processing time of the microcomputer is reduced. Furthermore, if processing during the remaining time after rewriting data does not fall within To, To will vary, causing uneven brightness on the display device.

The present invention eliminates these drawbacks, and therefore, an object of the present invention is to provide a system that can automatically send necessary data to a display device without having to transfer the display data each time using software, thereby improving the performance of a microcomputer. The goal is to make sure that enough time is available for software processing without being bothered by the display, and to eliminate fluctuations in the brightness and flickering of the display device.

FIG. 3 shows in block diagram form one embodiment of the system of the present invention. RAM17 is Y register 15 and X
In addition to reading or writing the contents of the cell whose address is specified by the contents of the register 16 via the bus line 25, there is also a store circuit 18 for display.
can be read directly without going through the bus line. At this time, due to the action of the timer 19, the X address specified by the necessary signal 23 is changed once when necessary to the signal 2.
6, it is separated from the X data 22 and selected. At this time, 1 bit specified by the RAM address corresponds to 1 segment of the display 1:1.
Correspond with this. In other words, in 128 segments, this RAM1
Display information is stored in 128 bits out of 7 bits. Therefore, data rewriting can be completed by simply rewriting the data in the bits of the RAM corresponding to the segment for which data needs to be rewritten. In addition, the display data can be read out in exactly the same way as before, and as a result, compared to the conventional method, the software does not need to be concerned with the transfer of display data at all, so there is no burden on the software, and the program area can be saved. It becomes possible to simplify the program.

FIG. 4 is a more specific example of the circuit shown in FIG. 3. The Y data is input to the Y register 34, and further converted into 2 ^m CAS signals by the Y decoder 33.
A circuit 30 for read/write control and data multiplexing is connected to data lines 51 and 5.
2 on bus line 45 or read.
RAM is 2 ⁿ × 2 ^m × 4 if 1 word is 4 bits
Consists of cells for bits, 2 ⁿ ′ × 2 ^m × 4 bits is the display area, 2 ⁽ⁿⁿ ′ ⁾ × 2 ^m × 4 bits
The bit becomes the normal working area. The X data that enters the X register 36 and directly enters the X decoder 35 is a working area of 2 ⁽ⁿⁿ ' ⁾ x 2 ^m x 4 bits, and a display area of 2 ⁿ ' x 2 ⁿ x 4 bits. multiplexer 3
8, the signal from the X register or the signal from the timer is selected and input to the X _D decoder 37. Timer 39 has the function of generating a time division signal for dynamic drive of the display, and frequency divider 40 is sent to multiplexer 38 to select the X address of the RAM for outputting the data input to latch 43. The differentiator 41 sends a multiplex signal 57 to indicate that it is time to newly replace data in the latch 43 in order to set the display data to the next timing by the timer 39.
to occur.

Only at this time, the X _D decoder selects the address set by the frequency divider 40 instead of the X data. 4
2 further narrows the width of signal 57 to generate a strobe signal for latching. FIG. 7 shows this situation. Display selection signal is signal 57
Additionally, the latch strobe signal corresponds to signal 56. The X address is switched to a signal on the timer side only when the display is selected. The latch 43 transfers data from the RAMs 31 and 32 to signals 51 and 5.
2, and all signals are input to the latch 43 in parallel without multiplexing, and are further input to the display driver 44 in parallel.
is input. As a result, you can read and write the entire RAM working area and display area completely freely most of the time, and at the same time, the data in the display area can be sequentially latched only by hardware using a timer.
The data is sent to the dynamic drive and becomes time-division data. At this time, if you are having trouble reading or writing the RAM while reading the display area to the latch side, please refer to Figure 4.
If you output it as a WAIT signal and wait for one instruction only during this period, there will be no problem.

Figure 5 is intended to make the present invention more understandable.
This is a specific example of one bit in the Y direction of RAM. In the figure, m is the number of bits in the Y register 34, and n and n' are numerical values indicating the number of bits in the X register 36, each of which corresponds to a specific storage area in the RAM. Input data DI is Light Naple
Tri-state inverter 61,6 when WE is present
Y address being selected via 2, i.e.
A BIT line is connected to the row where one of CAS ₁ to CAS ₂ ^m is selected and transistors 64 and 65 are turned on.
It is input via the line. This data is
It is written to the cell of one selected column of RAS _1-2 ⁽ⁿⁿ ' ⁾ or _RAS'1-2n ^' . Cells 71-73,
Cells 74 to 75 each correspond to one bit in each RAM cell, and the written data is conversely passed through the Y address selected by CAS _{1 to 2} ^m to the inverter 63 as an amplifier, and becomes output data Do. At the same time, the BIT line is directly input to the data terminal of latch 69 using inverter 68 as an amplifier. Therefore, in FIG. 4, transistors 64, 65 and inverters 60-63 correspond to control circuit 30, one bit of latch 43 corresponds to latch 69, and one bit of driver 44 corresponds to driver 70. When the timer requests rewriting of the drive data and selects one of RAS' ₁ to RAS' ₂ ⁿ ', the data in the inverter 68 becomes valid at this time, so the latch strobe signal STB is input at the same time. Data is latch 69
Stored in BIT line, signal that separates the line
If the DRAM-EN is divided into a working area and a display area on the software, by separating these areas with transistors 66 and 67, reading and writing to the working area and strobe to the latch 69 by triggering the timer can be performed simultaneously. This is convenient because the weighting rate can be drastically reduced by the weight signal.

FIG. 6 shows another embodiment of the present invention, in which a RAM working area 81 and a display area 82 are shown.
The division is performed in the X direction, and the outputs of the register and decoder for selecting the X address are input to the data control and multiplex circuit 80. On the one hand, X data is working area 81
is input to the decoder 84. Also, on the display area 82 side, the X data is multiplexed with the signal of the timer 88 as in FIG. 4, and is selected by the decoder 87. Therefore, the signal in the display area 82 is
m' bits enter latch 85 in parallel and are further input to driver 86.

As described above, the present invention is not concerned with data transfer for the display on the software, so it can handle RAM and the display operation can be performed in exactly the same way as before, so there are no restrictions on program length or manufacturing problems. This method is advantageous because it eliminates the troublesome process and the processing time can be shortened accordingly. When this invention is applied to a microcomputer that drives a 1/8 duty (28 segment) display, it becomes possible to reduce the data transfer for the display, which conventionally accounted for about 20% of the time, to almost zero. .

[Brief explanation of the drawing]

Figure 1 shows an example of a microcomputer with a built-in conventional display driving circuit. FIG. 2 shows the operation timing of the example shown in FIG. FIG. 3 shows an embodiment of a microcomputer incorporating a display driving circuit according to the present invention. Figure 4 is a specific example of Figure 3. Figure 5 is a specific example of the RAM part in Figure 4. FIG. 6 shows another embodiment of a microcomputer incorporating a display driving circuit according to the present invention. FIG. 7 shows the operation timing of the embodiment shown in FIG. 30...Write control and data multiplexer, 38...Multiplexer, 40...
... Frequency divider, 41 ... Differential signal generator, 42 ... Strobe signal generator, 31, 81 ... RAM working area, 32, 82 ... RAM display area, 71 to 75 ... RAM cell 1
Bit minute.

Claims (1)

[Claims] 1 a first register that receives first address data and outputs a first address signal; a second register that receives second address data and outputs a second address signal; a memory circuit whose address is selected by the signal and the second address signal, a latch circuit that holds display data read from the memory circuit, and a display device that drives the display according to the display data latched by the latch circuit. In a microcomputer that includes a drive circuit and a time-division signal generation circuit that outputs a time-division signal, the memory circuit has a working memory whose address is selected by the first address signal and the second address signal and which stores data. and a display area whose address is selected by the first address signal and the second address signal to store the display data, and from which the display data whose address is selected by the time division signal and is stored is read out. The microcomputer is further characterized in that the latch circuit latches the read display data in accordance with the time division signal that selects the address of the display area.