JPH0430055B2 - - Google Patents

Description

Detailed Description of the Invention a. Technical Field of the Invention The present invention is directed to verifying the validity of the contents of an address array that manages a buffer storage device when moving data from a main storage device to a buffer storage device in a data processing device. This relates to the method of inspection.

b. Prior art and its problems Generally, in a data processing device, when data is moved from the main memory to the buffer memory, it is fixed length (called a block; for example, 64 bytes).
Register and manage data. Data is moved from the main memory to the buffer memory by dividing the block into several blocks (for example, 8 bytes*8
times). Further, at the same time that data is moved to the buffer storage device, in order to manage the data, the address on the main storage device where the data was stored is stored in an address array in the buffer storage device.

Additionally, the validity of the address array is also checked.

Conventionally, the validity of the address array was not checked when data was moved from the main memory, but was usually checked when the data was actually read from the buffer storage after the movement was completed. Therefore, when it is detected that the contents of the address array are invalid, it is impossible to distinguish whether the cause of the invalidity is due to a fixed failure in the address array itself or whether it occurs when writing or reading the address.

Furthermore, when attempting to check the validity of the contents of the address array during data movement, reading and writing to the buffer storage device cannot be performed at the same time, resulting in the disadvantage that extra processing time is required.

c. Object of the Invention Therefore, the present invention attempts to check the validity of the contents of the address array without requiring extra processing time when moving data from the main memory to the buffer memory.

d.Structure of the Invention Therefore, in the present invention, when moving any one block of data in the main storage device and the address of that block to the buffer storage device, the one block of data is divided into data to be moved. In the processing device, at least the storage element to which the address is moved is made independent of the storage element to which the data is moved, and the address is read from the storage element at the same timing as the last movement of the divided data, and the address is The present invention provides a buffer storage control method characterized by checking the validity of the buffer storage.

e. Embodiment of the Invention The figure is a block diagram showing part of an address array (also referred to as TEG storage or directory) of a buffer storage device that is an embodiment of the invention. In reality, there are multiple circuits shown in the figure (so-called multiple ways).
exist.

In the figure, 1 is a control bit array, 2 is an address array, 3 is a comparison circuit, 4 is a judgment circuit,
5 to 7 indicate or gates.

The data array in which data is stored from main memory is not shown in the figure. Array 1 stores an entry valid indicator V and an entry defect indicator D for each entry in array 2. In the present invention, the data array, address array 2, and control bit array 1 can each be operated independently, so that writing and reading can be performed in parallel.

The array 2 stores part of the block addresses on the main memory of data stored from the main memory to the buffer memory.

In normal use, when the lower bits of the address of data to be accessed are given to arrays 1 and 2, arrays 1 and 2 communicate with comparator circuit 3,
The V, D, and address registered in the entry corresponding to the lower bit of the address are read. Comparison circuit 3
In this case, V of array 1 is "1" (indicating that a valid address is stored in the entry of array 2 corresponding to that address), and D is "0" (indicating that the entry of array 2 corresponding to that address is stored). ), and the address read from array 2 matches the address to be accessed in the upper bits. If there is a match, the determination circuit 4 determines that the data to be read is present in the buffer storage device. If the data you want to read is not in the buffer storage device,
Move data from main storage.

Next, the operation of transferring data from the main memory to the buffer memory and storing it in the buffer memory will be described. For example, it is assumed that one block of 64 bytes is moved eight times each by eight bytes. This assumes that the bus width for data transfer between the main storage device and the buffer storage device is 8 bytes. If one block of data array storage is 64 bytes, eight 8-byte transfers are required.

At the first transfer (move-in), 8-byte data is written to the data array, and "0" is stored in V of array 1, and the upper bit of the address on the main memory of the block is stored in array 2. do. The fact that the first 8 bytes were transferred is
This can be seen from the first move-in signal input to gate 7 in the figure.

From the 2nd to the 7th time, each 8
Write byte data.

At the time of the 8th transfer (this can be seen by the input of the last move-in signal to gate 7 in the figure), the last 8 bytes of data are written to the data array, and V of array 1 is set to "1". Write. This writing is performed by inputting the last move-in signal to array 1. At the same time, the address registered during the first movement is read from array 2. The read address is compared in comparison circuit 3 with the upper bits of the address on the main memory of the block. As a result of the comparison, a match indicates that the address is correctly stored in array 2, and a mismatch indicates that it is incorrectly stored.

If they do not match, the entry is considered to be defective, and the determination circuit 4 displays an error. Furthermore, "1" (indicating that it is defective) is registered in D of array 1. However, this requires extra time.

Furthermore, even if the comparison results in a match, if the comparison results of multiple other comparison circuits do not all match, the same address may be stored redundantly in one of the other multiple address arrays. Therefore, the determination circuit 4 displays an error.
Therefore, while the 8-byte transfer is performed 8 times,
In parallel, perform the following operations. When the first data is stored in the data array, the address is stored in the address array, and when the eighth data is stored in the data array, the address is stored in the address array at the time of the first data storage. The stored address is read out and a comparator is used to check whether the stored address is correct. That is, since the address check is performed in parallel without comparing after the completion of 64-byte data transfer, the check can be performed without taking extra time. Checking the validity of an address is not limited to simply comparing one address array, but when multiple address arrays are created, the comparing circuit 3
It is also possible to adopt a configuration in which an error is displayed when a match is detected. As mentioned above, this point is performed by the determination circuit 4 shown in the figure.

f Effects of the Invention According to the present invention, the validity of an address array can be checked without spending extra time.

[Brief explanation of drawings]

The figure is a block diagram showing a part of an address array of a buffer storage device according to an embodiment of the present invention, in which 1 is a control bit array, 2 is an address array, 3 is a comparison circuit, 4 is a judgment circuit, 5- 7 indicates an or gate.

Claims (1)

[Claims] 1. Any one block of data in the main storage device;
When storing the address of the block in the buffer storage device, the data of the one block is divided into multiple transfers and transferred from the main storage device to the buffer storage device. , the buffer storage device includes a data storage section that stores data, an address storage section that stores addresses corresponding to entries in the data storage section, and a comparison circuit, and the data storage section and the address storage section The unit operates independently, divides the data into multiple times and sequentially transfers the data from the main memory device to the buffer storage device, and also transfers the address of the data to the address storage unit and stores the address, While storing one block of data in the data storage section, a value obtained by reading out the address stored in the address storage section and an address transferred to the address storage section are stored in the address storage section. A buffer storage control method characterized in that the bypassed values are compared in the comparison circuit. 2. The buffer storage device has a plurality of address arrays, and determines that a match in the address comparison is detected in the plurality of address arrays, and displays an error. Buffer storage control method described in Section 1.