JPH0430746B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an SOI (Silicon on Insulator) process, and particularly to a device configuration for forming a complementary MIS on an insulating substrate.

(b) Technical background The most common complementary MIS semiconductor device
CMOS combines p-channel and n-channel with opposite polarity to form opposite transistors to perform circuit functions, and has advantages such as high operating speed and low static power loss, resulting in low power consumption. be. Despite these advantages in circuit configuration, the normal MOS process (bulk type CMOS) is complicated, especially in the p-well (p-well) for the n-channel region.
-well) diffusion, and the large p-well diffusion depth makes it difficult to miniaturize IC chips, and it is necessary to precisely diffuse and form low-concentration p-type impurities.

On the other hand, SOI technology (CMOS/SOI) or
The process of configuring CMOS on spinel crystals or non-single crystals (Al ₂ O ₃ , MgO) using SOS technology (CMOS/SOS) is more advantageous than the bulk type CMOS process mentioned above, and with large-scale integration, it is becoming more popular for watches.
It is being applied to ICs, memories, logic, microcomputers, etc.

(c) Prior art and problems Figures 1 and 2 are cross-sectional views showing conventional CMOS semiconductor devices. Figure 1 shows an example of bulk CMOS and Figure 2 shows an example of CMOS/SOS using the epitaxial method. It is a diagram.

In FIG. 1, an n-type silicon substrate 1 is doped with p-type impurities at a low concentration to form a p-well diffusion layer 2, and a gate region is further diffused to form an n-channel region 3. P channel region 4 at the corresponding position
A circuit is constructed by forming the electrodes 5 and wiring the electrodes 5. As shown in the figure, the p-diffusion region occupies a large area, which is disadvantageous for integration, and there are also problems in impurity diffusion control.

In FIG. 2, an n-type eptaxial layer is formed on a sapphire substrate 6 to form a p-channel region 7 and an n-channel region 8, and an electrode 9 is wired to each contact hole to form a circuit. When configuring a CMOS circuit on an insulating substrate like this, for example, polycrystalline silicon (poly-si) on a quartz glass substrate is used.
When silicon is melted and recrystallized to become a single crystal, tensile stress is generated in silicon, and electron mobility increases, while hole mobility decreases due to tensile stress, which is the exact opposite relationship.

On the other hand, compressive stress occurs in the epitaxial silicon layer on the sapphire substrate, causing electron mobility to decrease and hole mobility to increase. Therefore, when a CMOS circuit is formed on a quartz glass or sapphire substrate, the operating characteristics of either the p-channel or n-channel MOS circuit become slow, and the overall high speed is lost.

As a result, an n-channel MOS circuit is formed on a silicon dioxide layer (SiO ₂ ), and a p-channel MOS circuit is formed on a spinel layer (Al ₂ O ₃ -MgO), and electron mobility and hole mobility are respectively controlled by strain. The focus is on increasing the speed of operating characteristics by increasing the device configuration.

(d) Object of the Invention In view of the above-mentioned points, an object of the present invention is to provide an effective complementary MIS semiconductor device configuration formed on an insulating substrate, and to improve its operating characteristics.

(e) Structure of the Invention According to the present invention, the first silicon layer formed on the first region of the substrate and the second silicon layer of the substrate
a second silicon layer formed on the region, an N-channel MIS type semiconductor device formed on the first silicon layer, and a P channel formed on the second silicon layer.
a channel MIS semiconductor device, a first insulator formed between the first silicon layer and the substrate and applying compressive stress to at least a channel portion of the first silicon layer of the N-channel MIS semiconductor device; a second insulating film formed between the second silicon layer and the substrate and applying tensile stress to at least a channel portion of the P-channel MIS type semiconductor device of the second silicon layer. Achieved by complementary MIS semiconductor devices. Further, the present invention is achieved by a complementary MIS semiconductor device in which the first insulating film is silicon dioxide and the second insulating film is spinel.

(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 3 shows CMOS/SOI, which is an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a multilayer CMOS/SOS according to another embodiment of the present invention.

As shown in FIG. 3, a silicon dioxide layer 12 and a spinel layer 13 are selectively formed on a silicon substrate 11, and an n-channel MOS 1 is formed on this silicon dioxide layer 12.
A p-channel MOS 15 is formed on the spinel layer 13. For example, a p-type island is formed in the n-channel region, that is, the silicon dioxide layer 12, and the n-channel
Phosphorus (P) is diffused to form n-type source and drain regions 16 and 17 for MOS formation. On the other hand p
An n-type epitaxial layer is formed on the spinel layer 13, which will serve as a channel region, and boron is diffused to form a p-type source,
Drain regions 18 and 19 are formed. Insulating layer 20
A window for taking out the electrode is opened, and an aluminum film is deposited and patterned to form the contact electrode 21.

With such a device configuration, tensile stress acts on the n-channel on the silicon dioxide layer, increasing electron mobility, and increasing the electron mobility on the p-channel on the spinel layer.
In the channel, compressive stress acts and the mobility of holes increases, resulting in high-speed operation characteristics (compared to conventional
1.5 to 1.7 times).

FIG. 4 shows an embodiment in which a CMOS device is formed on a sapphire substrate 22, in which two p-channel MOS devices 23 and 24 are formed on a spinel layer, and an n-channel MOS device 26 is further formed via an insulating layer 25 (for example, SiO ₂ ). , 27 elements are stacked and each element is connected by vertical wiring to create a double configuration.
CMOS/SOS can be obtained. With such a configuration, the mobility of holes increases in the lower p-channel MOS, and the mobility of electrons increases in the n-channel MOS, resulting in a high-speed, low-power switch element.

(g) Effect of the invention As explained in detail above, the complementary type shown in the present invention
By using an MIS semiconductor device, it is effective to increase the speed of operating characteristics.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views showing conventional CMOS semiconductor devices, and Figure 1 is a bulk type CMOS,
Figure 2 shows CMOS/SOS using the epitaxial method.
Figure 3 is a cross-sectional view showing a CMOS/SOI which is an embodiment of the present invention, and Figure 4 is a cross-sectional view showing a multilayer CMOS/SOS which is another embodiment of the present invention. be. In the figure, 11... silicon substrate, 12... silicon dioxide layer (SiO ₂ ), 13... spinel layer, 14, 2
6, 27...n channel MOS, 15, 23, 24
...p channel MOS, 16,17...n type source,
Drain region, 18, 19...p-type source, drain region, 20, 25... insulating layer, 21... contact electrode, 22... sapphire substrate.

Claims (1)

[Claims] 1. A first silicon layer formed on a first region of a substrate, a second silicon layer formed on a second region of the substrate, and the first silicon layer. N channel formed in
MIS type semiconductor device and P channel formed in the second silicon layer
an MIS type semiconductor device; a first insulating film formed between the first silicon layer and the substrate and applying compressive stress to at least a channel portion of the first silicon layer of the N-channel MIS type semiconductor device; and a second insulating film formed between the second silicon layer and the substrate and applying tensile stress to at least a channel portion of the P-channel MIS type semiconductor device of the second silicon layer. A complementary MIS type semiconductor device characterized by: 2 the first insulating film is silicon dioxide;
2. The complementary MIS semiconductor device according to claim 1, wherein said second insulating film is spinel.