JPH07112012B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a MOS semiconductor device to which SOI (Silicon On Insulator) technology is applied.

(Prior Art) Conventionally, a MOS type semiconductor device using the SOI technology mainly creates a MOS element in the SOI film, and a MOS element in the SOI film and another element on the substrate are connected via wiring. In many cases, they are combined to give and receive signals. In addition, in the manufacturing method for manufacturing the semiconductor device, the majority of the methods always use the seed. Therefore, when forming a MOS element on an SOI film, there are few that positively utilize the advantages of the SOI structure and those that functionally utilize the advantages of the structure. That is, the SOI element merely uses the conventional function as the SOI element and the MOS element on the substrate simply uses the conventional function as the MOS element.

With such a method, it cannot be said that the advantages of the SOI laminated structure are effectively utilized, and there remains a problem to be improved. In the method, for example, a wiring is required to connect the MOS element on the substrate and the MOS element in the SOI film, and although the length of this wiring is shorter than that when each element is formed flat, it is sufficient. It cannot be said that it is very short. In addition, it is necessary to perform wiring around the MOS element, and the wiring region for this becomes a factor that hinders high speed and high integration of the element.

(Problems to be Solved by the Invention) As described above, conventionally, there is a method of manufacturing a MOS semiconductor device by utilizing the SOI technique, but the original advantage of the SOI structure cannot be fully exerted.

The present invention has been made in consideration of the above circumstances, and an object thereof is to sufficiently exert the true advantages of the SOI laminated structure and to apply the same to a circuit function.
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can achieve significantly higher speed and higher integration than conventional devices.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to form a MOS transistor in each of an upper recrystallized semiconductor layer and a lower semiconductor substrate through an insulating film,
In addition, the source / drain and gate of each transistor are partially shared.

That is, the present invention provides a MOS type semiconductor device in which a single crystal semiconductor layer is provided on a semiconductor substrate via an insulating film, and two MOS transistors are formed on the substrate and the semiconductor layer.
Forming a source / drain of said MOS transistor on the surface of said substrate, and forming a second MOS on one side of said source / drain.
In this structure, the gate and the drain of the second MOS transistor are formed in the semiconductor layer, and the gate and the drain of the first MOS transistor are formed.

According to the present invention, in the method for manufacturing a semiconductor device having the above structure, a second conductivity type single crystal semiconductor layer is formed on a first or second conductivity type semiconductor substrate via an insulating film, and then the semiconductor layer is formed on the semiconductor layer. A mask is provided at a predetermined distance from the substrate, ions of the first conductivity type are ion-implanted, and diffusion layers of the first conductivity type are formed on the substrate surface and the semiconductor layer, respectively. A first MO having the first conductivity type diffusion layer as a source / drain and one of the second conductivity type layers adjacent to the first conductivity type diffusion layer formed in the semiconductor layer as a gate.
A second conductive type layer which constitutes an S transistor and has a first conductive type diffusion layer sandwiched between the first conductive type diffusion layer formed in the semiconductor layer, and one of the first conductive type diffusion layer formed in the substrate as a gate; In this method, a MOS transistor of No. 2 is configured.

(Operation) According to the present invention, the source or the drain of the MOS element (first MOS transistor) on the substrate is connected to the MOS in the SOI film through the insulating film (gate insulating film) between the substrate and the semiconductor layer. The gate electrode of the element (second MOS transistor) or, conversely, the source or drain of the second MOS transistor is the gate electrode of the first MOS transistor, and the vertically stacked MOS transistors are mutually different elements. It is the electrode of. For this reason, it is possible to significantly increase the degree of integration by utilizing the laminated structure, and further, it is possible to reduce the contact resistance of the wiring portion, the delay time, and the number of steps of the wiring portion.

In addition, a first MOS transistor is a source / drain region of the first MOS transistor and a channel region of the second MOS transistor.
Conductive diffusion layers can be formed simultaneously using the same mask, that is, the necessary impurity diffusion layers for the substrate and SOI film can be formed by self-alignment, so the number of patterning steps and the number of required masks can be reduced. Is. Furthermore,
By maximizing the high integration, which is an advantage of the laminated structure, the occupied area can be significantly reduced compared to the conventional one.

(Examples) The details of the present invention will be described below with reference to illustrated examples.

FIG. 1 is a perspective view showing a schematic structure of a MOS type semiconductor device according to an embodiment of the present invention. In the figure, 10 is an n-type single crystal silicon substrate, and p ⁺ type layers 21 and 22 are formed in the surface layer of this substrate 10 by impurity diffusion. p ⁺ type layers 21 and 22 are MOS
It becomes the source / drain region when forming the transistor. The channel region 23 between the p ⁺ type layers 21 and 22
May have the same conductivity type as that of the substrate 10, or may be a p-type layer by diffusing impurities on the surface of the substrate 10.

A single crystal silicon layer 40 is formed on the substrate 10 with a thin insulating film 30 interposed therebetween. In the silicon layer 40, n ⁺ type layers 41 and 42 and a p type layer 43 are formed by impurity diffusion. The p-type layer 43 serves as the channel region of the MOS transistor, and the n ⁺ -type layers 41 and 42 on both sides of the p-type layer 43 serve as the source / drain regions of the MOS transistor. The thin insulating film serves as the gate oxide film of the MOS transistor.

Here, the n ⁺ -type layer 42 is arranged above the channel region 23 between the p ⁺ -type layers 21 and 22, and the p ⁺ -type layer 21 is arranged below the channel region 43 between the n ⁺ -type layers 41 and 42. ing. And the p ⁺ -type layers 21, 22 and n
^{The +} -type layer 42 constitutes a p-channel first MOS transistor, and the n ⁺ -type layers 41 and 42 and the p ⁺ -type layer 21 form an n-channel second MOS transistor.
The MOS transistor is configured. In the figure, 60 indicates an oxide film for element isolation.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device. First, as shown in FIG. 2A, the surface of the n-type single crystal silicon substrate 10 having a plane orientation (100) is oxidized to form a gate oxide film (insulating film) 30. Then, as ion implantation of p-type impurities, for example, phosphorus is carried out at 130 KeV and the dose is 1 × 10 ¹⁶ cm 2.
Ion implantation is performed under the condition of ^-3 to form the p-type layer 20 on the entire surface of the substrate 10. This implantation of p-type impurity ions is to make the impurity concentration on the substrate surface uniform. Then CVD
A polycrystalline silicon layer 40 'is deposited on the gate oxide film 30 by the method.

Then, the polycrystalline silicon layer 40 'is annealed by an electron beam and recrystallized to form a silicon single crystal layer 40 as shown in FIG. 2 (b). At this time, amorphous silicon may be recrystallized instead of polycrystalline silicon,
Further, instead of the electron beam, another energy beam such as a laser beam or an ion beam may be used. Further, a recrystallization method using a tungsten heater or zone melting or a recrystallization method using lamp annealing may be used. Further, a protective film made of SiO ₂ or the like may be formed on the upper portion for recrystallization. After that, n-type impurities are ion-implanted into the silicon single crystal layer 40 to form an n ⁺ -type layer.

Then, as shown in FIG. 2C, a mask for ion implantation
50 is provided to perform ion implantation of p-type impurities. At this time,
The acceleration voltage for ion implantation is selected so that the p-type impurity is sufficiently implanted not only in the silicon layer 40 but also in the silicon substrate 10. As a result, the p ⁺ type layers 21 and 22 are formed on the surface of the substrate, and the p type layer 43 is formed on the silicon layer 40. Where p
P ⁺ type layers (source / drain) 21 and 22 are formed on the surface of the substrate by ion implantation of the type impurities, and the p type layer 4 is formed on the silicon layer 40.
By forming 3, the n ⁺ type layers (source / drain regions) 41, 43 are formed on both sides of the layer 43. That is, the sources and drains of the two MOS transistors are realized by self-alignment.

Next, as shown in FIG. 2 (d), the mask 50 is removed, and only the necessary portion of the silicon layer 40 is patterned into an island shape, and further element isolation is performed as necessary.

Instead of the step shown in FIG. 2C, the silicon layer 40 may be patterned into an island shape in advance, and the mask 50 may be formed as shown in FIG. 2E to perform ion implantation. Further, an oxide film or the like as a protective film may be formed on the side wall of the silicon layer 40 during this ion implantation.

Thus, the first MOS transistor (p-channel depletion type) Q ₁ having the p ⁺ type layers 21 and 22 as the source / drain and the n ⁺ type layer 42 as the gate is formed, and the n ⁺ type layer 41 is formed. A second MOS transistor (n-channel enhancement type) Q ₂ is formed with the sources and drains of 42 and 42 and the gate of the p ⁺ type layer 21. That is, the drain of the transistor Q ₁ is also serves as a gate of the transistor Q _2, the source of the transistor Q ₂ is configured to serve as the gate of the transistor Q ₁ is realized. In this case, unlike the conventional device, the wiring area is not required for connecting the two transistors, and the two transistors can be formed in an extremely small area.
It is possible to stack Q ₁ and Q ₂ .

Next, an example in which the device of this embodiment is applied to a MOS inverter will be described. FIG. 3A is a sectional view schematically showing the basic structure of the MOS inverter, and FIG. 3B is its equivalent circuit configuration diagram. The drain of transistor Q ₁ is a transistor
Connected to the gate of Q ₂ , these connection points become the input terminals. The source of the transistor Q ₂ is connected to the gate of the transistor Q ₁ , and these connection points are grounded via the resistor R ₁ . This resistance R ₁ is about the same size as the effective resistance of the channel, and is 1 kΩ here. The drain of the transistor Q ₂ is connected to the power supply (+ 5V), the source of the transistor Q ₁ is connected to the output terminal, and is grounded via the resistor R ₂ . This resistance R ₂ needs to be larger than that of R ₁ , and here it is set to 20 KΩ.

In the above structure, when put input signal 1V as "H" input signal, the transistor Q ₂ is for n-channel, closed opening is had gate, a current flows from the drain to the source. At this time, the effective resistance of the channel is 1 KΩ, and the resistor R ₁ connected to the source is also grounded at ₁ KΩ.
A gate voltage of 2.5V is applied to the gate of transistor Q ₁ . Since the transistor Q ₁ is a p-channel, the gate is closed and the output connected to the source is "L" (0V),
The output signal is inverted. On the other hand, when the input signal is 0.1V when the input is “L”, the gate of transistor Q ₂ closes,
The source potential is 0 V, and the gate of transistor Q ₁ is
It becomes 0V and the gate opens. Then, 0.1 V of the input signal becomes the drain voltage, and a current flows. The resistance connected to the source is sufficiently larger than the effective resistance of the channel and is almost equal to the voltage effect, and an output signal "H" of about 0.1 V is obtained. The above results are shown in Table 1.

Further, when the operation time was measured by the device of this example,
It was 20 picoseconds. This means that the semiconductor device formed by the conventional method has achieved a high speed exceeding 30 picoseconds. Furthermore, when the area occupied by the elements was compared, it was possible to reduce the area to 70% or less compared to the conventional device.

Thus, according to this embodiment, M and M are respectively formed on the substrate and the SOI film.
By forming an OS transistor and also using a part of each electrode, a semiconductor device in which there is no signal delay and high integration can be provided. In addition, a first impurity diffusion step for forming the source / drain, etc.
Moreover, the second MOS transistor can be self-aligned, and there is an advantage that the manufacturing process can be simplified.

The present invention is not limited to the above embodiment. For example, the same effect can be obtained by using germanium, gallium arsenide, indium phosphide or the like instead of the silicon substrate. Further, although a single crystal silicon wafer is used as a semiconductor substrate in the examples, a single crystal semiconductor thin film obtained by recrystallization, for example, SOS (Silicon On Sapphire) can also be used. In addition, various modifications can be made without departing from the scope of the present invention.

As described in detail above, according to the present invention, a MOS transistor is formed in each of the upper recrystallized semiconductor layer and the lower semiconductor substrate via the insulating film, and the source / source of each transistor is formed.
By sharing a part of the drain and the gate, it is possible to fully realize the real advantages of the SOI laminated structure and to realize a semiconductor device and a manufacturing method thereof that can achieve significantly higher speed and higher integration than conventional devices. it can.

[Brief description of drawings]

FIG. 1 is a perspective view showing a schematic structure of a MOS type semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device, and FIG. 3 is an inverter using the semiconductor device. FIG. 3 is a schematic diagram and a circuit diagram showing the basic configuration of FIG. 10 ... n type single crystal silicon substrate, 20 ... p type layer, 21,22 ... p ⁺
Type layer (source / drain region), 23 ... p type layer (channel region), 30 ... gate oxide film (insulating film), 40 '... polycrystalline silicon layer, 40 ... single crystal silicon layer, 41, 42 ... n ⁺ P-type layer (source / drain region), 43 ... p-type layer (channel region),
50 ... mask, 60 ... isolation insulating film, Q ₁ ... first MOS transistor (p-channel depletion type), Q ₂ ...
Second MOS transistor (n-channel enhancement type), R ₁ , R ₂ ... Resistors.

Claims (1)

[Claims] 1. A step of forming a second-conductivity-type single-crystal semiconductor layer on a first or second-conductivity-type semiconductor substrate via an insulating film, and maintaining a predetermined distance on the semiconductor layer. Two or more masks are provided, and impurities of the first conductivity type are ion-implanted at an acceleration voltage sufficient to ion-implant not only the semiconductor layer but also the substrate surface, and the substrate surface and the semiconductor layer are vertically moved by the mask. Correspondingly, the step of forming two or more first-conductivity-type diffusion layers, wherein the first-conductivity-type diffusion layer is used as a source / drain on the surface of the substrate, and a mask region sandwiched therebetween is a gate. of
A second MOS transistor is formed, which constitutes a MOS transistor, and uses a mask region as a source / drain in the semiconductor layer and a gate as the first conductivity type diffusion layer sandwiched between the mask region and the semiconductor region. Production method.