JPH0432425B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Fourier transform device used, for example, in a radar signal processing device.

A Fourier transform device used in a radar signal processing device is used to detect a target by suppressing unnecessary signal components and improving the S/N ratio by performing frequency analysis of the Doppler component of a received signal. The present invention is a saturation gain control device that minimizes the loss of small signal data due to underflow during calculation in the Fourier transform device described above. It is characterized by preventing overflow from occurring during conversion operations.

FIG. 1 shows an example of a radar signal processing device using the above Fourier transform device. In Figure 1, the radio waves emitted from antenna 1 are reflected from the target,
A portion of the reflected echo is received again by the antenna 1 and detected by the receiver 2. Receiver 2
The video signal output from is input to the pre-stage signal processing device 3. In the pre-stage signal processing device 3, the video signal is converted into a digital signal, and processing such as suppression of clutter, which is an unnecessary signal, and pulse compression are performed. The output of the pre-stage signal processing device 3 is input to the Fourier transform device 4 of the present invention, where it is multiplied by a time window function and then subjected to a Fourier transform (hereinafter referred to as FFT) operation to be decomposed into frequency components. The output of the Fourier transform device 4 has distance direction information divided into frequency bins, and is input to the subsequent signal processing device 5. After removing the contents of frequency bins containing clutter components, the subsequent signal processing device 5 automatically detects the target within each frequency bin, making it possible to derive the position and velocity of the target.

In the Fourier transform device 4, the operations are repeated multiplication and addition. At this time, floating-point calculations are difficult in high-speed processing such as radar signal processing, and fixed-point calculations are usually performed. As a result, data may overflow during calculation, so overflow is prevented by shifting down the output by 1 bit each time an addition is performed.

However, if a small signal is input, the signal may be lost during calculation due to 1 bit being discarded by the shift down.
In order to solve this problem, there is a saturation gain control circuit that has a function of preventing the above-mentioned overflow and at the same time minimizing signal loss. The present invention relates to this saturation gain control circuit.

[Prior art]

The second is an example of a fast Fourier transform device using a conventionally used saturation gain control circuit. In FIG. 2, the saturation gain control circuit 6 converts the complex input data into 1CPI (coherent processing
interval (data sample time for Fourier integration) is monitored, and the maximum absolute value of the complex input data during that period is detected and held. Thereafter, in the next CPI, the control signal I, which is the output of the saturation gain control circuit 6, controls the complex input data a to be shifted up within a range where the maximum value does not overflow when the complex input data a passes through the shifter 7. For example, in Figure 2, if the bit length of the data line of the complex input data is m, and the maximum absolute value between a certain CPI is n bits, then at the next CPI, the shifter 7 carries (m-n) bits. do. The output of shifter 7 is sent to calculation memory 8 by 1 CPI
After that, the butterfly calculation is repeated with the butterfly calculation section 9. For example, when performing an l-point FFT, calculations are repeated log ₂ l times between the calculation memory 8 and the butterfly calculation unit 9. The butterfly calculation unit 9 includes an adder, and depending on the input, the output may overflow. Therefore, the input to the butterfly calculation unit 9 is a 1/2 scaler 10,
Always carried up by 1/2.

As described above, the Fourier transform apparatus shown in FIG. 2 can suppress signal loss during the calculation by performing the FFT operation after the complex input data is shifted within a range that does not saturate. However, in the above device, the maximum value of the next CPI is predicted using data from one CPI before, so a maximum value larger than the prediction is input between the next CPIs, and the shifter 7 may overflow.

Figure 3 shows a Fourier transform device that solves the above problem by using a buffer memory that temporarily stores data for 1 CPI. In FIG. 3, complex input data is input to the saturation gain control circuit 6.
The maximum absolute value between 1CPI is detected and simultaneously stored in the buffer memory 11. At the next CPI, the complex input data stored in the buffer memory 11 is read out and shifted by the shifter 7. At this time, since the control signal A for controlling the shifter 7 is generated using the maximum value of the complex input data A, data does not overflow in the shifter 7. This buffer memory 11 is originally used to temporarily store input data, which is a radar reception signal that is constantly sent, for FFT calculation.

[Summary of the invention]

By the way, the Fourier transform device shown in Figure 3 prevents the loss of small signals during FFT calculation by carrying the input data for FFT calculation to the maximum bit length, but in FFT calculation with a large number of points, Note that the loss of small signals due to digit reduction during calculation poses a problem.

The present invention solves the above problem by performing saturation gain control during transfer from the calculation memory to the butterfly calculation section.

[Embodiments of the invention]

FIG. 4 shows an example of the Fourier transform device of the present invention. In FIG. 4, the complex input data is processed by the first saturation gain control device 6a, similar to the device shown in FIG.
The maximum absolute value between 1CPI is detected and stored in the buffer memory 11 at the same time. The first saturation gain control device 6a consists of an absolute value detection circuit, a maximum value comparator, and a register between CPIs, and holds the maximum value between CPIs and determines the shift amount of the first shifter 7a at the next CPI. do. buffer memory 1
The complex input data for 1CPI stored in 1 is as follows.
The signals are sequentially read out using the CPI and sent to the first shifter 7a. At this time, the control signal A of the first shifter 7a is determined by the maximum value of the complex input data currently being sent to the first shifter 7a, so the output of the first shifter 7a will not overflow. .

The output of the shifter 7a is sent to the calculation memory 8, and FFT calculation is performed with the butterfly calculation section 7. The output of the arithmetic memory 8 is sent to the second shifter 7b. The second shifter 7b performs a 1/2-fold or 1-fold shift, and the output of the calculation memory 8 is first multiplied by 1/2 and sent to the butterfly calculation unit 9. The butterfly calculation unit 9 multiplies the input data by a twist factor, performs two-point DFT (discrete Fourier transform), and stores the result in the calculation memory 8. At this time, the second saturation gain control circuit 6b monitors the output of the butterfly calculation section and detects the maximum value of all the data of the first butterfly calculation output. In the second butterfly operation, if the number of bits of the maximum value reaches the maximum bit length, the second saturation gain control circuit 6b performs the following:
The second shifter 7b is controlled to lower the digit by 1/2, and if it has not reached the lower value, the second shifter 7b is controlled to lower the digit by 1. Arithmetic memory 8 and butterfly computing section 9
As mentioned in the explanation of Figure 2, the number of operations between
It increases as the number of FFT points increases. Therefore, in the conventional device, if k operations are performed, 1/
It is possible that some signals are multiplied by 2k and disappear, but in the device shown in FIG. 4, the signal does not decrease because the shifter is multiplied by 1 unless the output of the butterfly calculation unit 9 reaches the maximum bit length for each calculation.

[Effects of the Invention] As described above, according to the present invention, even for FFT calculations with a large number of points, it is possible to perform complete saturation gain control without signal loss or overflow during the calculation.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a radar signal processing device using the Fourier transform device of the present invention, FIG. 2 is a diagram showing a Fourier transform device using a conventionally used saturation gain control circuit, and FIG. The figure shows a Fourier transform device that is an improved version of the device shown in FIG.
FIG. 4 is a diagram showing a Fourier transform device of the present invention using a saturation gain control circuit, in which 1 is an antenna, 2 is a receiver, 3 is a front-stage signal processing device, 4 is a Fourier transform device, and 5 is a rear-stage signal processing device. A signal processing device, 6 a saturation gain control circuit, 7 a shifter, 8 arithmetic memory,
9 is a butterfly calculation unit, 10 is a 1/2 scaler, 1
1 is a buffer memory. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1 Real-time complex input data is converted to 1CPI (Coherent
a first saturation gain control circuit that detects the maximum value of the complex input data within 1 CPI and controls a first shifter; and a first shifter that changes the gain of the buffer memory output. , the output of the first shifter is 1CPI
Between the arithmetic memory that stores data and the arithmetic memory.
It includes a butterfly calculation unit that performs FFT calculation, a second saturation gain control circuit that detects the maximum value of the output of the butterfly calculation unit and generates a control signal, and a second shifter that controls the output of the calculation memory. A Fourier transform device characterized by: