JP2667945B2 - Video signal processor for radar system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radar system,
More particularly, the present invention relates to a video signal processing apparatus of a radar system for extracting video data from a pre-processed radar signal received from an antenna.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a general radar system, and a radar system will be generally described with reference to FIG. A radar system transmits a specific form of an electron wave, such as a pulse-modulated sine wave, and then searches for the nature of the opposite wave.

In FIG. 2, an antenna 101 is operated in a time-division manner, and emits an electron wave having a specific form or receives a reflected wave thereof. Pulse modulator 10
4 generates an electron wave of a specific form, that is, a pulse-modulated sine wave. The electron wave generated from the pulse modulator 104 is applied to the antenna 101 via the transmitter 103 and the duplexer 102, and then applied to the antenna 101.
Through the air. Here, the duplexer 10
2 performs the function of switching the mode of the antenna 101. The antenna 101 is used as a transmitting antenna for a certain period of time, and then used as a receiving antenna for the next certain period of time. That is, the antenna 101 is set in the transmission mode for a certain period by the duplexer 102, and is set in the reception mode for the next certain period. On the other hand, the received reflected wave is applied to the mixer 106 through the low noise RF amplifier 105.

The mixer 106 mixes the local oscillation signal generated from the local oscillator 107 with the output signal of the low noise RF amplifier 105, and thereby the low noise RF amplifier 105.
Perform the function of transitioning the output signal of FIG. The intermediate frequency amplifier 108 amplifies the output signal of the mixer 106, and can adjust the gain by a signal applied from an automatic gain control unit AGC included in the preprocessor 109. The preprocessor 109 and the video signal processor 111 basically perform a function of detecting target data from a received signal in a radar system. At this time, the preprocessor 109 and the video signal processor 111 have CFAR (Constant False).
Performs various algorithms to maintain the alarm rate.

First, a preprocessor 109 includes a time sensitivity adjuster (STC: Sensitivity Time Control), an FTC
(Fast Time Control) and automatic gain control unit (AGC:
Automatic Gain Control) . STC
And FTC respectively remove various forms of clutter contained in the received radar signal . Also, AGC
Adjusts the gain of the intermediate frequency amplifier 108. Here, the preprocessor 109 outputs the first radar signal, ie, S
The above processing by all of TC, FTC and AGC is performed.
And the second radar signal, ie, STC and FT.
And the radar signal processed by C
Together, these signals are applied to the video signal processor 111.
You.

FIG. 11 is a block diagram of a video signal processor 111 of a conventional radar system, which comprises an analog-to-digital converter 201, a cell averaging circuit 202, and a buffer memory 203.

Referring to FIG. 11, the analog-to-digital converter 201 converts analog first and second radar signals into digital first and second radar signals using A / D converters 204 and 205, respectively. It is converted into a two-radar signal. Here, the A / D converter operates with a sampling clock having a constant frequency. The sampling clock will be closely related to the range resolution. Therefore, in order to improve the range resolution, the sampling operation can be performed at a higher frequency.
Requires a D converter. However, the sampling clock frequency of the A / D converter depends on the element characteristics, and in general, the maximum sampling clock frequency at which the A / D converter can operate stably is determined. Therefore,
The range resolution of the conventional radar system is A / D
Limited by the maximum sampling clock frequency at which the converter can operate.

The cell averaging circuit unit 202 removes background noise and background clutter from the data output from the A / D converters 204 and 205, and removes them from the buffer memory 20.
8 and 209, which adaptively set a threshold value for discriminating whether or not the data is target data. here,
The method for adaptively setting the critical value is cell average value (cella
veraging).

After storing the output of the cell averaging circuit 202, the buffer memories 208 and 209 output the stored data at the request of a scan converter or a tracking processor. Here, the scan converter converts the video data of the polar coordinate format stored in the buffer memory 208 into the video data of the rectangular coordinate format, and applies the video data to the raster scan type display unit. A function of estimating a next operation by calculating a speed, an acceleration, and the like of a target using the video data stored in the buffer memory 209 is performed.

FIG. 12 shows the cell averaging circuit shown in FIG.
The detailed block diagrams of the units 206 and 207 show a first delay line 210, a second delay line 213, an output cell 212, a first adder 211, a second adder 214, and a first constant multiplier 2
15, a second constant multiplication unit 217, a maximum value detection unit 216, a critical value processing unit 218, and the like.

In FIG. 12, the first delay line 210 and the second delay line 210
The delay line 213 includes delay elements connected in series. In each delay element, data corresponding to an earlier range and data corresponding to a subsequent range based on the output cell 212 are sequentially stored. The data stored in this way are stored in the first adder 211 and the second adder 21 respectively.
It is added at 4. The output of the first adder 211 is multiplied by a predetermined constant value α1 by a first constant multiplier 215,
The second constant multiplication unit 217 multiplies the output of 14 by a predetermined constant value α2.

Here, the constant value α1 and the constant value α2 vary according to the number of cells added through the first adder 211 and the second adder 214 and the maximum data level that can be regarded as a signal for an imaginary target. The maximum value detection unit 216 is the first
After detecting the higher value of the outputs of the constant multiplication unit 215 and the second constant multiplication unit 217, the higher value is applied to the critical value processing unit 218 as the critical value. Threshold processing unit 218 outputs only this as video data when the data of the output cell 212 is greater than the critical value, and outputs the shown female no signal data that there is no target otherwise.

As described above, the range resolution of the conventional video signal processor is limited by the sampling clock frequency allowed by the A / D converter. Also, since cell averaging is performed by a fixed form of hardware,
It is impossible to adjust the number of addition ranges and the constant value to be multiplied adaptively due to the situation that changes every moment. In addition, the cell averaging circuit shown in FIG. 12 performs only one of the cell averaging algorithms. Generally, a radar system changes and uses the cell averaging algorithm according to the situation of the area to be detected. There is a need.

[0014]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a video signal processing device of a radar system capable of performing improved functions.

[0015]

Means for Solving the Problems A video signal processing apparatus of a radar system of the present invention in order to achieve the object, Les
The first record generated by performing clutter removal processing of the radar signal
The radar signal and radar signal
And outputting a second radar signal generated by performing gain control.
A video signal processing device that performs video signal processing of the first radar signal and the second radar signal and outputs target data, a tracking processor and a scan converter that perform predetermined processing based on the target data A first or second analog-to-digital conversion means for receiving the first or second radar signal and performing an analog-to-digital conversion at a predetermined conversion speed with respect to the video signal processing device of the radar system comprising: A radar signal included in a predetermined pulse repetition frequency (PRF) signal among the radar signals digitally converted by the digital conversion means is sequentially written into different memories according to the period of the pulse repetition frequency signal, and then the radar corresponding to the same range gate is used. A first or second direct average value calculating means for averaging and outputting signals; and a microphone A microprocessor configured to download a cell averaging program selected by a main control unit (MPU) of the radar system according to a change in a detection environment and store the program in the RAM memory; A first and second cell averaging unit for performing a cell averaging operation on the outputs of the first and second direct average value calculating means based on the cell averaging execution program, respectively, and an output of the second cell averaging unit Target data extracting means for extracting only target data among them, a radar video processor control means commonly connected to the respective means and the first and second cell averaging processing units and generating a control signal such as the PRF signal, A main controller of the radar system and a radar video processor controller connected to the radar video processor control means. Wherein the cell and a communication processing unit that performs data transmission and reception functions such as average execution program, be configured to include with the.

[0016]

According to the video signal processing apparatus of the radar system according to the present invention, each means constituting the video signal processing apparatus of the radar system operates optimally according to the situation of the area to be detected.

[0017]

Referring to FIG. 1, a video signal processing apparatus for a radar system according to the present invention comprises a first analog-to-digital converter 301, a second analog-to-digital converter 302, and a first analog-to-digital converter 302.
Direct average value calculator 303, second direct average value calculator 30
4. First cell averaging section 305, second cell averaging section 3
06, first buffer memory 307, second buffer memory 309, extractor 308, radar video processor controller 31
0 and the communication processing unit 311, and the output of the first analog-to-digital
The output is transmitted to the direct average calculator 303, and the output of the second analog-to-digital converter 302 is transmitted to the second direct average calculator 304 via the H-bus.

In FIG. 1, a first analog-to-digital converter 301 and a second analog-to-digital converter 302 set a frequency that is a predetermined multiple (for example, twice) of a sampling frequency allowed by an adopted A / D converter chip. The analog-to-digital conversion is performed using the clock. This will be described more specifically with reference to FIGS.

The first direct average value calculator 303 and the second direct average value calculator 304 receive digitally converted data, average the data included in a certain period for each range gate, and output the averaged data. Here, the certain period is a period of several periods of a pulse repetition frequency (PRF) signal, and the number is determined in advance by a user's command or program. Therefore, data received for several periods of the PRF signal is reduced to data that can be received during one period of the PRF signal. The reason for performing such an operation is that the frequency of the PRF signal is high enough to extract more data than data displayed through a normal display unit. The above-described operation of averaging for each range performs a simple data compression, and also performs a function of preventing a target from being erroneously captured due to temporary noise. This will be described more specifically with reference to FIGS.

The first cell averaging unit 305 and the second cell averaging unit 306 perform the cell averaging as described with reference to FIG. 12, and perform the cell averaging through a software program which is not hardware means unlike the related art. Carry out. At this time, the executed software program is downloaded from the main control unit of the radar system to the first and second cell average processing units 305 and 306 through the communication processing unit 311. Therefore, the user of the radar system can change the software program. The extractor 308 removes non-signal data indicating that there is no target from the data output from the second cell averaging unit 306 and applies the same to the second buffer memory 309. This will be described more specifically with reference to FIG.

The radar video processor controller 310 is connected to each circuit included in the radar video processor and performs various control operations. In particular, each circuit variably performs the operations. In addition, it performs the function of generating various clocks and control signals according to the given conditions. Here, various clocks and control signals generated from the radar video processor controller 310 are controlled by a control bus.
s) to each circuit.

The analog-digital converter shown in FIG. 1 will be described below with reference to FIGS. FIG. 3 is a block diagram of the first analog-digital converter and the second analog-digital converter shown in FIG. 1. The first analog-digital converter 301 is a first A / D converter chip ADC1.
And a second A / D converter chip ADC2 and a frequency dividing means 401. The second analog / digital converter 302 includes a third A / D converter chip ADC3 and a fourth A / D converter chip.
It comprises a converter chip ADC4 and frequency dividing means 401. That is, the frequency dividing means 401 of FIG. 3 is commonly used by the first analog-to-digital converter 301 and the second analog-to-digital converter 302.

The frequency dividing means 401 includes a D flip-flop 402, a D flip-flop 403, and an inverter I1. Here, each of the D-flip-flop 402 and the D-flip-flop 403 functions as a frequency divider, and the sampling clock S
-CK and the inverted signal of the sampling clock S-CK are divided. The frequency of the sampling clock S-CK is determined when the first A / D converter chip ADC1, the second A / D converter chip ADC2, the third A / D converter chip ADC3, and the fourth A / D converter chip ADC4 sample. It is twice the frequency of the clock used. That is, the frequency of the sampling clock S-CK is twice the frequency at which the adopted A / D converter chip can perform analog-to-digital conversion. Such a sampling clock S-CK is supplied to the signal 404 through the frequency dividing means 401.
And the signal 405. According to the modulated signal, the first A / D converter chip ADC1 and the third A / D converter chip ADC3 perform the analog-to-digital conversion operation at the edge of the odd pulse of the sampling clock S-CK, and the second A / D converter chip ADC2. In addition, the fourth A / D converter chip ADC4 performs an analog-to-digital conversion operation at the edge of the even pulse of the sampling clock S-CK.
Here, the first A / D converter chip ADC1 and the second A / D
The D converter chip ADC2 alternately transmits its output value through the G-bus, and the third A / D converter chip ADC3
And the fourth A / D converter chip will alternately transmit its output value through the H-bus. FIG. 4 shows these waveforms.

FIG. 5 is a block diagram showing one of the first direct average calculator and the second direct average calculator shown in FIG. 1. The enable signal generator 601 includes a plurality of PRF video FIFO memories. (PRF VIDEO FIFO-1, PRF VIDEO FI
FO-2, PRF VIDEO FIFO-3), average lookup table section 605, buffer 606, multiplexer 607
It is comprised including.

In FIG. 5, the plurality of PRF video first-in-first-out (FIFO) memories are commonly connected on the G-bus or the H-bus, and sequentially transmit radar signals included in one cycle of the pulse repetition frequency PRF signal. It can be stored, and the radar signals will be output according to the stored order. That is, the digitally converted radar signal has one cycle of the PRF signal.
It is stored in PRF VIDEO FIFO-1, and PRF is stored in the next cycle.
Stored in VIDEO FIFO-2, and in the next cycle, PRF VIDE
O Stored in FIFO-3. At this time, the digitally converted radar signal is sequentially written in each PRF VIDEO FIFO according to the range. While the digital radar signal is written in the PRFVIDEO FIFO-3, the radar signal stored in each PRFVIDEO FIFO is read out for each range gate and transmitted to the average look-up table unit 605. Enable signal generator 6
01 is the PRF VIDEO FIFO-1, PRF VIDEO FIFO-2,
In order for the PRF VIDEO FIFO-3 to operate as described above, a plurality of write clock signals to be applied to each PRF VIDEO FIFO are generated. The enable signal generator 601 will be described more specifically with reference to FIG.

The average look-up table unit 605 stores an average value of the divided addresses after dividing the address by a predetermined number of bits, and outputs the average value as soon as the address is applied. For example, the address of the average look-up table section 605 is composed of 12 bits, and the PRF VIDEO FIFO-1, PRF VIDEO FIFO-2, PR
When the output of the F VIDEO FIFO-3 is composed of 4 bits, the value stored in the address 110110001111 is 1100. That is, [(1101)
₂ + (1000) ₂ + (1111) _2] / 3 = [(10
0100) ₂ ] / 3 = (1100) _2, so (110
0) ₂ is stored in the average look-up table unit 605 as an average value of addresses. When the average value is calculated using the look-up table method, the average value is calculated within a very short time.

Here, the radar system usually uses PRF signals of various frequencies in order to improve the detection capability.
As described above, the reason for making the frequency of the PRF signal different is as follows.
If the frequency of the PRF signal is different, a return signal to the true target always appears, while
This is because an echo signal to an imaginary target due to clutter, noise, or the like sometimes appears or does not appear, so that it is possible to determine that an echo signal that always appears is a signal that has bounced back from a true target. At this time, the frequency of the sampling clock also changes depending on the frequency of the PRF signal, which causes the PRF VIDEO FIFO-1, PRF VIDEO FIFO-2, PR
The frequencies of the first write clock WR-CK1, the second write clock WR-CK2, and the third write clock WR-CK3 applied to the F VIDEO FIFO-3 and the like also change. If the frequency of the PRF signal is very low, the
PRF VIDEO FIFO-1, PRF VIDEO FIFO-2, PRF VIDEO
The calculation of the average value by the FIFO-3 or the like is not performed, and the calculation of the average value is performed directly only when the frequency of the PRF signal is high.

In FIG. 5, the multiplexer 607 is connected to the G-
Buffer 60 connected to the bus or H-bus.
6, the output of the first analog-to-digital converter or the output of the second analog-to-digital converter which is connected to the output terminal of the average look-up table unit 605 and transmitted through a G-bus or an H-bus according to the frequency of the PRF signal. Or the output of the buffer 606 is selected. FIG. 6 is a waveform diagram for explaining the operation of the direct average value calculating means shown in FIG. In FIG. 6, the -DPRF signal is substantially the same as the -PRF signal, which is a negative PRF signal. That is, the -PRF signal is a negative PRF signal to which noise and the like are attached during transmission,
The DPRF signal is a negative PRF signal that has undergone noise removal processing by the video signal processing unit.

In FIG. 6, / WE1, / WE2, and / WE3 are the PRF VIDEO FIFO-1, PRF VIDEO FIFO-2, and PRF VI.
This is a write enable signal that becomes active during the period when data is written in DEO FIFO-3. At this time, each write enable signal is AND-operated with the write clock WR-CK applied from the radar video processor control unit 310, and PRF VIDEO FIFO-1, PR
It is applied to each write terminal / WR of F VIDEO FIFO-2 and PRF VIDEO FIFO-3. On the other hand, PRF VIDEO FIFO-1, PR
The RD-CK shown in FIG. 6 is applied to each read terminal / RD of the F VIDEO FIFO-2 and the PRF VIDEO FIFO-3 and the write terminal / WR of the buffer 606. RD-CK is PRF
When the third write clock WR-CK3 applied to the write terminal of VIDEO FIFO-3 is delayed by several clock cycles, the resulting signal has the same form. Therefore, the first and second radar signals are PRF VIDEO FIFO-
When a few clocks have passed since the data was stored in No. 3, the average value by the range gate was calculated and applied to the buffer 606.

FIG. 7 is a block diagram of the enable signal generator shown in FIG. 5, and includes a PRF level comparator 801, an inverter I2, a D flip-flop 802, a D flip-flop 803, and three OR gates OR1, OR2. , O
R3, AND gate AND, and inverter I3 are included. Referring to FIG. 7, a PRF level comparator 801 receives a positive PRF signal + PRF and a negative PRF signal -PRF, which may include noise, and compares the level difference between the two input signals with a predetermined value to obtain a digital PRF signal.
It outputs DPRF, which is an RF signal.

FIG. 8 is a waveform diagram for explaining the function of the PRF level comparator 801. + PRF and -P
The RF signal is a signal containing noise and the like, and FIG. 8B shows the + PRF and -PRF signals without noise and the + PRF and -PRF signals with noise. As shown in FIG. 8B, if a signal containing noise is used as it is, an error occurs. Therefore, the noise must be removed. The basic principle of noise removal is that a signal below a certain level is regarded as noise and output to level "0", and a signal other than that is regarded as non-noise and level "1".
Output to At this time, by comparing the difference voltage between the + PRF signal and the −PRF signal with a predetermined voltage, the margin for determination can be further widened.

In FIG. 7, the second inverter I2 is connected to the PRF
The DPRF signal output from the level comparator 801 is inverted and applied to the clock terminals of the D-flip-flop 802 and D-flip-flop 803. D-flip-flop 802, D-flip-flop 803,
The AND gate and the inverter I3 are components for sequentially generating the write enable signals / WE1, / WE2, and / WE3, which are signals that are enabled every period of the PRF signal. Looking at these operations, it is as follows. First, the D-flip-flop 802 delays the signal applied to the D-input terminal of the D-flip-flop 802 by one cycle of the pulse output from the inverter 12 and outputs the delayed signal. That is, the D-flip-flop 802 performs a function of delaying the signal applied to the input terminal by one period of the PRF signal. D-flip-flop 8
Numeral 03 delays the output of the D-flip-flop 802 for one cycle of the output pulse of the inverter I2 and outputs it. Each negative output / Q of D-flip-flop 802 and D-flip-flop 803 is connected to AND gate AN.
After being ANDed through D, it is applied again to the input terminal D of the D-flip-flop 802. Inverter I3 inverts the output of AND gate AND.

Here, the output of the inverter I3 is the first
The write enable signal / WE1 becomes the negative output of the D-flip-flop 802, the second write enable signal / WE2, and the negative output of the D-flip-flop 803 becomes the third write enable signal / WE3.

Write enable signal / WE1, / WE
2, / WE3 are three OR gates OR1, O, respectively.
ORed with the write clock WR-CK through R2 and OR3, the first write clock WR-CK1, the second write clock WR-CK2, and the third write clock W
Converted to R-CK3.

FIG. 9 is a block diagram of the first cell averaging processor or the second cell averaging processor shown in FIG. 1, which is a one-chip microprocessor 1001 and a cell averaging video RAM 10.
02 etc. are included.

The cell averaging unit executes an algorithm for suppressing imaginary target detection due to impulsive noise that may be included in a specific range. In other words, an algorithm for keeping the imaginary target detection rate below a predetermined value despite such noise is performed. As described with reference to FIG. 2, there are various methods for performing the cell averaging, and it is advantageous to be able to change each time according to the environment of the radar system in order to improve the detection capability of the radar system.

In FIG. 9, the one-chip microprocessor 1001 stores the radar signal output from the multiplexer 607 in the cell average video RAM 1002.
The one-chip microprocessor 1001 is configured to include a nonvolatile memory RAM inside. The RAM included in the one-chip microprocessor 1001 is used as a work area when an execution program is downloaded and an operation is performed. At this time, the cell average video R
AM1002 and one-chip microprocessor 100
Transmission and reception of data between the devices 1 are performed through a data bus and an address bus, and control of each bus is performed by a one-chip microprocessor 1001. FIG. 10 is a detailed block diagram of the extractor shown in FIG.
01, target data latch means 1102, range counter 1103 and the like.

Referring to FIG.
Reference numeral 1 denotes a unit for inspecting the output of the cell averaging unit bit by bit to determine the presence or absence of a target, and is basically a logical OR gate for performing logical OR. This will be specifically described as follows.

Assuming that the output of the cell averaging unit consists of 4 bits, if there is no target, the output is 0000, otherwise "1" appears in at least one or more bit positions. Therefore, the target presence / absence determining means 1
Reference numeral 101 denotes a target data latch unit 11 which is activated when the output of the cell averaging unit is not 0000 (in FIG. 10, it is "low" active).
02.

The range counter 1103 has a function of generating a range gate value of the data output from the cell averaging unit, and is composed of a general counter.

On the other hand, the target data latch means 1102
One of the latch means is connected to the output of the cell averaging unit, and the input terminal of the other latch means is connected to the output of the range counter 1103. doing. Here, each latch means is constituted by a first-in-first-out buffer FIFO. The reason that the latch means is constituted by the first-in-first-out buffer is that the processing speed of the cell averaging unit and the processing speed of the tracking processor are different. .

At this time, the latch enable signal of each latch means is at least one of the output data of the cell averaging processor.
When "1" appears at the above bit position, it becomes active. Therefore, when the output data of the cell averaging unit is regarded as the target data, the two latch units 1104 and 1105 output the output data of the cell averaging unit. The range gate value corresponding to the output data is latched. Therefore, data deemed non-target is deleted. PR of Figure 10
SP-WRITE-CK is a clock signal used when the cell averaging unit outputs data, and the range counter 1103 counts this.

[0043]

As described above, the video signal processor of the radar system according to the present invention performs its operation variably according to the environment of the radar system, and improves the detection capability of the radar system. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal processing device of a radar system according to the present invention.

FIG. 2 is a block diagram of a general radar system to which the present invention and conventional techniques can be applied.

3 is a detailed block diagram of a first analog-digital converter and a second analog-digital converter shown in FIG.

FIG. 4 is a waveform diagram of input / output signals of the clock frequency dividing means shown in FIG.

5 is a block diagram of a first direct average value calculator or a second direct average value calculator shown in FIG. 1. FIG.

FIG. 6 is a waveform diagram of input / output signals of each component shown in FIG.

7 is a detailed block diagram of an enable signal generator of FIG.

8 is a waveform diagram of input / output signals of the PRF-level comparator shown in FIG.

9 is a detailed block diagram of a first cell average processing unit or a second cell average processing unit shown in FIG.

FIG. 10 is a detailed block diagram of the extractor shown in FIG.

FIG. 11 is a block diagram of a video signal processing device of a conventional radar system.

12 is a detailed block diagram of the cell averaging circuit shown in FIG.

Continuation of the front page (56) Reference JP-A-3-102279 (JP, A) JP-A-3-197889 (JP, A) JP-A 64-18083 (JP, A) JP-A 2-16479 (JP , A) JP-A-2-226083 (JP, A) JP-A-3-82976 (JP, A) JP-A-4-54481 (JP, A) Sekine Matsuo, "Radar signal processing technology", electronic information The Telecommunications Society, first edition issued on September 20, 1991, p. 96-P. 157

Claims (14)

(57) [Claims] 1. A method for removing clutter from a radar signal
First radar signal to be generated and clutter removal of radar signal
The second ray generated by performing the
And a video signal processing device that performs video signal processing on the first radar signal and the second radar signal and outputs target data, and tracking that performs predetermined processing based on the target data. A video signal processing apparatus for a radar system, comprising: a processor and a scan converter, wherein the first or second analog-digital receiving the first or second radar signal and performing analog-to-digital conversion at a predetermined conversion speed Converting means for writing the radar signals included in a predetermined pulse repetition frequency (PRF) signal among the radar signals digitally converted by the analog-to-digital conversion means into different memories sequentially according to the period of the pulse repetition frequency signal; First or second direct average calculation for averaging radar signals corresponding to the same range gate and outputting Output means, a microprocessor and a RAM memory, and downloads the cell averaging program selected by the main control unit of the radar system, and downloads the RA.
After being stored in the M memory, the first processor is controlled based on the cell averaging program under the control of the microprocessor.
A first and a second cell averaging unit for performing a cell averaging operation on the output of the second direct averaging unit, and a target data extracting unit for extracting only target data from the output of the second cell averaging unit; A radar video processor control means commonly connected to the respective means and the first and second cell averaging sections for generating a control signal such as the PRF signal; and a radar video processor control means connected to the radar video processor control means. A video signal processing device, comprising: a communication processing unit that performs a data transmission / reception function such as a cell averaging program between a main control unit and the radar video processor control unit. 2. The video signal processing apparatus according to claim 1, further comprising a first buffer memory for storing the output of the first cell averaging unit and outputting the output upon request of a scan converter. 3. The video signal processing apparatus according to claim 1, further comprising a second buffer memory for storing the output of the extracting means and outputting the output at the request of the tracking processor. 4. The first analog-to-digital converter includes a first sampling clock divider that divides the sampling clock by two, and two first A / Ds that operate at different edges of the divided sampling clock. A first A / D converter and a second A / D converter. The output signal is transmitted for each sampling clock through a G-bus commonly connected to the output terminals of the first A / D converter and the second A / D converter. 2. The video signal processing apparatus according to claim 1, wherein: 5. The second analog-to-digital converter includes a second sampling clock divider that divides the sampling clock by two, and two third A / Ds that operate on different edges of the divided sampling clock. A third A / D converter and a fourth A / D converter. The output signal is transmitted for each sampling clock through an H-bus commonly connected to the output terminals of the third A / D converter and the fourth A / D converter. 2. The video signal processing apparatus according to claim 1, wherein: 6. The first direct average value calculating means, which is commonly connected to the G-bus, can sequentially store radar signals included in one cycle of a pulse repetition frequency (PRF) signal, and according to the stored order. A predetermined number of first Ps that output radar signals
RF video first-in first-out (FIFO) memory means;
An RF signal is input, and a plurality of write clock signals that are enabled in each period are sequentially generated to generate the first write clock signal.
A first enable signal generating means for applying to the PRF video FIFO memory means, and an average value for an address divided in a predetermined bit unit for storing the first enable signal;
2. The video signal processing apparatus according to claim 1, further comprising first average look-up table means to which data output from the O memory means for each range gate is applied as an address. 7. The first direct average value calculating means is connected to the output terminal of the first average look-up table through a buffer at the same time as being connected to the G-bus, and based on the frequency of the PRF signal. 7. The video signal processing apparatus according to claim 6, further comprising a first multiplexer for selectively outputting an output of the first analog-to-digital converter or an output of the first average look-up table transmitted through the first multiplexer. 8. The second direct average value calculating means, which is commonly connected to the H-bus, can sequentially store radar signals included in one cycle of a pulse repetition frequency (PRF) signal, and according to the stored order. A predetermined number of second Ps that output radar signals
RF video first-in first-out (FIFO) memory means;
An RF signal is input, and a plurality of write clock signals that are enabled in each cycle are sequentially generated to generate the second write clock signal.
A second enable signal generating means for applying to the PRF video FIFO memory means, and a second PRF video FIFO storing an average value for an address divided in a predetermined bit unit;
2. The video signal processing apparatus according to claim 1, further comprising: a second average lookup table to which data output from the O memory means for each range gate is applied as an address. 9. The second direct average value calculation means is connected to the output terminal of the second average look-up table through a buffer at the same time as being connected to the H-bus, and is connected to the H-bus based on the frequency of the PRF signal. 9. The video signal processing apparatus according to claim 8, further comprising a second multiplexer for selectively outputting an output of the second analog-to-digital converter or an output of the second average look-up table transmitted through the second multiplexer. 10. A first enable signal generating means, comprising: a positive PRF signal and a negative PR signal which may include noise;
A PRF that receives an F signal, compares the level difference value with a predetermined level value, and outputs a digital PRF signal.
A level comparator; first inverting means for inverting the output of the PRF level comparator;
A first D-flip-flop that delays one cycle of the output pulse of the inverting means, and a second D-flip-flop that delays the output of the first D-flip-flop by one cycle of the output pulse of the first inverting means
AND gate means for ANDing the flip-flop, the negative output of the first D-flip-flop and the negative output of the second D-flip-flop, and applying this to the D-input terminal of the first D-flip-flop; Second inverting means for inverting the output of the AND gate means, wherein the output of the second inverting means, the negative output of the first D-flip-flop and the negative output of the second D-flip-flop are the first and the second, respectively. 7. The video signal processing apparatus according to claim 6, wherein the second and third enable signals are applied to the write enable terminals of the plurality of PRF video FIFO memory means. 11. The first enable signal generating means performs an OR operation on the first, second, and third enable signals and a write clock that can be applied to the radar video processor control means, and performs first, second, and First OR gate means for applying a third write signal to write clock terminals of a plurality of PRF video FIFO memory means after generating the third write signal;
The video signal processing device according to claim 10, further comprising a second logical sum gate means and a third logical sum gate means. 12. The second enable signal generating means includes a positive PRF signal and a negative PR signal which may contain noise.
A PRF that receives an F signal, compares the level difference value with a predetermined level value, and outputs a digital PRF signal.
A level comparator; first inverting means for inverting the output of the PRF level comparator;
A first D-flip-flop that delays one cycle of the output pulse of the inverting means, and a second D-flip-flop that delays the output of the first D-flip-flop by one cycle of the output pulse of the first inverting means
AND gate means for ANDing the flip-flop, the negative output of the first D-flip-flop and the negative output of the second D-flip-flop, and applying this to the D-input terminal of the first D-flip-flop; Second inverting means for inverting the output of the AND gate means, wherein the output of the second inverting means, the negative output of the first D-flip-flop and the negative output of the second D-flip-flop are the first and the second, respectively. 9. The video signal processing apparatus according to claim 8, wherein the second and third enable signals are applied to the write enable terminals of the plurality of PRF video FIFO memory means. 13. The second enable signal generating means logically ORs the first, second, and third enable signals with a write clock that can be applied to the radar video processor control means, and performs first, second, First OR gate means for applying a third write signal to write clock terminals of a plurality of PRF video FIFO memory means after generating the third write signal;
13. The video signal processing device according to claim 12, further comprising a second logical sum gate means and a third logical sum gate means. 14. An extraction means for examining the output of the second cell averaging unit in bit units and generating a signal indicating presence / absence of a target, and a second presence / absence determination means based on an output signal of the target presence / absence determination means. First latching the output of the cell averaging unit
Latching means, range counting means for generating a range gate value of data output by the second cell averaging processing section, and second latching means for latching the output of the range counting means based on an output signal of the target presence / absence determining means. The video signal processing device according to claim 1.