JPH0433062B2 - - Google Patents

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (Fig. 1) Working example (a) Portable example Explanation of the terminal (Fig. 2, Fig. 3, Fig. 4) (b) Explanation of the internal configuration of the embodiment device (Fig. 5, Fig. 6) (c) Explanation of the operation of the embodiment configuration (Fig. 7) , FIG. 8) Effects of the Invention [Summary] This is a system for dynamically checking diagnostics of any area of a memory space including a port section that can be accessed by a processor. and a display section for displaying the contents of the memory space, so that the processor can repeatedly read a specified area of the memory space and display it on the display section, thereby dynamically diagnosing any area of the memory space including the port section. This is what I did.

[Industrial Application Field] The present invention relates to a dynamic memory space check method for dynamically diagnostically checking a memory space that can be accessed by a processor. The present invention relates to a dynamic check method of a memory space in which an operator performs a check by displaying the contents of that area on a display unit.

A processor, which is a data processing unit, requires a certain amount of memory space to perform processing.

This kind of memory space consists of a hard board for connecting I/O (input/output unit), data storage RAM (random access memory), program storage ROM (read only memory), etc. The processor accesses the memory space as necessary and exchanges data between I/O, RAM and ROM.

[Conventional technology]

If such memory space is destroyed, the processor will not be able to continue processing, so it is necessary to check the memory space.

Conventionally, this check has been performed by specifying an arbitrary address in the memory space using a key, performing a read operation, and displaying the contents on a display section for the operator to visually check.

This display content was the one at the time it was read out, and did not change after being read out.

[Problem that the invention seeks to solve]

However, in the conventional method, there was a problem in that after a read operation, if the contents of the address were changed by some operation, the read operation had to be performed again in order to check whether the change had occurred. . In particular, in the port section of the memory space, data and instructions are given from the outside to check whether they are operating normally according to instructions and data from the outside, and are not normally displayed on the display section, so it takes two seconds to check. A problem has arisen in that this operation requires multiple read operations, and this operation requires the number of ports.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic check method for a memory space that can check a memory space including a port section with a single read operation.

[Means for solving problems] FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 1 is a processor (hereinafter referred to as CPU)
, which reads a memory space according to a specified area from an area specifying section to be described later, 2 is a memory space, and a port section that can be accessed by the CPU 1;
3 is a designation section which is composed of, for example, a key input unit and is used for mode instruction and address (data) input; and 5 is a display section. 4 is a bus for displaying specified contents, and is used to connect these to exchange data and commands.

That is, the present invention includes a processor 1, a memory space 2 including a port section that can be accessed by the processor 1, and a specifying section 3 for checking the memory space 2 and specifying an area of the memory space 2 to be checked. , a display section 5, and the processor 1 has:
When a check of the memory space 2 is specified by the specifying unit 5, a check mode is executed, and the specified area of the memory space 2 is repeatedly read out until the check mode is canceled, and the display unit 5 At the same time, by rewriting the contents of the specified area during the check mode, the contents of the specified area before and after rewriting can be displayed on the display section 5 through the repeated reading. It is characterized by displaying.

[Effect]

The mode instruction (hereinafter referred to as memory set mode instruction) and area (address) from the specifying section 3 are transferred to the bus 4.
When it is given to CPU1 as shown in a in the figure,
The CPU 1 accesses and reads out the address in the memory space 2 as shown in b in the figure, and provides it to the display section 5 via the bus 4 as shown in c in the figure. The CPU 1 repeats this operation until the memory set mode instruction is released. Therefore, when the address in the memory space related to this period is rewritten, the contents before and after the rewriting are displayed on the display section 5, so that the operation of the memory space can be visually checked by the operator. , and the read operation for that purpose only needs to be done once.

〔Example〕

(a) Description of a portable terminal as an example.

FIG. 2 is an external view of a data input device according to an embodiment of the present invention, showing a portable terminal, and FIG. 3 is an explanatory diagram of an example of use of the data input device configured in FIG. 2.

In the figure, PT is a handheld terminal,
It is held in the hand of an operator to perform operations such as data input, and as the internal configuration will be described later in FIG. BD is the main body, SW is the power switch, which is installed on the top of the main body BD to turn on/off the power, and 3 is the key as the designated part. It has 7 rows and 5 columns of keys, and is provided with numeric keys "0" to "9", an input instruction key "ENTER", and other necessary alphanumeric keys and function keys.
General data is entered using the numeric keypad and alphanumeric keys, and functions (processing details) are entered using the "ENTER" key and function keys. 5 is the display, which is composed of a liquid crystal display.
A connector 8 is provided on the top of the main body BD to display input data, etc., and is provided on the side of the main body BD to connect with external equipment such as a communication unit or printer unit to exchange data and commands. This will be described later with reference to FIG. 4A.

In FIG. 3, CIU is a communication interface unit, which has a housing section for housing the handheld terminal PT, and a connector 9 connected to the connector 8 of the handheld terminal PT at the bottom.
(described later in FIG. 4B), and when the handheld terminal PT is housed in the housing part as shown in FIG. 3, the connectors 8 and 9 are connected, and the input data in the memory 2 of the handheld terminal PT is is sent to the host computer.

To explain an example of how such a handheld terminal PT is used, an operator holds the handheld terminal PT in his hand at a business partner (supermarket, etc.) and while checking the product, inputs the product type, quantity, etc. by operating the key part 3. and confirm the input data on the display 5. The input data is
Processed by CPU 1 and stored in memory 2.

Then, the operator connects the handheld terminal PT to, for example, a printer device (not shown) loaded in the vehicle, issues a slip, and hands it to the business partner. Furthermore, when the user returns to his/her office, the handheld terminal PT is connected to the communication interface unit CIU installed in the office, and the input data is sent to the host computer for purposes such as sales aggregation.

Figure 4 shows these handheld terminals PT.
FIG. 2 is a configuration diagram of connectors 8 and 9 provided in the communication interface unit CIU.

In FIG. 4A, 80a and 80b are guide holes for receiving alignment studs, which will be described later, on the other connector 9 provided on the communication interface unit CIU, and 81a to 81d are holes for lead terminals. 82 is an optical connection part, which receives the signal line pins (to be described later) of the other connector 9, respectively, and makes an electrical connection of the signal line, and includes three light emitting elements (light emitting diodes) 83,
It is composed of six light-receiving elements (phototransistors) 84, and exchanges signals by optical coupling while facing the six light-emitting elements and three light-receiving elements of the other connector 9, which will be described later. 85 is a connector support part. Guide holes 80a and 80b, lead terminal holes 81a to 81d, and an optical connection section 82 are provided.

In FIG. 4B, 90a and 90b are positioning studs, and guide holes 80a and 80 of one connector 8 provided in the handheld terminal PT.
91a to 91d are signal line pins that are inserted into the lead terminal holes 81a to 81d of one connector 8, and are inserted into the lead terminal holes 81a to 81d of one connector 8. 92 is an optical connection part that electrically connects the signal line, and is composed of six light emitting elements (light emitting diodes) 93 and three light receiving elements (phototransistors) 94, and is connected to one connector 8. 95 is a connector support part, which faces the six light receiving elements 84 and three light emitting elements 83 of one connector 8 and exchanges signals by optical coupling. , signal line pin 9
1a to 91d, and an optical connection section 92 are provided.

To connect the connectors 8 and 9, insert the handheld terminal PT into the slot of the communication interface unit CIU so that the alignment studs 90a/90b of the connector 9 are inserted into the guide holes 80a, 80b of the connector 8. do.

As a result, the signal line pin 91a of the connector 9
~91d is the lead terminal hole 81a of the connector 8~
81d, an electrical connection is made, and the optical connection part 92 of the connector 9 and the optical connection part 82 of the connector 8 face each other, and the light emitting element 93 connects to the light receiving element 84, and the light receiving element 94 connects to the light emitting element 81d. Opposing the element 83, optical coupling is possible.

In connectors using such optical coupling, signal lines for power supply, connection detection, and signal ground that are unsuitable for optical coupling are connected to the signal line pin 91.
This is done by electrically connecting a to 91d and the lead terminal holes 81a to 81d. On the other hand, data lines, clock lines, etc. that can be optically coupled are optically coupled between optical connections 92 and 82. Compared to electrical connections made by mechanical connections, connections made by optical coupling are more reliable because there is no need to consider connection failures due to wear and deterioration of the pins, and they are electrically isolated and do not expose the terminals. This prevents damage to internal circuits caused by static electricity.

(b) Explanation of the internal configuration of the example device.

FIG. 5 is an internal block diagram of one embodiment of the present invention.

In the figure, the same parts as shown in Figs. 1, 2, and 4 are indicated by the same symbols, and 4a is an address bus, which is a part of the bus 4 and handles the exchange of addresses. 4b is a data bus which is part of the bus 4 and is used to exchange commands; 6 is a buzzer which issues a warning; 7 is a display controller; 5 is for double-sided control, 10 is an interface circuit for transmitting and receiving with external equipment via the connector 8 using the RS-232c interface procedure, and 11 is a battery, which has an operating voltage Vcc inside the device. When connected to the communication unit CIU, pin 91 of the connector 9 is connected to the power supply of the communication unit CIU.
Charging voltage BV is applied from connector 8 through pin 91d of connector 9 during charging, and operating voltage Vcc is applied to each part from the power supply through pin 91d of connector 9.
is given. 20, 21, 22, 2
3 and 24 are port sections, which are composed of input/output registers and constitute part of the memory space 2; the port section 20 is connected to the buzzer 6 and the display controller 7;
The port section 21 is for the key section 3, and the port section 22 is for the interface circuit 10.
The port section 23 is for the reception (RD line) of the interface circuit 10, and the port section 24 is for the control line of the interface circuit 10 (terminal ready line ER, transmission request line RS). , reception timing line DR, transmission permission line CS, carrier detect line CD). 25 is a display buffer, 26 is a data memory, and 27 is a program memory, which constitutes the other part of the memory space 2. The display buffer (hereinafter referred to as buffer) 25 stores data to be displayed. Memory for storing data (hereinafter referred to as RAM)
26 is a memory for storing input data and necessary programs, a program memory (hereinafter referred to as
A ROM (referred to as ROM) 27 stores programs necessary for the operation of the CPU 1.

The basic operation of a data input device with such a configuration is as follows:
The CPU 1 reads the input contents of the key section 3 from the address bus 24a through the data bus 4b via the port section 21, decodes the input contents, and processes (for example,
If arithmetic processing such as addition/subtraction, multiplication, division, etc. or search processing) is instructed, the instructed processing is executed, and if it is general data, the data related to the display buffer 25 and RAM 26 is transferred via the address bus 4a. It is supplied via bus 4b and stored. Also, the display controller 7 is connected via the port 20.
In the DMA mode, the display buffer 25 is accessed via the address bus 4a, and display data is received from the data bus 4b and displayed on the display 5. These programs are read and executed by the CPU 1 from the ROM 27. Also, in transmit/receive mode,
CPU1 connects to ports 22 and 2 from address bus 4a.
3 or 24, commands and data are exchanged with the interface circuit 10, and transmission/reception operations are performed with the outside via the connector 8.

In such a configuration, as shown in FIG.
The memory space 2 is composed of port sections 20 to 24, a buffer 25, a RAM 26, and a ROM 27,
Addresses from “0000” to “FFFF” are assigned.

(c) Description of the operation of the example configuration.

FIG. 7 is a process flow diagram of the memory set mode in the configuration shown in FIG. 5, and FIG. 8 is an explanatory diagram of an example of display on the display section 5 by such processing.

First, to instruct memory set mode,
The operator presses a specific key on the key section 3. For example, press both the "0" and "3" keys on the numeric keypad and press the power switch SW.
When turned on, CPU1 uses address bus 4a.
The pressed content of the key unit 3 is detected from the data bus 4b via the port unit 21, and determined to be a memory set mode activation designation.

Next, the operator inputs the address of the area to be read using the key section 3. The CPU 1 thereby first stores the input address in the display buffer 25, and displays it on the display section 5 by the display controller 7 as shown in FIG. 8A. That is, the memory set mode "M" and the input address "n ₁ n ₂ n ₃ n ₄ " are displayed.

Next, the CPU 1 starts from the specified address in the memory space 2 and reads out an 8-byte area from that address to the display buffer 25.

As a result, the display controller 7 reads out the contents of the display buffer 25 and displays them as shown in FIG. 8B.

Next, the CPU 1 detects whether or not the key section 3 is pressed from the port section 21 via the address bus 4a, and if not, returns to step.

When it is detected that key part 3 is pressed, CPU1
checks whether the pressed key is an address change key, and if it is an address change key, returns to step.

If it is not an address change key, it is checked whether it is a mode end key, and if it is not a mode end key, input data is written to the designated address via the data bus 4b as a data key, and the process returns to step.

Conversely, if the mode end key is pressed, the memory set mode is ended. In this way, for example, when you want to check the port section, specify the address assigned to the port section, read and display it as shown in FIG. This is read out and displayed again by the CPU 1, so that the operator can visually check whether the rewriting has been completed normally. For example, in Figure 8C, the 8th
This shows that "e" in Figure B has been replaced with "d".

Similarly, by operating an external device during the memory set mode to rewrite the contents of the port sections 23 or 24 via the interface circuit 10, the rewritten contents of these port sections are displayed for checking.

Also, when checking and modifying the program in the RAM 26, it is possible to rewrite and check the program in the same manner.

By repeating steps in this manner, a display check for replacing the contents of the specified area can be performed by one reading operation (address setting).

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the contents of an arbitrary area in the memory space are repeatedly read out in a single read operation, and the contents of the area are rewritten for checking. Both of the replaced areas are displayed, thereby making it possible to check the relevant area with a single operation and also by visual inspection by the operator. Therefore, especially the hard port section, CPU operation,
In addition to being able to check RAM, it is also possible to check for program changes in RAM.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an external view of an embodiment of the device of the present invention, Fig. 3 is an explanatory diagram of an example of use of the embodiment of Fig. 2, and Fig. 4 is an embodiment of the embodiment of Fig. 2. 5 is an internal configuration block diagram of the embodiment in FIG. 2, FIG. 6 is a memory space configuration diagram in the block in FIG. 5, and FIG. 7 is a processing flow of an embodiment of the configuration in FIG. FIG. 8 is an explanatory diagram of a display example according to the processing flow shown in FIG. 7. In the figure, 1...processor, 2...memory space, 3...
Designation section, 5...Display section, 20-24...Port section.

Claims (1)

[Scope of Claims] 1. A processor, a memory space including a port section that can be accessed by the processor, a designation section for checking the memory space and designating an area of the memory space to be checked, and a display section. and when the processor is instructed to check the memory space by the specifying unit, the processor executes a check mode and repeatedly reads the specified area of the memory space until the check mode is released. By rewriting the contents of the specified area during the check mode, the display section displays the contents of the specified area before and after the rewriting through the repeated reading. A dynamic check method for a memory space characterized by displaying the contents.