JPH0435733B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a matrix type liquid crystal display device.
In particular, the present invention relates to the structure of a drive circuit section of a matrix type liquid crystal display device in which an addressing switching transistor is added to each picture element in a matrix type display pattern.

<Prior art> Matrix-type liquid crystal display devices that use nonlinear elements to drive liquid crystal display include address thin film transistors (hereinafter referred to as
Abbreviated as TFT. ) in a matrix, it is possible to obtain a high-contrast display equivalent to static drive even when performing multiplex drive with a small duty ratio, i.e., multiple lines.
TFT active matrix type liquid crystal display devices are known.

Some driving systems for this TFT active matrix type liquid crystal display device have circuit configurations and signal waveforms as shown in FIGS. 5 and 6. In the figure, 11 is a liquid crystal display panel, and a TFT 11c is connected to the intersection of a row electrode 11a and a column electrode 11b as shown in the figure. 11d is the capacitance of the liquid crystal layer. 12 is a row electrode driver mainly consisting of a shift register;
The scanning pulse S is sequentially shifted by the clock φ1 from the gate signal control section 13 and output to each row electrode. When the total scanning period of this row electrode is T and the number of scanning lines is N, the scanning period H is expressed as H=T/N. A pulse voltage having a pulse width equal to this scanning period H is sequentially applied to each row electrode so as to turn on the TFT 11c row by row. Reference numeral 14 denotes a column electrode driver, which has a drive method that samples and holds (SH) data directly to the display panel (hereinafter referred to as panel SH drive method), and a drive method that provides the column electrode driver with the function of sample and hold data (hereinafter referred to as “panel SH drive method”). (referred to as the driver SH drive system). As shown in FIG. 7, the panel SH drive type column electrode driver consists of a shift register 31, a sampling switch 32, etc., and clocks data serially sent from the data signal control section 15 at timings corresponding to each column. It is sampled in synchronization with φ2, outputted to the column electrodes sequentially, and written to the liquid crystal layer through the TFT 11c. In this driving method, data sampling and writing into the liquid crystal layer through the TFT 11c are performed within the same horizontal scanning period. Next, using Figures 8 and 9,
The SH drive method will be explained. In synchronization with the output of the shift register 41, the sampling switch 42
is turned on, and a charge corresponding to the data signal is stored in the capacitor 43. Then, a discharge pulse signal located in the first half of the horizontal blanking period is applied to Ce to discharge the remaining charge and form the reference state. Next, when a transfer pulse signal located in the latter half of the horizontal blanking period is applied to Cg,
The charge stored in the capacitor 43 is transferred to the transistor 44 and output. With this drive method, data is written to the liquid crystal in the next 1H after sampling.

When the row electrodes are taken out from the liquid crystal display panel, they are all taken out at one end as shown in FIG. A possible method is to divide the row electrodes into left and right row electrodes and take them out alternately. When row electrodes are taken out at both the left and right ends, the signals applied to the row electrodes must be alternated left and right in time, so if the row electrode driver is placed on one side, it will be difficult to route the wiring for connection to the liquid crystal display panel. This increases the length and causes problems such as wiring crossing, which increases the wiring area or requires wiring using through-holes, which poses problems in terms of miniaturization and reliability. In addition, when row electrode drivers are placed on both the left and right sides, one takes out the output of the odd-numbered shift register, and the other takes out the output of the even-numbered shift register, so only half of the total number of stages is used. However, there are problems in terms of miniaturization and power consumption. Furthermore, a start pulse signal and a clock signal are required for operating the shift registers on the left and right sides, respectively, leading to an increase in the number of input signals.

<Object of the Invention> The present invention has been made in view of the above-mentioned problems in conventional drive circuits for matrix-type liquid crystal display devices, and is novel and useful as it consumes less power and can be easily miniaturized and highly integrated. It is an object of the present invention to provide a structure of a drive circuit section of a liquid crystal display device.

<Basic Principles and Examples> Hereinafter, examples will be described in which the drive circuit section of the liquid crystal display device according to the present invention is applied to a liquid crystal television.

FIG. 1 shows a circuit diagram of a row electrode driver that can be used whether the row electrodes of a liquid crystal display panel are taken out on one side or on both the left and right sides, consumes less power, and can be easily integrated. If the row electrode of the liquid crystal display panel is taken out on one side, set the R/ terminal to "1",
B/ terminal to “0”, H _2/1 terminal _to “1”, D/
Set the P terminal to “0” and the terminal to “1”.
When the row electrodes are taken out from one side, in order to perform line sequential driving, a scanning pulse must be supplied to the scanning electrodes from the output terminal of the scanning circuit every sequential scanning period. The timing waveform in that case is shown in FIG. A start pulse signal SP with a width of 4H (Fig. 2A) and a clock signal CL with a period of 1H (Fig. 2B) are input to the flip-flop 61, and the output signal Q
(FIG. 2C) is selected by the clocked inverter 64 and input to the data terminal of the shift register 78. This shift register 78 shifts half bits at a time. On the other hand, the inverted output Q of the flip-flop 61 and the start pulse signal SP are connected to a NAND circuit 67.
After processing the output signal, the clocked inverter 69 selects the output signal and inputs it to the reset terminal of the flip-flop 71 (FIG. 2D). The flip-flop 71 is triggered by the falling edge of the clock signal CL (FIG. 2B), and the clocked inverter 74 selects a signal whose frequency is divided by 1/2 and inputs it to the clock terminal of the shift register 78 (second Figure E).
The output of the shift register 78 (Fig. 2G) is H, I.
The pulse width is 4H, and the signal is shifted by 1H.

The output of the OR circuit 76 is an enable signal for the row electrode driver output, and is set to "0" in this embodiment.
(Figure 2F). For example, set the Low terminal to “0”
Then, all row electrode outputs become "0".

77 is a delay circuit for adjusting timing. NOR the inversion of the output of the first stage of the shift register 78 (G in Fig. 2), the output of the second stage (H in Fig. 2), and the NOR signal of the enable signal (output of the delay circuit 77, currently "0"). A pulse signal outputted from the circuit 80, level-shifted by the level shifter 81, and outputted (J in FIG. 2) becomes a scanning side drive signal to be applied to the row electrodes of the liquid crystal display panel. The signal at terminal 86 is input to shift register 78.
The output of the first stage is input to the SP terminal which is the start pulse signal input of the next stage row electrode driver when a plurality of row electrode drivers are connected continuously. In this way, the R/ terminal is set to "1", the B/ terminal is set to "0",
_H2 / ₁ terminal is “1”, D/terminal is “0”,
When the terminal is set to "1", the row electrode driver output will be 1 pulse with a width of 1H as shown in Figure 2 J and K.
Shift bit by bit.

Next, a case will be described in which the row electrodes of the liquid crystal display panel are taken out in both left and right directions. First, in the case of the right side, the R/terminal is "1", the B/terminal is "1",
_H2 / ₁ terminal is “0”, D/terminal is “0”,
Set the terminal to “1”. When the row electrodes are taken out in both left and right directions, in order to perform line-sequential driving, scan pulses must be alternately supplied to the left and right scan electrodes every scan period from the output terminals of scan circuits distributed on both the left and right sides. Timing waveforms in that case are shown in FIGS. 3 and 4. First, FIG. 3 shows timing waveforms of the scanning circuit placed on the right side. The data input signal of the shift register 78 and the reset signal of the flip-flop 71 are the same as in the case where the row electrodes of the liquid crystal display panel are taken out from one side (FIGS. 2A-D and 3A-D). The output Q of the flip-flop 71 is input to the clock terminal of the flip-flop 72, and the clocked inverter 73 selects the 1/2 frequency-divided signal (E in FIG. 3), which is input to the clock terminal of the shift register 78. . The output of the shift register 78, which shifts half bits at a time, becomes a signal shifted by 2H with a pulse width of 4H, as shown in FIG. 3G, H, and I. The output (enable signal) of the delay circuit 77 is shown in Fig. 3F.
become that way. The final output signal has a pulse width of 1H and is shifted one by one as shown in FIG. 3J and K. That is, this output is equivalent to extracting the odd or even numbered signal that is successively shifted one bit at a time.
The signal at the terminal 86 is a signal generated by triggering the n-th stage output of the shift register 78 at the rising edge of the inverted output of the flip-flop 71, and is used as the start pulse signal input for the next stage row electrode driver when a plurality of row electrode drivers are continuously connected. input to the SP terminal.

Next, in the case of the left side, the R/ terminal is set to "0", and the other settings are the same as in the case of the right side. The timing waveform for the left side is shown in FIG. The start pulse signal is input to the data terminal of the flip-flop 61, and the clock signal is input to the clock terminal.The output Q (Fig. 4C) obtained by inputting the start pulse signal to the data terminal of the flip-flop 61 is input to the data terminal of the flip-flop 62, and it is triggered at the falling edge of the clock signal. The obtained signal is shown in FIG. 4D. Furthermore, this signal is transferred to the flip-flop circuit 6.
The clocked inverter 65 selects the signal obtained by inputting the signal to the data terminal 3 and triggering it at the rising edge of the clock (Fig. 4E), and outputs the signal to the shift register 7.
Input to data terminal 8. flipflop 6
A NAND signal of the output Q of the flip-flop 2 and the inverted output of the flip-flop 63 is output from the NAND circuit 68, selected by the clocked inverter 70, and this signal is input to the reset terminals of the flip-flops 71 and 72 (FIG. 4F). . These shift registers 78
The signals input to the data terminals of the row electrode driver and the signals input to the reset terminals of the flip-flops 71 and 72 are delayed by 1H in time than the signals when the row electrode driver is set to the right side. Triggered by the falling edge of the clock signal, the flip-flop 71,
A clocked inverter 73 selects the signal frequency-divided by 1/4 by 72, and inputs it to the clock terminal of a shift register 78 (FIG. 4G). The output of the shift register 78, which shifts by half a bit, is the fourth
As shown in Figures I, J, and K, the pulse width is 4H and the signal is shifted by 2H. The start position of the output signal of the shift register 78 is 1H later in time than when the row electrode driver is set for the right side.
The output (enable signal) of the delay circuit 77 is as shown in FIG. 4H. The final output signal has a pulse width of 1H and a pulse width of 1H, as shown in Figure 4 L and M.
They are shifting one by one. However, the position of the first output is 1H later than when the row electrode driver is set for the right side.

Therefore, if the row electrode drivers are placed on both the left and right sides of the liquid crystal display panel, the start pulse signal SP
and the clock signal CL can be shared, and by simply changing the settings of the R/terminals of the left and right row electrode drivers, the row electrodes on the right and left sides of the liquid crystal display panel can be driven alternately.

<Effects of the Invention> As explained in detail above, the structure of the drive circuit of the present invention has the row electrode driver having switching terminals for one side extraction and for left and right side extraction, thereby allowing the row electrodes of the liquid crystal display panel to be connected to each other. It can be handled whether the removal is from one side or both the left and right sides. Furthermore, even in the case of extraction from both the left and right sides, the start pulse and clock can be driven by a common signal for the left and right sides. Therefore, by using the row electrode driver of the present invention, it is possible to take out the row electrodes of a liquid crystal display panel either on one side or on both the left and right sides, resulting in low power consumption, miniaturization, and high integration. I can do it.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a row electrode driver showing an embodiment of the present invention. FIG. 2 is a waveform diagram of the main part of the row electrode driver of the embodiment shown in FIG. 1 when set for unidirectional terminal extraction, and FIG.
The main part waveform diagram when the row electrode driver of the embodiment shown in the figure is set for the right side with terminal extraction in both directions, and FIG. 4 is a waveform diagram of the main part when the row electrode driver of the example shown in FIG. FIG. Fig. 5 is a block configuration diagram showing the structure of a conventional liquid crystal display device, Fig. 6 is a timing waveform diagram showing the main driving waveforms of the liquid crystal display device shown in Fig. 5, and Fig. 7 is a conventional panel SH drive method. FIG. 8 is a circuit diagram illustrating a column electrode driver of the conventional driver SH driving method; FIG. 9 is a timing waveform diagram showing drive waveforms in the circuit of FIG. 8; FIGS. 10A and 10B are explanatory diagrams showing connections with scanning circuits when row electrodes are taken out on one side and when they are taken out on both sides. H...Horizontal scanning period, 31, 41, 78...Shift register, 32, 42...Analog switch, 43...Sampling capacitor, 44...
...Transistor, 61, 62, 63, 71, 7
2, 82...flip flop, 64, 65, 6
9, 70, 73, 74, 83, 84...Clocked inverter, 67, 68...NAND circuit, 80
...Noah circuit, 77...Delay circuit, 81...
level shifter.

Claims (1)

[Claims] 1 Equipped with a scanning circuit that supplies scanning pulses through output terminals that are sequentially connected to scanning electrodes connected to the switching elements of a liquid crystal display panel in which an addressing switching element is added to each pixel of a matrix type display pattern. In the circuit structure for a liquid crystal display device, the scanning circuit has a first pulse output state in which a scanning pulse is sequentially outputted from an output terminal to the scanning electrode every scanning period, and a first pulse output state in which a scanning pulse is outputted from an output terminal to the scanning electrode. A circuit structure for a liquid crystal display device, comprising a switching terminal for switching between a second pulse output state and a second pulse output state in which scan pulses are sequentially outputted to every other scan electrode in synchronization with a period.