JPH0435734B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a matrix type liquid crystal display device.
In particular, the present invention relates to the structure of a drive circuit for a matrix type liquid crystal display device in which an addressing switching transistor is added to each picture element in a matrix type display pattern.

<Prior art> Matrix-type liquid crystal display devices that use nonlinear elements to drive liquid crystal display include address thin film transistors (hereinafter referred to as
Abbreviated as TFT. ) in a matrix, it is possible to obtain a high-contrast display equivalent to static drive even when performing multiplex drive with a small duty ratio, i.e., multiple lines.
TFT active matrix type liquid crystal display devices are known.

Some driving systems for this TFT active matrix type liquid crystal display device have circuit configurations and signal waveforms as shown in FIGS. 5 and 6. In the figure, 11 is a liquid crystal display panel, and a TFT 11c is connected to the intersection of a row electrode 11a and a column electrode 11b as shown in the figure. 11d is the capacitance of the liquid crystal layer. 12 is a row electrode driver mainly consisting of a shift register;
The scanning pulse S is sequentially shifted by the clock φ1 from the gate signal control section 13 and output to each row electrode. When the total scanning period of this row electrode is T and the number of scanning lines is N, the scanning period H is expressed as H=T/N. A pulse voltage having a pulse width equal to this scanning period H is sequentially applied to each row electrode so as to turn on the TFT 11c row by row. Reference numeral 14 denotes a column electrode driver, which has a drive method that samples and holds (SH) data directly to the display panel (hereinafter referred to as panel SH drive method), and a drive method that provides the column electrode driver with the function of sample and hold data (hereinafter referred to as “panel SH drive method”). (referred to as the driver SH drive system). As shown in FIG. 7, the panel SH drive type column electrode driver consists of a shift register 31, a sampling switch 32, etc., and clocks data serially sent from the data signal control section 15 at timings corresponding to each column. It is sampled in synchronization with φ2, outputted to the column electrodes sequentially, and written to the liquid crystal layer through the TFT 11c. In this driving method, data sampling and writing into the liquid crystal layer through the TFT 11c are performed within the same horizontal scanning period. Next, using Figures 8 and 9,
The SH drive method will be explained. In synchronization with the output of the shift register 41, the sampling switch 42
is turned on, and a charge corresponding to the data signal is stored in the capacitor 43. Then, a discharge pulse signal located in the first half of the horizontal blanking period is applied to Cl to discharge the remaining charge and form the reference state. Next, when a transfer pulse signal located in the latter half of the horizontal blanking period is applied to Cg, the charge stored in the capacitor 43 is transferred to the transistor 44 and output. With this drive method, data is written to the liquid crystal in the next 1H after sampling.

When the row electrodes are taken out from the liquid crystal display panel, they are all taken out at one end as shown in FIG. A possible method is to divide the row electrodes into left and right row electrodes and take them out alternately. When row electrodes are taken out at both the left and right ends, the signals applied to the row electrodes must be alternated left and right in time, so if the row electrode driver is placed on one side, it will be difficult to route the wiring for connection to the liquid crystal display panel. This increases the length and causes problems such as wiring crossing, which increases the wiring area or requires wiring using through-holes, which poses problems in terms of miniaturization and reliability. In addition, when row electrode drivers are placed on both the left and right sides, one takes out the output of the odd-numbered shift register, and the other takes out the output of the even-numbered shift register, so only half of the total number of stages is used. However, there are problems in terms of miniaturization and power consumption. Furthermore, a start pulse signal and a clock signal are required for operating the shift registers on the left and right sides, respectively, leading to an increase in the number of input signals.

<Object of the Invention> The present invention has been made in view of the above-mentioned problems in conventional drive circuits for matrix-type liquid crystal display devices. The object of the present invention is to provide a structure of a drive circuit section of a liquid crystal display device.

<Basic Principles and Examples> Hereinafter, examples will be described in which the drive circuit section of the liquid crystal display device according to the present invention is applied to a liquid crystal television.

Figure 1 shows a row electrode that can be connected to terminals of the row electrodes that apply signals to the switching elements of the liquid crystal display panel either in one end direction or in both left and right end directions, and has low power consumption and is easy to achieve high integration. A circuit diagram of the driver is shown. When the row electrodes of the liquid crystal display panel are taken out from one end, the R/terminal is set to "0", the B/terminal is set to "0", the _H2 / ₁ terminal is set to "1", the D/terminal is set to "0", and the terminal is set to "0". Set to 1”. When the row electrodes are taken out from one side, in order to perform line sequential driving, a scanning pulse must be supplied to the scanning electrodes from the output terminal of the scanning circuit every sequential scanning period. The timing waveform in that case is shown in FIG. A start pulse signal SP (FIG. 2A) with a width of 4H and a clock signal CL (FIG. 2B) with a period of 1H are input to the flip-flop 61, and the output signal Q (FIG. 2C) is further input to the flip-flop 61.
A signal as shown in FIG. 2D is obtained by triggering at the falling edge of the clock signal input to the data terminal No. 2. Furthermore, this signal is input to the data terminal of the flip-flop 63, and the clocked inverter 65 selects the signal obtained by triggering at the rising edge of the clock signal (E in FIG. 2), and the shift register 7
It is input to the data terminal of 8. This shift register 78 shifts half bits at a time. On the other hand, the output Q of the flip-flop 62 and the output Q of the flip-flop 63
A NAND signal, which is an inverted output of
0 is selected and input to the reset terminals of flip-flops 71 and 72 (FIG. 2F). A signal triggered by the falling edge of the clock signal CL by the flip-flop 71 and divided into 1/2 (Figure 2 G)
is selected by clocked inverter 74 and input to the clock terminal of shift register 78. The output of the shift register 78 is shifted by half a bit with respect to the clock signal, and becomes a signal with a pulse width of 4H and shifted by 1H as shown in FIG. 2, I, J, and K.
On the other hand, the output of the OR circuit 76 is an enable signal for the row electrode driver output, and is set to "0" in this embodiment.
(Figure 2H). For example, set the terminal to “0”
When set to , all row electrode driver outputs become "0".

77 is a delay circuit for adjusting timing. A NOR signal of the inversion of the first stage output (FIG. 2 I) of the shift register 78, the second stage output (FIG. 2 J), and the enable signal (FIG. 2 H) is output from the NOR circuit 80, and the level shifter 81
The pulse signal level-shifted and output (L in FIG. 2) becomes a scanning drive signal to be applied to the row electrodes of the liquid crystal display panel. The signal at the terminal 86 is the output of the n-th stage of the shift register 78, and is used when a plurality of row electrode drivers are connected continuously. In this way, the R/ terminal is set to "0", the B/ terminal is set to "0",
_H2 / ₁ terminal is “1”, D/terminal is “0”,
When the terminal is set to "1", the row electrode driver output is a pulse with a width of 1H that is continuously shifted one bit at a time as shown in FIG. 2 L and M. Therefore, this corresponds to the case where the row electrode terminals of the liquid crystal display panel are taken out in one end direction.

Next, a case will be described in which the row electrodes of the liquid crystal display panel are taken out in both left and right end directions. First, for right side exit, set the R/terminal to "1", the B/terminal to "1", the _H2 / ₁ terminal to "0", the D/terminal to "0", and the terminal to "1". . When the row electrodes are taken out in both left and right directions, in order to perform line-sequential driving, scan pulses must be alternately supplied to the left and right scan electrodes every scan period from the output terminals of scan circuits distributed on both the left and right sides. Timing waveforms in that case are shown in FIGS. 3 and 4. First, the timing waveform of the scanning circuit placed on the right side is
As shown in the figure. A start pulse signal SP with a width of 4H (FIG. 3A) and a clock signal CL with a period of 1H (FIG. 3B) are input to the flip-flop 61, and the output signal Q (FIG. 3C) is input to the clocked inverter 64. It is selected and inputted to the data terminal of the shift register 78. On the other hand, after the inverted output of the flip-flop 61 and the start pulse signal SP are processed by the NAND circuit 67, the output signal is selected by the clocked inverter 69 and inputted to the reset terminals of the flip-flops 71 and 72 (FIG. 3D). . Flip-flops 71 and 72 reduce the clock signal CL to 1/4
The clocked inverter 73 selects the frequency-divided signal (FIG. 3E) and inputs it to the clock terminal of the shift register 78. The output of the shift register 78, which shifts half bits at a time, becomes a signal shifted by 2H with a pulse width of 4H, as shown in FIG. 3G, H, and I. The output (enable signal) of the delay circuit 77 is as shown in FIG. 3F. The final output signal has a pulse width as shown in Figure 3 J and K.
Shift one by one in 1H. That is,
This output is equivalent to extracting the odd or even number of a signal that is successively shifted one bit at a time. The signal at the terminal 86 is a signal generated by triggering the n-th stage output of the shift register 78 at the rising edge of the inverted output of the flip-flop 71, and is used as the start pulse signal input for the next stage row electrode driver when multiple row electrode drivers are connected continuously. SP that is
input to the terminal.

Next, in the case of exiting towards the left end, set the R/ terminal to “0”
, and other settings are the same as when extracting from the right end. FIG. 4 shows timing waveforms in the case of extraction in the left end direction. The data input signal to the shift register 78 and the reset signal to the flip-flops 71 and 72 are the same as in the case where the row electrode driver is set for single-end extraction (FIGS. 2A-F and 4A-F). The signals input to the data terminal of these shift registers 78 and the signals input to the reset terminals of flip-flops 71 and 72 are delayed by 1H in time than the signals when the row electrode driver is set for right-end extraction. . below,
The operation of the circuit is the same as when it is set for extraction in the right direction, and the final output signal is a pulse with a pulse width of 1H that shifts one by one, as shown in Figure 4 L and M. becomes. In other words, this output is equivalent to extracting the even or odd numbered signal that is successively shifted one bit at a time. However, the position of the first output signal is 1H later than when the row electrode driver is set for right-end direction extraction.

Therefore, when the terminals of the row electrodes of a liquid crystal display panel must be driven alternately left and right in both left and right directions, row electrode drivers are arranged for the left end and right end, respectively, as described above. By simply changing the setting of the R/terminal of the electrode driver, the start pulse and clock can be made common to the left and right sides, and the row electrodes of the liquid crystal display panel can be driven alternately on the left and right sides.

In this way, switching between single-end direction extraction and left-right direction both direction extraction can be performed using the B/terminal, and switching between right-end direction and left-end direction extraction can be performed using the R/terminal. can. Further, in either case, driving can be performed using a common start pulse and clock. The first output signal in the case of one-end direction extraction and the first output signal in the case of right- and left-end direction extraction (the first output signal in the case of right-end direction extraction)
are output at the same time position.

<Effects of the Invention> As explained above, the structure of the drive circuit of the present invention has the row electrode driver having a switching terminal for taking out in one end direction and for taking out in both left and right directions, thereby controlling the rows of the liquid crystal display panel. The terminal can be taken out from either one end or both left and right ends. Furthermore, since any terminal output can be driven using a common start pulse and clock, the position of the first output signal can be made temporally the same. Therefore, by using the row electrode driver of the present invention, it is possible to connect the row electrodes of a liquid crystal display panel either in one end direction or in both right and left end directions, resulting in low power consumption and small size. It is possible to realize high integration and high integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a row electrode driver showing one embodiment of the present invention. FIG. 2 is a waveform diagram of the main part of the row electrode driver of the embodiment shown in FIG.
The main part waveform diagram when the row electrode driver of the embodiment shown in the figure is set for terminal extraction in the right end direction with terminal extraction in both the left and right ends, and FIG. FIG. 4 is a waveform diagram of the main part when the terminal is set to be taken out in the left end direction. FIG. 5 is a block configuration diagram showing the configuration of a conventional liquid crystal display device, FIG. 6 is a timing waveform diagram showing main driving waveforms of the liquid crystal display device shown in FIG. 5, and FIG.
The figure is a circuit diagram illustrating a conventional panel SH drive system column electrode driver, and Figure 8 is a conventional driver SH
A circuit diagram illustrating a column electrode driver of the driving method, FIG. 9 is a timing waveform diagram showing drive waveforms in the circuit of FIG. 8, and FIGS. 10A and B are cases in which row electrodes are taken out on one side and on both sides. FIG. 3 is an explanatory diagram showing connection with a scanning circuit in the case of FIG. H...Horizontal scanning period, 31, 41, 78...Shift register, 32, 42...Analog switch, 43...Sampling capacitor, 44...
...Transistor, 61, 62, 63, 71, 7
2, 82...flip flop, 64, 65, 6
9, 70, 73, 74, 83, 84...Clocked inverter, 67, 68...NAND circuit, 80
...Noah circuit, 77...Delay circuit, 81...
level shifter.

Claims (1)

[Claims] 1 A scanning pulse is supplied to an input terminal through an output terminal that is sequentially connected to a scanning electrode connected to the switching element of a liquid crystal display panel in which an addressing switching element is added to each pixel of a matrix type display pattern. In a driving circuit for a liquid crystal display device comprising a scanning circuit that sequentially outputs signals in synchronization with a start pulse, the scanning circuit has a scanning circuit that outputs scanning pulses from the output terminal to the scanning electrodes in synchronization with the input of the start pulse. a first pulse output state in which every other scanning pulse is output sequentially corresponding to a scanning period; and a first pulse output state in which a scanning pulse is output from the output terminal in synchronization with the input of the start pulse. A switching terminal is provided for switching between a second pulse output state in which a scan pulse is outputted to every other scan electrode sequentially corresponding to the scan period in a state delayed by one pair of scan periods. A drive circuit for a liquid crystal display device characterized by: