JPH0435820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mode discriminating device, and more particularly to a mode discriminating device that discriminates a mode based on a plurality of mode signals input as digital signals, for example.

In the conventional mode discrimination circuit, a plurality of digital signal mode outputs are individually integrated and discriminated using a D-type flip-flop. Therefore, when the number of modes increases, a correspondingly large number of flip-flops must be used, making the circuit complex and expensive. Furthermore, such a mode discriminating circuit has a drawback in that when a plurality of digital signal mode outputs are erroneously inputted, it is not possible to determine which mode the circuit will shift to. Furthermore, such a mode discrimination circuit can be used for example in a VTR.
When used as a mode discrimination circuit for tape running speed, the following drawbacks occurred. That is, in the mode discrimination circuit described above, when the digital signal mode output switches from one mode to another mode, the discrimination output also immediately responds and switches from one mode to another mode. Therefore, the tape running speed of the VTR changes rapidly. Therefore, the tape may break or stretch, and an excessive load may be placed on the tape running mechanism.

Therefore, the main object of the present invention is to provide a mode discrimination device that can overcome all the above-mentioned drawbacks.

In summary, this invention provides one integrating circuit that integrates the output of a DC power supply, and switches the resistance value of this integrating circuit stepwise according to each mode output, so that each of the integrated circuits has a predetermined value corresponding to each mode output. A plurality of comparing means having a reference voltage are provided to compare the reference voltage with the output of the integrating circuit, and the output of the comparing means is taken out as a mode discrimination output.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the configuration, mode outputs based on digital signals are given to input terminals 1a, 1b, . . . 1n. These input terminals 1a, 1b...1n are connected to respective bases of transistors 2a, 2b...2n, respectively. A voltage for driving is applied from a DC power supply 13 to the collectors of predetermined ones of the transistors 2a to 2n. The emitters of these transistors are connected to one end of an integrating capacitor 6 via resistors 3a, 3b, . . . .
The emitters of the transistors other than the above-mentioned predetermined ones are grounded, and the collectors are connected to one end of the capacitor 6 via a resistor (for example, 3n). The connection point between the resistors 3a to 3n and the capacitor 6 is connected to the DC power supply 1 through the resistor 4.
3 and is grounded via a resistor 5. These resistors 3a to 3n, 4 and 5
constitutes a voltage dividing circuit for the DC power supply 13, and also constitutes an integrating circuit in cooperation with the capacitor 6. More specifically, the transistors 2a to 2n are turned on and off in accordance with the digital signal mode outputs applied to the input terminals 1a to 1n, and the voltage dividing ratio of the voltage dividing circuit described above changes accordingly. Note that the resistance values of resistors 4 and 5 are selected to be approximately equal. Therefore, when transistors 2a to 2n are all off, DC power supply 13 is voltage-divided only by resistors 4 and 5, and capacitor 6
A voltage approximately half the power supply voltage of the DC power supply 13 is applied to the DC power supply 13.

The output of the above-mentioned integrating circuit, ie, one end of the capacitor 6, is connected to one end of the resistors 7a, 7b, . . . , 7n. The other ends of these resistors 7a, 7b...7n are connected to the bases of one of the transistors constituting the comparators 8a, 8b...8n, respectively. The bases of the other transistors constituting these comparators 8a, 8b...8n are connected to resistors 10a, 10b, respectively.
...10n, a predetermined reference voltage is applied.
This reference voltage is obtained from a voltage dividing circuit constituted by resistors 11a, 11b, 11c...11n, ₁₁₀ connected in series to DC power supply 13 and resistors 10a to 10n. In addition, comparators 8a, 8b...
A constant current source 9a, 9b, . These constant current sources 9a to 9n are provided to prevent comparators 8a to 8n from malfunctioning due to fluctuations in power supply voltage or external noise. Each comparator 8
The comparison outputs (comparison results) of a, 8b...8n are provided to output terminals 12a, 12b...12n, respectively.

FIG. 2 is a diagram showing the relationship between the output voltage in each mode of the integrating circuit including the capacitor 6 and each reference voltage applied to the comparators 8a to 8n.
Now, if a mode output is given to the input terminal 1a, the transistor 2a is turned on, and the resistor 3a is connected in parallel to the resistor 4. Therefore, the voltage at the integral terminal 14 is obtained by dividing the DC power supply 13 by the resistors 3a, 4, and 5. The voltage at the integral terminal 14 at this time is assumed to be Va. Next, input terminal 1b
When mode output is given to resistor 4, resistor 3b
are connected in parallel, and the voltage at the integral terminal 14 is the DC power supply 13 divided by the resistors 3b, 4, and 5. The voltage at the integral terminal 14 at this time is assumed to be Vb. Thereafter, the voltage at the integral terminal 14 changes from Vc to Vn as mode outputs are applied to the input terminals 1c (not shown)...1n. Here, if the values of the resistors 3a to 3n are appropriately selected, it is possible to set the voltage Va to the voltage Vn at equal potential intervals, as shown in FIG. Note that when the mode output is not applied to any input terminal, a voltage dividing circuit is formed by resistors 4 and 5 as described above, and the integral terminal 1
The voltage of 4 is almost half the voltage of DC power supply 13 (V0)
becomes. Note that the resistors 3a to 3n include those connected in parallel to the resistor 4 and those connected in parallel to the resistor 5. When any of the resistors is connected in parallel to the resistor 4, the voltage at the integral terminal 14 at that time becomes larger than V0. Conversely, if any resistor is connected in parallel to the resistor 5, the voltage at the integral terminal 14 at that time will be smaller than the voltage V0. Therefore, the voltage V0 is from the voltage Va
It will be located somewhere between Vn,
The resistance values of the resistors 3a to 3n are appropriately selected so that the above-mentioned equipotential interval relationship does not collapse.
That is, voltage Va to voltage V0 changes at equal potential intervals, and voltage V0 to Vn similarly changes at equal potential intervals.

On the other hand, reference voltages as shown by dotted lines in FIG. 2 are applied to the comparators 8a to 8n. That is, the comparator 8a is given a voltage (Va+Vb)/2 intermediate between the voltage Va and the voltage Vb as a reference voltage, the comparator 8b is given a reference voltage (Vb+Vc)/2, and so on. A reference voltage Vn/2 is applied to the comparator 8n. To generate such a reference voltage, the resistance values of resistors 10a to 10n and resistors 11a to ₁₁₀ are chosen.

In operation, first, a case where a mode output is applied to the input terminal 1a will be described. In this case, the transistor 2a is turned on, and the resistor 4 is connected to the resistor 3a accordingly.
are connected in parallel. Therefore, as mentioned above,
The output voltage of the integrating circuit including capacitor 6 is Va. Since this voltage Va is higher than the highest reference voltage (Va+Vb)/2 among the reference voltages applied to the comparators 8a to 8n, no output appears at any of the output terminals 12a to 12n.

Next, when the mode output is applied to the output terminal 1b, the resistor 3b is connected in parallel to the resistor 4, and the output voltage of the integrating circuit becomes Vb. Since this voltage Vb is lower than the reference voltage applied to the comparator 8a, as shown in FIG. 2, the comparator 8a detects this fact. Therefore, an output appears only at the output terminal 12a. Similarly, when a mode output is applied to the input terminal 1n, the output of the integrating circuit becomes Vn, and outputs appear at all output terminals 12a to 12n. The outputs obtained from these output terminals 12a to 12n can be processed by a simple logic circuit depending on the purpose.

Next, a case will be described in which an incorrect mode output is applied to one of the input terminals 1a to 1n. In this case, if the mode output error time is short, the error will not be transmitted to the subsequent stage due to the integration effect of the integrating circuit including the capacitor 6. This is because even if an input voltage corresponding to a certain mode is applied to the integrating circuit, the output voltage becomes equal to the input voltage after a predetermined time delay determined by the time constant.

Further, as a manner in which erroneous mode outputs are input, two or more mode outputs may be provided at the same time. However, in the above-mentioned embodiment, the mode output given as a digital signal is once converted to a DC voltage level corresponding to the mode, and the mode is determined based on the converted DC voltage level. , even if two or more mode outputs are input at the same time, it is determined as any one mode.

Next, a case will be described in which the mode outputs applied to the input terminals 1a to 1n shift from one mode to another. In this case, no matter which mode the mode transition is made between, the output of the integrating circuit including the capacitor 6 smoothly changes from the mode before transition to the mode after transition due to the integration effect.
That is, the mode changes from the mode before the transition to the adjacent mode in sequence and settles into the mode after the transition. On the other hand, in the conventional mode discrimination circuit, each mode output is discriminated individually, so that the discrimination output also changes rapidly according to the transition of the mode output.

FIG. 3 is a circuit diagram showing another embodiment of the invention. The embodiment shown in FIG. 3 is constructed so that three modes can be distinguished. That is, an input terminal 1a to which a first mode output is applied and an input terminal 1b to which a second mode output is applied are provided. Then, this mode discriminating device selects first and second mode outputs corresponding to these first and second mode outputs.
The third mode is determined, and the third mode is determined when a mode output is not applied to any of the input terminals 1a and 1b.

Note that in FIG. 3, parts having similar functions to those in FIG. 1 are given the same reference numerals as in FIG. 1.

First, when the first mode output is applied to the input terminal 1a, the transistor 21a is turned off, the transistor 23a is turned on, the transistor 27a is turned on, and so on.
Transistor 28a is turned on. Therefore,
The potential of the integral terminal 14 is a value V1 obtained by dividing the voltage of the DC power supply 13 by the resistors 4, 5, and 3a. on the other hand,
When the second mode output is applied to the input terminal 1b, the transistor 21b is turned off and the transistor 3 is turned off.
3b is turned on, and the potential of the integral terminal 14 becomes a value V2 obtained by dividing the voltage of the DC power supply 13 by the resistors 4, 5 and 3b. Next, when the mode output is not applied to either of the input terminals 1 and 2, both the transistors 28a and 33b are off, and the potential of the integral terminal 14 is the voltage of the DC power supply 13, which is connected to the resistors 4 and 5. The voltage divided by is the value V0.
Reference voltages (V1+V0)/2 and (V0+V2)/2 are applied to comparators 8a and 8b, respectively. For that purpose, resistors 10a, 10b, 11
Each resistance value of a, 11b and 11c is selected to be an appropriate value. When the output of the integrating circuit is V1, it is higher than either reference voltage, so no output is obtained from either of the output terminals 12a and 12b. When the output of the integrating circuit is V0, only the comparator 8a detects that it is lower than the reference voltage, and the output terminal 12a
Output is obtained only when When the output of the integrating circuit is V2, it is smaller than the reference voltage of both comparators 8a and 8b, so the output terminals 12a and 12b
You can get the output from Therefore, the output terminal 12
The mode can be switched by processing the outputs obtained from a and 12b with an appropriate logic circuit.

Incidentally, the embodiment shown in FIG. 3 also has the same effect as that shown in FIG. 1. That is, erroneous input of the mode output within the time constant of the integrating circuit is not transmitted to comparators 8a and 8b. Further, even if the first and second mode outputs are applied at the same time, it will not become impossible to determine the mode. Furthermore, even when the output of the integrating circuit shifts from V2 to V1 or from V1 to V2, it always passes through the level of V0, so the mode does not change abruptly but smoothly. That is, from the first mode to the second mode or
Even when transitioning from mode to first mode, the mode can be determined as first mode → third mode → second mode or second mode → third mode → first mode. It will be done in stages. For example, the mode discrimination circuit shown in Figure 3 can be used for VHS system.
The first mode is SP mode (tape speed 33.35 mm/s), the third mode is LP mode (tape speed 16.68 mm/s), and the second mode is EP mode (tape speed 11.12 mm/s). /s), rapid speed changes of the capstan are prevented, and transient loads on the tape and the capstan motor are reduced. In addition, the above SP, LP,
Digital detection in EP mode is normally detected by the number of capstan FG signals in the CTL signal section.

Furthermore, the embodiments shown in FIGS. 1 and 3 have the following effects. That is, since it is sufficient to provide only one integrating capacitor for discrimination between a plurality of modes, it is easy to integrate the circuit. This is because even if the capacitor 5, which is difficult to implement with a semiconductor, is an external component of an integrated circuit, since there is only one capacitor, only one terminal pin needs to be added, and an efficient integrated circuit can be realized. In contrast, conventional mode discrimination circuits require integration capacitors corresponding to the number of mode outputs, making integration difficult.

As described above, according to the present invention, by switching the resistance value of the integrating circuit in stages according to the plurality of mode outputs based on digital signals, mode changes are converted to a DC voltage level, and the DC voltage level is Since the levels are compared by a plurality of comparison means to obtain the discrimination output, the mode transition is performed stepwise and smoothly. Therefore, when applied to various electronic devices such as VCRs, the tape and devices will not be damaged. Further, even if a plurality of mode outputs are input at the same time, it will not become impossible to distinguish as in the conventional case.

Furthermore, since it is only necessary to provide one integration circuit,
This facilitates circuit integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing the relationship between the output of the integrating circuit and the reference voltage of the comparator. FIG. 3 is a circuit diagram showing another embodiment of the invention. In the figure, 1a to 1n are input terminals, 2a
2n to 2n are transistors, 3a to 3n, 4
and 5 is a voltage dividing resistor for an integrating circuit, 6 is an integrating capacitor, 8a to 8n are comparators, 10a to 1
0n and 11a to ₁₁₀ are reference voltage dividing resistors, and 13 is a DC power supply.

Claims (1)

[Scope of Claims] 1. A device comprising: a plurality of input terminals each receiving a plurality of mode signals based on digital signals; a resistance means connected to a power supply potential; and a capacitance means connected to the power supply potential via the resistance means. a plurality of resistor elements each having a predetermined different resistance value and connected to the resistor means, each connected between the power supply potential and the plurality of resistor elements; and a plurality of switching means that are selectively turned on in response to mode signals applied to the plurality of input terminals, the integrating circuit means being connected to the resistor means and the switching means that are selectively turned on. a reference voltage generating means for outputting a voltage determined by a combined resistance with a resistive element and generating a plurality of predetermined reference voltages; A mode discriminating device including a plurality of comparison means each comparing a given reference voltage with a given reference voltage.