JPH0435911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic MIS semiconductor memory element and a method for manufacturing the same.

(Prior art and its problems) In recent years, there has been a growing trend toward higher integration and higher density of semiconductor memory elements, and along with this, the miniaturization of elements is progressing. We are facing various technical difficulties in many aspects, including the following. In addition, since the storage capacity cannot be reduced especially in a one-transistor memory cell, which is a typical structure of dynamic random access memory (hereinafter abbreviated as DRAM), which consists of one transistor and one storage capacitor, miniaturization is difficult. Although more difficult problems are being faced and various new techniques are being considered, at the IEDM (International Electronic Devices Conference) held in Washington, USA in December 1982,
From page 806 to page 807 of the paper proceedings, “A
CORRUGATED CAPACITANCE CELL
(CCC) FOR MEGABIT DYNAMIC MOS
H.SUNAMI titled “MEMORIES”
In a paper published by et. Although the element area is significantly smaller than that of a memory element, the element area, including the surrounding isolation area, is approximately
It is about 21 square microns, and if you try to create a 4-megabit memory circuit using this structure, the memory element alone will be about 88 square millimeters, which is quite large.

(Objective of the Invention) The present invention eliminates these conventional drawbacks, dramatically reduces the device area compared to conventional devices with the same design standards, and furthermore, the channel portion of the control transistor is electrically connected to the substrate. An object of the present invention is to provide a semiconductor memory element and a method for manufacturing the same.

(Structure of the Invention) According to the present invention, a columnar structure made of a first silicon layer of a second conductivity type is provided on the surface of a silicon single crystal substrate of a first conductivity type, and a columnar structure is further provided around the columnar structure. It has a first silicon of a first conductivity type that is electrically connected to the substrate and whose upper surface is substantially the same as the upper surface of the columnar structure, and the columnar structure and the first silicon around the columnar structure.
An insulating film is provided on at least a partial region of the interface with the conductive type silicon, or is not provided at all, and at least a portion of the upper surface of the first silicon of the first conductive type and the above on both sides thereof. A second silicon layer of the first conductivity type spans a part of the upper surface of the columnar structure, an insulating film is provided on the other upper surface, and a thin insulating film is formed on one side of the second silicon layer. A conductor layer is provided in contact with this thin insulating film, and a second conductor layer is provided on the upper surface of the second silicon layer.
A semiconductor memory element characterized by being provided with a conductivity type layer is obtained.

B. Furthermore, according to the present invention, for a structure in which a single crystal silicon layer of a second conductivity type is formed on a single crystal silicon substrate of a first conductivity type, the silicon layer is formed until it reaches the substrate, leaving a desired region in a columnar shape. ○B Cover the exposed silicon surface with an insulating film, ○C Selectively remove the insulating film on the top surface of the silicon substrate outside the columnar region, ○D Recess almost to the top surface of the columnar part. A first monocrystalline or polycrystalline silicon of the first conductivity type, or a combination thereof, is buried in the first conductivity type, ○e the entire surface is covered with an insulating film, ○f a part of the upper surface of the columnar part and a part of the upper surface of the buried layer in the recess is buried. A conductor layer is formed to serve as a gate electrode spanning the conductor layer, ○G is coated with a gate insulating film on the side surface of the conductor layer, and ○H is the silicon surface on the top surface of the columnar part not covered with the conductor layer and the adjacent area covered with the conductor layer. Both parts of the silicon surface of the upper surface of the buried layer which are not etched are exposed by selectively etching the insulating film indicated by ○ and ○. A method for manufacturing a semiconductor memory element is obtained, which comprises forming a second single-crystalline or polycrystalline silicon layer, and adding an impurity to the upper surface of the silicon layer to form a second conductivity type diffusion layer.

Furthermore, according to the present invention, ○a) the silicon layer in a desired region of the first conductivity type single crystal silicon substrate is removed to a desired depth to form a columnar hole; ○b) the exposed silicon surface is insulated. ○C Remove the insulating film on the bottom of the columnar hole or the part including it, ○D Cover almost the top of the hole with an impurity that changes from the first conductivity type to the second conductivity type in the middle. ○E Cover the entire top surface with an insulating film, ○F A gate electrode straddles a part of the top surface outside the columnar part and a part of the top surface of the buried layer in the recess. A conductor layer is formed, ○g. A gate insulating film is deposited on the side surface of the conductor layer, and ○h. Both parts of the silicon surface on the upper surface of the buried layer are exposed by selectively etching the insulating film indicated by ◯◯, and a second conductivity type of the first conductivity type is formed on at least the exposed silicon surface. A method for manufacturing a semiconductor memory element, comprising: forming a single-crystalline or polycrystalline silicon layer, and adding an impurity to the upper surface of the silicon layer to such an extent that a second conductivity type diffusion layer overlaps the gate electrode. is obtained.

Furthermore, according to the present invention, for a structure in which a second conductivity type single crystal silicon layer is formed on a first conductivity type single crystal silicon substrate, the silicon layer is extended until it reaches the substrate, leaving a desired region in a columnar shape. ○B Cover the exposed silicon surface with an insulating film; ○C Selectively remove the insulating film on the top surface of the silicon substrate outside the columnar region from the substrate; ○D Up to almost the top surface of the columnar part. Fill the recess with the first single crystal or polycrystalline silicon of the first conductivity type, or a combination thereof. Or, instead of ○A to ○D, fill the desired region on the single crystal silicon substrate of the first conductivity type. Remove the silicon layer to a desired depth, create a columnar hole, ○F. Cover the exposed silicon surface with an insulating film, ○G. Remove the bottom of the columnar hole or the part containing it, ○C. Hole. For a structure created by filling almost the top surface of the silicon single crystal or polycrystalline silicon or a combination thereof having an impurity distribution such that the conductivity type changes from the first conductivity type to the second conductivity type in the middle thereof, A silicon layer of the first conductivity type is grown over the entire surface, and at least on the single crystal silicon, single crystal silicon is epitaxially grown, and a silicon layer of the first conductivity type is grown on the second conductivity type region. The bottom of the layer is the second
Next, the single crystal silicon layer of the first conductivity type in the region including the substrate of the first conductivity type and the buried layer of the second conductivity type is left in the lower layer, and The other regions grown in step 1 are removed, and a thin insulating film is grown on the exposed silicon surface. A conductor that will become a gate electrode is attached to a portion including the region, and an impurity is added to the upper surface of the first conductivity type silicon layer to form a second conductivity type diffusion layer to an extent that it overlaps the gate electrode. Further, according to the present invention, there is obtained a method for manufacturing a semiconductor memory element characterized by the following: The silicon layer is removed until it reaches the substrate, leaving a desired region in the form of a column. ○B. The exposed silicon surface is covered with an insulating film. ○C. The insulating film on the top surface of the silicon substrate outside the columnar region is selectively removed. ○D The first single crystal or polycrystalline silicon of the first conductivity type is buried in the recess almost up to the top surface of the columnar part, or a combination thereof is buried in the recess, or ○H is replaced with ○I to ○D. 1) Remove the silicon layer in a desired area on a single conductivity type single crystal silicon substrate to a desired depth, provide a columnar hole, ○F) Cover the exposed silicon surface with an insulating film, ○G) Cover the bottom surface of the columnar hole or Remove the insulating film in the part containing it, and use monocrystalline silicon or polycrystalline silicon, which has an impurity distribution that changes from the first conductivity type to the second conductivity type, or In combination, an insulator is deposited on the surface of the structure created by the method of embedding, and an opening is provided in the insulator containing the underlying first and second conductive layer regions. Silicon of the first conductivity type is grown within the exposed silicon surface, and the bottom of the first conductivity type layer is of the second conductivity type on the underlying second conductivity type region. Adding impurities of the conductivity type, ○W fills an insulator in the surface recesses, ○F forms a second conductive region on the exposed silicon surface, and ○Y forms an upper layer existing in the part containing the second conductive region in the lower layer. A method for manufacturing a semiconductor memory element, characterized in that a region including a part of the silicon region is removed, a gate insulator is formed on the surface of the silicon region, and a conductor serving as a gate electrode is embedded in a concave portion of the surface. is obtained.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a partially cutaway perspective view showing one embodiment of the present invention, showing four memory elements at the same time. 101 is a P-type single crystal silicon substrate, 102
is columnar n-type single crystal silicon perpendicular to the substrate 101,
103 is embedded P type silicon, 104 is n
between the P-type silicon 103 surrounding the vertical sidewalls of the columnar single crystal silicon 102 and embedded therein.
An insulating thin film forming an MIS capacitor, 105 is an insulating film formed to cover a part of the upper surface of the n-type columnar single crystal silicon 102 and a part of the upper surface of the buried P-type silicon 103, 106 is a control MIS transistor 107 is a P-type single-crystal silicon layer that becomes the channel part of the control transistor, and 107 is a P-type single-crystal silicon layer that spans two column-shaped n-type single-crystal silicon layers 102 and serves as a word line. contacting a portion of the upper surface of the type single crystal silicon that is not covered with the insulating film 105, and furthermore, contacting at least a portion of the upper surface of the buried P type silicon sandwiched between the two columnar n type single crystal silicon. It is set up in such a way that it touches. Therefore, the channel portion is electrically connected to the substrate 101.

108 is an n layer provided on the P-type silicon layer.
The mold is a silicon layer. 109 is a gate insulating film, 1
Reference numeral 10 denotes an n-type portion formed in the P-type silicon stack 107 by diffusion of impurities from the upper part of the n-type columnar single crystal silicon 102 . 108 and 10
2,110 are source/drain electrodes.

Reference numeral 111 is an interlayer insulating film, and 112 is a metal wiring, which is connected to the n-type layer 108 and becomes a bit line.

In this way, a dynamic memory cell is constructed.

The insulating thin film 104 forming the MIS capacitor is formed before embedding the P-type silicon 103.
Cases such as 104a where the joint is completely covered and the above
A case such as 104b where the Pn junction is not completely covered may occur during the process of partially removing the insulating thin film.

Therefore, in the former case, most of the power storage capacity is MIS.
In the latter case, one part will be MIS type and the other part will be Pn junction type. These capacitances change according to the product of the circumferential length of the columnar portion, the height at which the n-type layer 102 and the p-type layer 103 overlap, and the sum of the cross-sectional area of the columnar portion. Even if the n-type layer 102 and the p-type layer 10
There is an advantage that a sufficiently large electric storage capacity can be obtained by increasing the height of the overlapping portions. If this structure is used, the minimum occupied area can be reduced to 5F ² (2F x 2.5F) when the design standard is F, and high density can be achieved.

A more specific example of this embodiment will be described below with reference to FIG. 2 together with the second invention (manufacturing method) of the present application.

FIG. 2a shows a substrate in which an n-type silicon layer 202 with a thickness of about 4 μm and a concentration of ~10 ¹⁸ cm ^-3 is epitaxially grown on a P-type single crystal silicon substrate 201, and a mask material (in this case, a thick SiO ₂ Using anisotropic etching such as reactive ion etching (RIE), the part of the substrate that will become the memory cell is etched vertically by about 5 μm, with a pitch of 3 μm in the horizontal direction, and in the vertical direction.
Short side 1.5μm x long side arranged at 3.75μm pitch
A state in which a 2.25 μm prismatic pattern is formed is shown.

Figure 2b shows a thickness of 100 Å on the side wall of the prismatic pattern.
thermal oxide film with a thickness of about 100 Å and low pressure CVD with a thickness of about 100 Å
A two-layer insulating film 204 made of a silicon nitride film is formed, and the insulating film deposited also on the single crystal silicon substrate at the bottom of the trench is selectively removed using anisotropic etching. If the prismatic pattern is slightly inclined from the vertical or the etching anisotropy is slightly poor, selective epitaxial growth (source gas Si ₂ Cl ₂ +HCl, 950°C,
0.3 μm/min) to form the groove at 2 × 10 ¹⁶ cm ^-3
A state in which the mold silicon layer 203 is embedded is shown.

Next, the entire surface is covered with a silicon oxide film 2 with a thickness of 2000 Å.
05 and then a polycrystalline silicon layer 206 doped with a high concentration of n-type impurity and having a thickness of about 2 μm.
is deposited to cover a part of the upper surface of the prism to form a gate electrode of a control capacitance MOS transistor, that is, a word line. The word line runs in the long side direction of the prism pattern, has a width of 1 μm, and is formed so that its end almost coincides with the end of the prism when viewed from above.

Thereafter, a thin gate oxide film 209 with a thickness of 200 Å is formed on the side wall of the polycrystalline silicon pattern by thermal oxidation, and the polycrystalline silicon is used to form a thin gate oxide film 209 in one direction.
A side is defined, and two sides perpendicular to the side are provided with rectangular openings determined separately by a photoresist process.

(Figure 2c) This opening spans two prisms, and the buried P-type layer 2 is sandwiched between the two prisms.
03 is formed in a shape that also hangs over the top surface.

The dimensions of the opening are 2.5 μm on the long side and 2.25 μm on the short side. In this embodiment, the short side is substantially aligned with the long side of the prism. The channel width of the MOS transistor is approximately determined by the dimension of this short side.

The short side of this opening may be slightly larger or slightly smaller than the long side of the prism.

Next, P at a concentration of about 2×10 ¹⁶ cm ^-3 is added from the opening.
The mold layer 207 was grown by selective epitaxial method.
(Figure 2d). This P-type layer becomes the channel portion of the two MOS transistors. Since the concentration of the P-type layer is set to be lower than the concentration of the n-type prismatic portion, part of the P-type layer becomes 0.2 μm thick or more due to the diffusion of n-type impurities during epitaxial heating. n
It is converted into a mold layer 210.

Therefore, since the gate electrode and the n-type layer 210 overlap with the gate oxide film 209 in between, there is no need for offset. Next, an n ⁺ layer 208 having a thickness of about 0.3 μm is formed by arsenic ion implantation or the like. two n-type layers 20
The distance between 8,210 and 210 is the effective channel length.

Thereafter, the exposed portion of the silicon oxide film 205 is filled in using a CVD method, an RF bias sputtering method, a silica coating method, or the like. Thereafter, an interlayer insulating film is formed on the entire surface, and aluminum wiring is formed to serve as a bit line for the n ⁺ layer 208, thereby obtaining the structure shown in FIG.

Next, an embodiment of the third invention (manufacturing method) of the present application will be described with reference to FIG.

The difference from the second invention is that the source/drain electrodes to be formed deep (corresponding to 202 in Figure 2) are formed by digging into the silicon substrate and filling the holes with silicon. It is.

In FIG. 3a, a part of the P-type single-crystal silicon substrate 301 is subjected to RIE using a thick silicon oxide film or the like as a mask.
After excavating vertically by about 5 μm using anisotropic etching, forming 1.5 μm x 2.25 μm prismatic holes arranged at a 3 μm pitch in the horizontal direction and 3.75 μm in the vertical direction, a thick An insulating film 304 made of a thermal oxide film with a thickness of about 100 Å and a CVD nitride film with a thickness of about 100 Å is formed, and the insulating film deposited on the bottom of the hole is selectively removed by anisotropic etching. shows.

Figure 3b shows the selective epitaxial growth method.
The columnar hole portion is covered with a P-type single crystal silicon layer 321.
Next, a state in which an n-type single crystal silicon layer 302 is buried is shown. This state is the first state of the manufacturing method.
The structure shown in FIG. 1 can be obtained by going through the steps shown in FIG. 2 c and d.

Next, an embodiment of the fourth invention (manufacturing method) of the present application will be described with reference to FIG. 4.

FIG. 4a shows epitaxial growth after the state b in FIG. 2 or the state b in FIG. P-type single crystal silicon 40 with a thickness of about 2 μm and a concentration of about 2 × 10 ¹⁶ cm ^-3 was prepared by
7 is formed over the entire surface. Due to the heating at this time, impurities from the n-type columnar region 402 with a concentration of about 10 ¹⁸ cm ^-3 or higher are diffused, and a part of the bottom of the P-type single crystal silicon 407 in contact with the upper surface of the n-type region becomes n. The mold area 410 is converted.

FIG. 4b shows P-type single crystal silicon 407 in a region that is in contact with a portion of the upper surface of two vertically adjacent n-type columnar regions 402 and a portion of the upper surface of a P-type silicon substrate 401 sandwiched between them. The figure shows a state in which the epitaxially grown layer in other regions is removed by anisotropic etching. 407 is a channel of a control capacitance n-channel MOS transistor.

Fig. 4c shows a silicon oxide film 409 formed on the entire exposed silicon surface by thermal oxidation or the like.
The formed state is shown at 200 Å. Since the sidewalls of the P-type single crystal silicon 407 constitute a MIS transistor, the silicon oxide film on the sidewalls becomes a gate insulating film.

Regarding the film thickness on the horizontal plane, a thick silicon oxide film may be formed separately from the gate film in order to reduce the capacitance with the gate electrode. Figure 4 d shows high concentration of n.
A polycrystalline silicon layer doped with type impurities and having a thickness of about 2 μm was deposited by CVD or the like, and then formed as a gate electrode 406 . Thereafter, arsenic or the like is added to the P-type silicon single crystal growth layer 40 by ion implantation.
7 is doped with a thickness of about 0.3 μm to form a highly concentrated n ⁺ layer 408 that will serve as an electrode of an MIS transistor. Thereafter, an interlayer insulating film is applied, and aluminum wiring to serve as a bit line is formed in the n ⁺ layer to obtain the structure shown in FIG.

Next, an embodiment of the fifth invention (manufacturing method) of the present application will be described with reference to FIG.

FIG. 5a shows that the state shown in FIG. 2b or the state shown in FIG. Afterwards, a silicon oxide film 505 with a thickness of 1000 Å is formed on the entire surface by thermal oxidation or the like, and a part or all of the upper surface of each of the two columnar n-type single crystal regions 502 and the P-type silicon sandwiched between them are formed. Area 5
03 shows a state in which an opening is provided across the top surface.

FIG. 5b shows a film formed on the opening by selective epitaxial growth to a thickness of about 2 μm and a concentration of 2×10 ¹⁶
After forming a P-type silicon layer 507 with a thickness of approximately cm ^-3 , the silicon oxide film 505 is removed and boron 505 is applied over the entire exposed silicon surface using a normal thermal diffusion method.
P-type doped layer 5 diffused to a concentration of approximately ×10 ¹⁶ cm ^-3
23 (which becomes a channel stopper) is shown. At this time, a high concentration of n of about 10 ¹⁸ cm ^-3 or more
The exposed top surface of the type columnar region 502 is maintained without being converted to P type, and the portion of the bottom surface of the P type epitaxial growth layer 507 that is in contact with the top surface of the n type columnar region 502 is coated with n from the n type columnar region. An n-type doped layer 510 is formed by diffusion of the type impurity. It is not necessary to remove the silicon oxide film when diffusing boron.

FIG. 5c shows a state in which the recesses between the epitaxially grown layers are filled with a silicon oxide film 511 by a vapor phase growth method, an RF bias sputtering method, a silica coating method, or the like.

Next, on the top surface of the ^P -type silicon growth layer,
An n ⁺ type doped layer 508 of about ^-3 or more is formed by ion implantation of arsenic or the like. After this, n-type columnar region 5
By removing portions of the silicon 507, 523, and 510 on 02 and a portion of the silicon oxide film filling the recessed portions, grooves extending in the lateral direction are provided. On the side surface of the silicon layer after etching, the P-type doped layer 523 is removed and the P-type silicon layer 507 is exposed. After forming a thin silicon oxide film 509 that will become a gate film on the side surfaces and the exposed silicon surface of the lower layer by thermal oxidation, a polycrystalline silicon layer with a thickness of about 2 μm doped with n-type impurities at a high concentration is placed in the groove as a gate electrode. CVD as 506
form by law. (FIG. 5d) After that, an interlayer insulating film is applied, and an aluminum wiring to serve as a bit line is formed in the n ⁺ layer to obtain the structure shown in FIG. 1. A slight difference between the case of FIG. 1 and this example is the presence of a P-type doped layer 523, and because of this doped layer, the leakage current suppression effect of the parasitic MIS transistor formed on the sidewall of the epitaxial growth layer is reduced. can be expected.

Although one embodiment of the present invention has been described above, the same effect can be obtained even if the P type and n type of the embodiment are replaced.

Furthermore, instead of polycrystalline silicon, the gate electrodes 107 and 207 are made of high melting point metals such as tungsten, molybdenum, ketane, or silicides thereof.
Furthermore, it is possible to use a multilayer structure thereof. However, in the case of a high melting point metal, a thin insulating film 10
9,209 cannot be formed by thermal oxidation method.
It is necessary to use CVD method etc.

Further, in the above embodiment, a case is shown in which MIS capacitance is mainly used as the power storage capacitance, but it is obvious that there may be no MIS capacitance and all Pn junction capacitances may be used.

Further, in the above embodiment, the buried layers 103, 20
3, 302, 402, 503, silicon layer 107, 2 formed across the buried layer and columnar structure
07, 407, and 507 were all made of single crystal silicon. However, polycrystalline silicon may be used if leakage current and the like are not a problem. Alternatively, both may be combined.

In other words, a two-step growth method may be used in which monocrystalline silicon is selectively epitaxially grown halfway, and then polycrystalline silicon of the same conductivity type is grown.

(Effects of the Invention) As a result, in this example, a dynamic MIS semiconductor memory element can be created with a design rule of 1.5 μm in a small area of 3 μm x 3.75 μm pitch, and the capacitor area for power storage is 30 μm. ² can be made large enough. Therefore, it was found that it can sufficiently withstand soft errors such as α-ray errors. Furthermore, the effective channel length of the control transistor can be made sufficiently large, approximately 1 μm or more, and the short channel effect can be suppressed.

Furthermore, the channel portion of the control transistor is electrically connected to the substrate via the P-type buried layer in the groove, and the channel portion is electrically connected to the substrate through the P-type buried layer in the groove. There are no concerns about potential oscillations or bipolar operation.

If the present invention is applied to a 1.5 μm design rule and a 1 megabit storage circuit is created, the area of only the memory element portion will be 11.6 mm ² (3.04 mm x 3.80 mm), which is 4 using a 1 μm design rule.
In the case of megabits, the size is 20.6mm ² (4.06mm x 5.07mm), and it was found that even including peripheral circuits, it could be accommodated in a package about the same size as a current 64KDRAM package.

[Brief explanation of drawings]

FIG. 1 is a partially cutaway perspective view showing one embodiment of the structure of the present invention, and FIGS. 2 to 5 are partially cutaway perspective views showing an embodiment of the manufacturing method of the present invention. In the figure, 101, 201, 301, 401
...p-type silicon substrate, 102, 202, 30
2,402,502...N-type columnar single crystal silicon, 103,203,503...Buried p
Type silicon, 104, 204, 304... Insulating thin film, 105, 205, 505... Insulating film, 10
6,206,506...n-type silicon layer, 10
7,207,407,507...p-type silicon stack, 108,208,408,508...n-type silicon stack, 109,209,409,509...
...Thin insulating film, 110, 210, 410, 510
...n-type silicon part, 111, 211, 511...
...Interlayer insulating film, 112, 212...Metal, 321
...N-type silicon stack, 523...P-type doped layer.

Claims (1)

[Claims] 1. A columnar structure made of a first silicon layer of a second conductivity type is provided on the surface of a silicon single crystal substrate of a first conductivity type, and further around the columnar structure there is an electrical connection between the substrate and the columnar structure. a first silicon of a first conductivity type connected to the columnar structure and whose upper surface is substantially the same as the upper surface of the columnar structure; is provided or is not provided at all, and the first conductive material spans at least a portion of the upper surface of the first silicon of the first conductivity type and a portion of the upper surface of the columnar structure on both sides thereof. A second silicon layer of the mold is provided, an insulating film is provided on the other upper surface, a thin insulating film is formed on one side of the second silicon layer, and a conductor layer is provided in contact with the thin insulating film. and a second conductivity type layer is provided on the upper surface of the second silicon layer. 2 (a) For a single crystal silicon layer of a second conductivity type formed on a single crystal silicon substrate of a first conductivity type, remove the silicon layer until it reaches the substrate, leaving a desired region in a columnar shape; (b) covering the exposed silicon surface with an insulating film; (c) selectively removing the insulating film on the top surface of the silicon substrate outside the columnar region; burying the first single crystal or polycrystalline silicon of the first conductivity type, or a combination thereof; (e) covering the entire surface with an insulating film; and (f) covering part of the upper surface of the columnar part and the upper surface of the buried layer in the recess A conductor layer that becomes a gate electrode is formed over a part of the conductor layer, (g) a gate insulating film is deposited on the side surface of the conductor layer, and (h) the silicon surface on the top surface of the columnar part that is not covered with the conductor layer and the adjacent conductor are formed. Both parts of the silicon surface of the upper surface of the buried layer that are not covered with the layer are exposed by selectively etching the insulating film shown in (e) above, and (li) at least a layer is formed on the exposed silicon surface. forming a second single-crystalline or polycrystalline silicon layer of the first conductivity type; (v) adding impurities to the upper surface of the silicon layer to form a second conductivity type diffusion layer to such an extent that it overlaps with the gate electrode; A method for manufacturing a semiconductor memory element characterized by: 3 (a) Removing the silicon layer in a desired region of the first conductivity type single crystal silicon substrate to a desired depth,
Forming a columnar hole, (b) covering the exposed silicon surface with an insulating film, (c) removing the insulating film from the bottom of the columnar hole or the part including it, and (d) covering the part halfway up to almost the top of the hole. embedded with silicon single crystal or polycrystalline silicon or a combination thereof having an impurity distribution that changes from the first conductivity type to the second conductivity type, (e) covering the entire upper surface with an insulating film, and (f) the columnar portion Forming a conductor layer to serve as a gate electrode over a part of the outer upper surface and a part of the upper surface of the buried layer in the recess, (g) depositing a gate insulating film on the side surface of the conductor layer, and (h) covering with the conductor layer. selectively etching the insulating film shown in (e) above on both the silicon surface on the upper surface outside the columnar part which is not covered with the conductor layer and the part of the silicon surface on the upper surface of the buried layer adjacent thereto which is not covered with the conductor layer. (i) forming a second monocrystalline or polycrystalline silicon layer of the first conductivity type on at least the exposed silicon surface; A method for manufacturing a semiconductor memory element, comprising: forming a conductive type diffusion layer to such an extent that it overlaps with the gate electrode. 4 (a) For a single crystal silicon layer of a second conductivity type formed on a single crystal silicon substrate of a first conductivity type, remove the silicon layer until it reaches the substrate, leaving a desired region in a columnar shape; (b) covering the exposed silicon surface with an insulating film, (c) selectively removing the insulating film on the top surface of the silicon substrate outside the columnar region from the substrate, and (d) forming a recess almost up to the top surface of the columnar part. embedding the first single-crystal or polycrystalline silicon of the first conductivity type, or a combination thereof, or instead of (a) to (d), Remove the silicon layer in the region to a desired depth, create a columnar hole, (f) cover the exposed silicon surface with an insulating film, and (g) remove the bottom of the columnar hole or the part containing it. (H) Filling the hole almost up to the top surface with silicon single crystal or polycrystalline silicon, or a combination thereof, having an impurity distribution that changes from the first conductivity type to the second conductivity type midway through the hole; (i) A silicon layer of the first conductivity type is grown on the entire surface, single crystal silicon is epitaxially grown on at least the single crystal silicon, and a silicon layer of the first conductivity type is grown epitaxially on the second conductivity type region. , the bottom of the first conductivity type layer is the second conductivity type layer.
(N) Next, the single crystal silicon layer of the first conductivity type in the region including the substrate of the first conductivity type and the buried layer of the second conductivity type is left (released). (l) grow a thin insulating film on the exposed silicon surface; (v) then deposit the first and A conductor that will become the gate electrode is attached to a portion including the second conductivity type region, and (iv) an impurity is added to the upper surface of the first conductivity type silicon layer, so that the second conductivity type diffusion layer is connected to the gate electrode. A method for manufacturing a semiconductor memory element, characterized in that the semiconductor memory element is formed to such an extent that it overlaps with the semiconductor memory element. 5 (a) For a single crystal silicon layer of a second conductivity type formed on a single crystal silicon substrate of a first conductivity type, remove the silicon layer until it reaches the substrate, leaving a desired region in a columnar shape; (b) covering the exposed silicon surface with an insulating film; (c) selectively removing the insulating film on the top surface of the silicon substrate outside the columnar region; Embed the first single crystal or polycrystalline silicon of the first conductivity type, or a combination thereof, or instead of (a) to (d), (e) embed the desired silicon substrate on the first conductivity type single crystal silicon substrate. Remove the silicon layer in the region to a desired depth, create a columnar hole, (f) cover the exposed silicon surface with an insulating film, and (g) remove the bottom of the columnar hole or the part containing it. (H) Filling the hole up to the surface with silicon single crystal or polycrystalline silicon, or a combination thereof, having an impurity distribution such that the conductivity type changes from the first conductivity type to the second conductivity type along the way; (i) Depositing an insulating material on the surface of the structure, (iii) providing an opening containing the first and second conductive layer regions under the insulating material, and depositing the first conductive layer in the opening. (e) growing silicon of the first conductivity type on the underlying second conductivity type region so that the bottom of the first conductivity type layer becomes the second conductivity type; Adding impurities, (W) burying an insulator in the surface recesses, (F) forming a second conductive region on the exposed silicon surface, and (Y) forming an upper layer existing in the portion containing the second conductive region in the lower layer. A semiconductor memory element characterized in that a region including a part of the silicon region is removed, (t) a game insulator is formed on the surface thereof, and (v) a conductor serving as a gate electrode is embedded in a recessed part of the surface. Production method.