JPH0435912B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic MIS semiconductor memory element and a method for manufacturing the same.

(Prior art and its problems) In recent years, there has been a strong trend towards higher integration and higher density of semiconductor memory elements, and along with this, the miniaturization of elements is progressing. We are facing various technical difficulties in many aspects, including the following. In particular, dynamic random access memory (hereinafter abbreviated as DRAM)
In a one-transistor memory cell consisting of one transistor and one storage capacitor, which is a typical structure of the Although the technique is being considered, "A
CORRUGATED CAPACITANCE CELL
(CCC) FOR MEGABIT DYNAMICMOS
H.SUNAMI titled “MEMORIES”
In a paper published by et. Although the element area is significantly smaller than that of a memory element, the element area, including the surrounding isolation area, is approximately
It is about 21 square microns, and if you try to create a 4-megabit memory circuit using this structure, the memory element alone will be about 88 square millimeters, which is quite large.

(Objective of the Invention) The present invention eliminates these conventional drawbacks, dramatically reduces the device area compared to conventional devices with the same design standards, and furthermore, the channel portion of the control transistor is electrically connected to the substrate. An object of the present invention is to provide a semiconductor memory element and a method for manufacturing the same.

(Structure of the Invention) According to the present invention, the first impurity doped layer of the second conductivity type is formed on a part of the side surface on the silicon single crystal substrate of the first conductivity type, and the impurity layer of the second conductivity type is doped on the upper surface. It has a columnar structure composed of a first conductivity type single crystal silicon layer having a second conductivity type second impurity doped layer that is not continuous with the doped layer, and at least the surface of the first impurity doped layer. A portion of the columnar structure is covered with an insulating film or a surface is not covered with an insulating film, and the periphery of the columnar structure is made of first conductivity type silicon electrically connected to the substrate single crystal silicon. The impurity doped layer is buried halfway, an insulating film is formed on the top surface of this buried layer, and a gate insulating film is formed on the side surface of the columnar structure that is not covered with the buried layer. A semiconductor memory element characterized in that it has a conductor layer that spans the first and second impurity doped layers of the second conductivity type and serves as a gate electrode is obtained.

Furthermore, according to the present invention, a desired region is etched deeper than the silicon layer by etching a single crystal silicon layer of the second conductivity type formed on the single crystal silicon substrate of the first conductivity type. A desired region is left deeper than this silicon in a columnar shape, ○B The exposed silicon surface is covered with an insulating film, and only the insulating film deposited on the etched bottom surface is selectively etched away, ○H The substrate is further etched deeply, and the exposed silicon surface is doped with impurities of the second conductivity type using the insulating film formed in step ○B as a mask, and the surface is covered with a thin insulating film, ○E around the columnar structure. The thin insulating film and the impurity doped layer of the second conductivity type, which are also formed on the bottom surface of the silicon substrate in which the trenches are etched, are selectively etched away, and the silicon of the first conductivity type is deposited in the grooves to form the columnar structure. ○T An insulating film is formed on the surface of the buried layer, and an insulating film on one side of the columnar structure is buried from the surface to the above. etching and removing the second conductivity type impurity doped layer to the upper end thereof to expose the silicon surface and forming a gate insulating film there; A conductor layer serving as a gate electrode is formed spanning the side surface of the second conductivity type impurity doped layer provided on the upper part of the structure.

A method for manufacturing a semiconductor memory element is obtained.

Furthermore, according to the present invention, ○a) the single crystal silicon substrate of the first conductivity type is etched leaving a desired region in the form of a column, ○b) the side surface of the columnar structure silicon is doped with an impurity of the second conductivity type, and the surface thereof is etched. Covering with a thin insulating film, ○C Selectively etching and removing the thin insulating film and the second conductivity type impurity doped layer, which are also formed on the bottom surface of the silicon substrate dug around the columnar structure, ○D. burying silicon of the first conductivity type in the groove until the upper end of the impurity doped layer of the second conductivity type provided on the side surface of the columnar structure is left; ○e forming an insulating film on the surface of the buried layer; A single crystal silicon layer of a first conductivity type is selectively formed on the top surface of the structure, and a single crystal silicon layer of a second conductivity type is selectively formed on the top surface of the structure; A gate insulating film is formed spanning the formed single crystal silicon layer of the second conductivity type and the upper end of the second conductivity type impurity doped layer; Forming a conductor layer to serve as a gate electrode, spanning over the side surface of the second conductivity type impurity doped layer selectively formed in step ○ and the upper end of the second conductivity type impurity dope layer formed on the side surface of the columnar structure formed in step ○○○. A characteristic method for manufacturing a semiconductor memory element is obtained.

(Example) Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a partially cutaway perspective view showing an embodiment of the first invention of the present application, showing a memory element for 4 bits. 101 is a single-crystal p-type silicon substrate, 102 is a p-type silicon single crystal with a columnar structure perpendicular to the substrate 101, and 103 is a p-type silicon substrate 101 provided on the lower part of the surface of the side wall of the columnar structure.
Alternatively, the n-type impurity doped layer 104 that forms a junction capacitance with the p-type silicon 102 provided in a form that is electrically connected thereto is an insulating thin film that covers at least a part of the surface of the impurity doped layer 103; A MIS capacitor is formed between the p-type silicon 105 and the p-type silicon 105. 106 is an n-type impurity doped layer formed at the top of the columnar structure, and this doped layer and 103
and constitute the source and drain electrodes of the control MIS transistor. The p-type silicon 102 between these two doped layers constitutes a channel portion. In this way, a control MIS transistor is formed on the upper side of one pillar, and a storage capacitor is formed on the lower side, and the channel portion of the transistor is electrically connected to the substrate.
107 is a silicon oxide film that fills the remaining part of the trench, 109 is a gate insulating film, and 108 is two n-type impurity doped layers 10 in contact with the gate insulating film.
3 and 106 is n ⁺ type polycrystalline silicon that constitutes the gate electrode of the control MIS transistor and serves as a word line. Reference numeral 110 is a metal and is connected to the n-type doped layer to form a bit line.

In this way, a dynamic memory cell is constructed.

The insulating thin film 104 forming the MIS capacitor completely covers the pn junction with the p-type silicon substrate 104a.
Cases such as 104b and 104b where the pn junction is not completely covered may occur during the step of partially removing the insulating thin film. The storage capacity is a composite capacity of MIS type capacitance and junction type capacitance, and in the case of the former, MIS
The area of the mold and the area of the joint mold are approximately equal, and in the latter case, most of the mold is the joint mold. These 2
The two capacitances are the area represented by the product of the peripheral length of the columnar structure, the overlap height of the n-type impurity doped layer 103 and the p-type buried layer 105, and the area where the n-type impurity doped layer 103 is in contact with the p-type layer 102. increases according to the sum of Therefore, even if the cross-sectional area of the columnar structure portion is made small, there is an advantage that a sufficiently large storage capacity can be obtained by increasing the dimension in the depth direction, that is, the height direction of the substrate.

If this structure is used, when the design standard is F,
The minimum occupied area can be reduced to 6F ² (2F x 3F), making it possible to achieve high density. Furthermore, the channel part of the control transistor is connected to the p-type substrate via the p-type part at the center of the columnar structure, and problems that may occur if the channel part is floating from the substrate (such as charge increase in the channel, threshold This has the advantage of avoiding voltage instability, etc.).

Hereinafter, a more specific example of this embodiment will be described with reference to FIG. 2 together with the second invention (manufacturing method) of the present application.

First, using a substrate in which an n-type impurity doped layer 206 with a thickness of about 0.5 μm is formed on a p-type single crystal silicon substrate 201 with a concentration of about 5×10 ¹⁶ cm ^-3 , a thick SiO ₂
Using an appropriate mask material such as a film pattern, etching the area of the substrate where you want to form a memory cell by about 2 μm by anisotropic etching such as reactive ion etching (RIE), and etching the area with a pitch of 3 μm in the horizontal direction and 4.5 μm in the vertical direction. A 1.5 μm x 1.5 μm prismatic pattern arranged at μm pitch was formed. Thereafter, the exposed silicon surface was covered with an insulating film 211 such as a silicon oxide film, and only the insulating film on the bottom of the dug silicon trench was selectively removed (FIG. 2a).

Next, after the silicon trench is further dug by approximately 6 μm using RIE, an n-type impurity doped layer 203 is shallowly formed on a part of the side surface of the columnar structure by thermal diffusion of arsenic, etc. (Fig. 2b) ).

Next, the n-type impurity doped layer that is also formed on the bottom surface of the silicon trench dug by the thermal diffusion is selectively removed by anisotropic etching, and then a thin insulating film, such as a thermal oxide film or a thermal oxide film, that will become the MIS capacitor is etched. and
A stack 204 with CVD nitride is formed on the exposed silicon surface. Thereafter, the insulating film deposited also on the bottom of the silicon trench was selectively removed by anisotropic etching (FIG. 2c). If the anisotropy of the etching is slightly poor or the columnar structure is slightly slanted, a portion of the insulating thin film at the bottom of the sidewall will be removed as shown in FIG. 104b. FIG. 2d shows a state in which the dug silicon trench is filled with a p-type silicon layer 205 of about 5 μm by selective epitaxial growth. As a filling method, a p-type polycrystalline silicon film may be grown in a vapor phase and then etched back, or this method may be combined with selective epitaxy. Figure 2e shows that after filling the remaining groove with a silicon oxide film 207 using CVD, RF bias sputtering, or silica glass coating, two n-type impurity doped layers 203 and 206 are separated. This shows a state in which a groove 212 with a depth of about 2.5 μm is formed so as to straddle and contact the surface of a part of the p-type columnar silicon 202 that is continuous with the substrate. Next, as shown in FIG. 1, a gate insulating film 109 is formed on the side wall portion of the columnar structure where the silicon surface is exposed, and a gate electrode 1 is formed.
A conductive film such as n ⁺ polycrystalline silicon having a conductive film of 0.08 is buried in the groove formed in FIG.
By applying 0 to the n-type impurity doped layer 106, a dynamic memory cell with a new structure is obtained.

If there is a risk of leakage occurring in the n-channel MOS transistor, fill in boron glass (BSG) instead of the silicon oxide film 207 and fill the trench 2.
After forming the gate electrode 108, heat treatment is performed to form the gate electrode 108.
What is necessary is to dope boron into the silicon in the region that is not in contact with the silicon.

Next, a third embodiment (manufacturing method) of the present application will be described with reference to FIG.

First, a p-type single crystal silicon substrate 301 with an impurity concentration of about 5×10 ¹⁶ cm ^-3 is used, and anisotropic etching such as reactive ion etching (RIE) is performed using an appropriate mask material such as a thick SiO ₂ film pattern. The area of the substrate where you want to form the memory cell is etched.
It is dug to a depth of about 6 μm to form a prismatic pattern having the same dimensions in the plane direction as in the above embodiment. After this, an n-type impurity doped layer 303 is formed shallowly on the side surface of the columnar structure by thermal diffusion of arsenic, etc., and an insulating thin film 304 that becomes the MIS capacitor is formed on the surface, such as a thermal oxide film or a stack of a thermal oxide film and a CVD nitride film. Forms a film. (Figure 3a).

Next, the insulating film deposited also on the bottom surface of the silicon trench and the n-type impurity doped layer covered therewith are selectively removed by anisotropic etching, and then the trench is etched with SiH A p-type silicon layer 305 is buried by about 5 μm by selective epitaxial growth using ₂ Cl ₂ and HCl as raw material gases, and the upper part of the buried layer is further covered with a silicon oxide film 307. (Figure 3b).

Next, the top surface of the columnar structure is exposed, and a p-type silicon stack 322 with a thickness of 1 μm and an n ⁺ type silicon stack 306 with a thickness of 0.5 μm are successively formed by selective epitaxial growth (FIG. 3c). . At this time, it is of course possible to form a p-type silicon stack with a thickness of 1.5 μm and form an n ⁺ layer on the top surface by implanting arsenic ions or the like. The state in Figure 3c is the second
In terms of the figure, this corresponds to an intermediate state between figure d and figure e.
Therefore, the latter part of the embodiment of the second invention of the present application can be used for the following steps. In this embodiment, as shown in FIG. 3c, a p-type silicon stack 322,
An n ⁺ type silicon laminated layer 306 was formed on the entire upper surface of the columnar structure. However, these two laminated layers may be formed only on a portion of the upper surface of the columnar structure. However, the p-type silicon stack 322 must be electrically connected to at least a portion of the p-type portion on the upper surface of the columnar structure. Even in this embodiment, if there is a risk of leakage occurring in the transistor, boron can be doped as in the previous embodiment.

Although the present invention has been described above based on one embodiment, the same effect can be obtained even if the p-type and n-type of the embodiment are replaced.

Further, instead of polycrystalline silicon, the gate electrode 108 can be made of a high melting point metal such as tungsten, molybdenum, or titanium, or a silicide thereof, or a multilayer structure thereof. Since it is normally desirable that the work function φ _M of the gate electrode be constant over the channel, it is preferable to form multiple layers so that the portion of the gate electrode that spans the channel and the other portions are made of a constant material.

(Effect of the invention) As a result, in this example, 3 μm×4.5 μm (=13.5 μm
A dynamic MIS semiconductor memory element can be fabricated in a small area of 1.5 μm (m ² ) with a design rule of 1.5 μm, and the storage capacitor area alone can be sufficiently large to 30 μm ² . If the pn junction capacitance is also added, it becomes even larger. Therefore, it was found that it can sufficiently withstand soft errors such as α-ray errors. Furthermore, the effective channel length of the control transistor can be made sufficiently large, approximately 1 μm or more, and the short channel effect can be suppressed. Furthermore, the channel section of the control transistor is electrically connected to the substrate through the center of the columnar structure, and the channel section potential oscillates due to the charge pumping phenomenon that occurs when the channel section is floating from the substrate. There are no concerns about bipolar operation.

If the present invention is applied to a 1.5 μm design rule and a 1 megabit memory circuit is manufactured, the area of only the memory element portion will be 14.1 mm ² (3.07 mm x 4.61 mm), and in the case of 4 megabits using a 1 μm design rule, the area will be 25.2 mm ² ( 4.10mm×6.14mm)
Therefore, even including peripheral circuits, the current 64KDRAM
It turned out that it could be stored in something about the same size as a package cage.

[Brief explanation of drawings]

FIG. 1 is a partially cutaway perspective view showing one embodiment of the structure of the present invention, FIGS. 2 a-e, and 3 a-c.
FIG. 2 is a partially cutaway perspective view showing an example of the manufacturing method of the present invention. In the figure, 101, 201, 301... p-type silicon substrate, 102, 202... p-type silicon columnar structure, 103, 203, 303... n-type impurity doped layer, 102, 202... p-type silicon columnar structure, 103,203...N-type impurity doped layer, 104,204...Insulating thin film, 105,20
5...P-type silicon buried layer, 106...N-type impurity doped layer, 107...Insulating film, 108...
Conductor film such as polycrystalline silicon, refractory metal or refractory metal silicide, 109... Insulating thin film, 1
10... Metal, 211... Insulating film, 212... Groove dug in insulating film, 104, 204, 304
...Insulating thin film, 105, 205, 305...p-type silicon layer, 106...n-type impurity doped layer, 3
06...N-type silicon stack, 107,307...
Insulating film, 108... Conductor film, such as polycrystalline silicon, refractory metal, or refractory metal silicide, 10
9... Insulating thin film, 110... Metal, 211... Insulating film, 212... Groove dug into insulating film, 32
2...P-type silicon stack.

Claims (1)

[Claims] 1. A silicon single crystal substrate of a first conductivity type, having a first impurity doped layer of a second conductivity type on a part of a side surface, and a layer doped with an impurity of a second conductivity type on an upper surface. It has a columnar structure composed of a first conductivity type single crystal silicon layer having a second conductivity type second impurity doped layer that is not continuous, and at least a part of the surface of the first impurity doped layer is insulated. a first impurity-doped layer of silicon of a first conductivity type, which is covered with a film or whose surface is not covered with an insulating film, and the periphery of the columnar structure is electrically connected to the substrate single crystal silicon; is buried halfway, an insulating film is formed on the top surface of this buried layer, a gate insulating film is formed on the side surface of the columnar structure that is not covered with the buried layer, and a second conductive film is in contact with this gate insulating film. 1. A semiconductor memory element comprising a conductor layer that spans first and second impurity-doped layers and serves as a gate electrode. 2 ○a A monocrystalline silicon layer of a second conductivity type is formed on a single-crystal silicon substrate of a first conductivity type, and etching is performed to leave a desired region deeper than this silicon layer in a columnar shape, ○ (b) Covering the exposed silicon surface with an insulating film, selectively etching away only the insulating film deposited on the etched bottom surface, (c) Etching the substrate even more deeply, (d) Step (b) Using the insulating film formed in step 1 as a mask, the exposed silicon surface is doped with impurities of the second conductivity type, and that surface is covered with a thin insulating film. selectively etching and removing the thin insulating film and the second conductivity type impurity doped layer; burying the doped layer until the upper end remains, ○g forming an insulating film on the surface of the buried layer, ○ch removing the insulating film on one side of the columnar structure from the surface to the upper end of the second conductivity type impurity doped layer; to expose the silicon surface and form a gate insulating film there; ○ri a second conductive type impurity doped layer in contact with the gate insulating film and provided on the upper end of the second conductive type impurity doped layer and on the top of the columnar structure; A conductor layer serving as a gate electrode is formed spanning the side surfaces. A method of manufacturing a semiconductor memory element, characterized in that: 3 ○B Etching the single crystal silicon substrate of the first conductivity type leaving a desired region in the form of a column, ○B Doping the side surface of the columnar structure silicon with an impurity of the second conductivity type, covering the surface with a thin insulating film, ○C. Selectively etching and removing the thin insulating film and the second conductivity type impurity doped layer formed also on the bottom surface of the silicon substrate dug around the columnar structure, ○D. embedding silicon of the second conductivity type impurity doped layer provided on the side surface of the columnar structure until the upper end remains; ○E forming an insulating film on the surface of the buried layer; ○F a first conductor on the top surface of the columnar structure; A single crystal silicon layer of the first conductivity type and a second conductivity type single crystal silicon layer formed thereon are selectively formed on the upper surface thereof, and A gate insulating film is formed across the three sides of the single crystal silicon layer of the mold and the upper end of the second conductivity type impurity doped layer, and is selectively formed on the top of the columnar structure in contact with the insulating film. A semiconductor memory element characterized in that a conductive layer serving as a gate electrode is formed over the side surface of the second conductivity type impurity doped layer and the upper end of the second conductivity type impurity doped layer on the side surface of the columnar structure formed in step ○○○. manufacturing method.